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authorMike Frysinger <vapier.adi@gmail.com>2008-08-06 05:05:20 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-06 05:05:20 -0400
commit778307d372555f979cf6cef112a6d7fbff056cd9 (patch)
tree6ab304d2f1ef333f48b56eb2913268fe9dfc9714 /include/asm-blackfin
parentd6a29891369827317659b7833170d2f5f0c7b97f (diff)
Blackfin arch: remove support for Anomaly 05000125 as it doesnt exist on any supported processor/silicon
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin')
-rw-r--r--include/asm-blackfin/mach-common/cdef_LPBlackfin.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index ede210eca4ec..d39c396f850d 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -39,11 +39,7 @@
39#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) 39#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) 40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) 41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
42#if ANOMALY_05000125
43extern void bfin_write_DMEM_CONTROL(unsigned int val);
44#else
45#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) 42#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
46#endif
47#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) 43#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
48#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) 44#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
49#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) 45#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
@@ -129,11 +125,7 @@ extern void bfin_write_DMEM_CONTROL(unsigned int val);
129#define DTEST_DATA3 0xFFE0040C 125#define DTEST_DATA3 0xFFE0040C
130*/ 126*/
131#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) 127#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
132#if ANOMALY_05000125
133extern void bfin_write_IMEM_CONTROL(unsigned int val);
134#else
135#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) 128#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
136#endif
137#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) 129#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
138#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val) 130#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
139#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) 131#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)