Blackfin arch: Start untangling the CPLB handling code.

 - Move cache initialization to C from assembly.
 - Move anomaly workaround for writing [ID]MEM_CONTROL to assembly, so
   that we don't have to mess around with .align directives in C source.
 - Fix a bug where bfin_write_DMEM_CONTROL would write to IMEM_CONTROL
 - Break out CPLB related code from kernel/setup.c into their own file.
 - Don't define variables in header files, only declare them.

Signed-off-by: Bernd Schmidt <bernd.schmidt@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>

2 files changed, 15 insertions, 141 deletions

diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index e14ea397cdbb..bec6ecdf1bdb 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -57,8 +57,8 @@ struct cplb_tab {
         u16 size;
 };
 
-u_long icplb_table[MAX_CPLBS+1];
-u_long dcplb_table[MAX_CPLBS+1];
+extern u_long icplb_table[MAX_CPLBS+1];
+extern u_long dcplb_table[MAX_CPLBS+1];
 
 /* Till here we are discussing about the static memory management model.
  * However, the operating envoronments commonly define more CPLB
@@ -70,134 +70,27 @@ u_long dcplb_table[MAX_CPLBS+1];
  */
 
 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
-u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
-u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
+extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
+extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
 
 #ifdef CONFIG_CPLB_INFO
-u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
-u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
+extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
+extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
 #endif /* CONFIG_CPLB_INFO */
 
 #else
 
-u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
-u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
+extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
+extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
 
 #ifdef CONFIG_CPLB_INFO
-u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
-u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
+extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
+extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
 #endif /* CONFIG_CPLB_INFO */
 
 #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
 
-struct s_cplb {
-        struct cplb_tab init_i;
-        struct cplb_tab init_d;
-        struct cplb_tab switch_i;
-        struct cplb_tab switch_d;
-};
+extern unsigned long reserved_mem_dcache_on;
+extern unsigned long reserved_mem_icache_on;
 
-#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
-static struct cplb_desc cplb_data[] = {
-        {
-                .start = 0,
-                .end = SIZE_1K,
-                .psize = SIZE_1K,
-                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf = SDRAM_OOPS,
-                .d_conf = SDRAM_OOPS,
-#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
-                .valid = 1,
-#else
-                .valid = 0,
-#endif
-                .name = "ZERO Pointer Saveguard",
-        },
-        {
-                .start = L1_CODE_START,
-                .end = L1_CODE_START + L1_CODE_LENGTH,
-                .psize = SIZE_4M,
-                .attr = INITIAL_T | SWITCH_T | I_CPLB,
-                .i_conf = L1_IMEMORY,
-                .d_conf = 0,
-                .valid = 1,
-                .name = "L1 I-Memory",
-        },
-        {
-                .start = L1_DATA_A_START,
-                .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
-                .psize = SIZE_4M,
-                .attr = INITIAL_T | SWITCH_T | D_CPLB,
-                .i_conf = 0,
-                .d_conf = L1_DMEMORY,
-#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
-                .valid = 1,
-#else
-                .valid = 0,
-#endif
-                .name = "L1 D-Memory",
-        },
-        {
-                .start = 0,
-                .end = 0,  /* dynamic */
-                .psize = 0,
-                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf =  SDRAM_IGENERIC,
-                .d_conf =  SDRAM_DGENERIC,
-                .valid = 1,
-                .name = "SDRAM Kernel",
-        },
-        {
-                .start = 0, /* dynamic */
-                .end = 0, /* dynamic */
-                .psize = 0,
-                .attr = INITIAL_T | SWITCH_T | D_CPLB,
-                .i_conf =  SDRAM_IGENERIC,
-                .d_conf =  SDRAM_DNON_CHBL,
-                .valid = 1,
-                .name = "SDRAM RAM MTD",
-        },
-        {
-                .start = 0, /* dynamic */
-                .end = 0,   /* dynamic */
-                .psize = SIZE_1M,
-                .attr = INITIAL_T | SWITCH_T | D_CPLB,
-                .d_conf = SDRAM_DNON_CHBL,
-                .valid = 1,//(DMA_UNCACHED_REGION > 0),
-                .name = "SDRAM Uncached DMA ZONE",
-        },
-        {
-                .start = 0, /* dynamic */
-                .end = 0, /* dynamic */
-                .psize = 0,
-                .attr = SWITCH_T | D_CPLB,
-                .i_conf = 0, /* dynamic */
-                .d_conf = 0, /* dynamic */
-                .valid = 1,
-                .name = "SDRAM Reserved Memory",
-        },
-        {
-                .start = ASYNC_BANK0_BASE,
-                .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
-                .psize = 0,
-                .attr = SWITCH_T | D_CPLB,
-                .d_conf = SDRAM_EBIU,
-                .valid = 1,
-                .name = "ASYNC Memory",
-        },
-        {
-#if defined(CONFIG_BF561)
-                .start = L2_SRAM,
-                .end = L2_SRAM_END,
-                .psize = SIZE_1M,
-                .attr = SWITCH_T | D_CPLB,
-                .i_conf = L2_MEMORY,
-                .d_conf = L2_MEMORY,
-                .valid = 1,
-#else
-                .valid = 0,
-#endif
-                .name = "L2 Memory",
-        }
-};
-#endif
+extern void generate_cpl_tables(void);
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index 58f878947cbc..94ed381e5606 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -40,16 +40,7 @@
 #define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
 #define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
 #ifdef ANOMALY_05000125
-static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        local_irq_save(flags);
-        __asm__(".align 8\n");
-        bfin_write32(IMEM_CONTROL, val);
-        __builtin_bfin_ssync();
-        local_irq_restore(flags);
-}
+extern void bfin_write_DMEM_CONTROL(unsigned int val);
 #else
 #define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
 #endif
@@ -139,17 +130,7 @@ static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
 */
 #define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
 #ifdef ANOMALY_05000125
-static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        local_irq_save(flags);
-        __asm__(".align 8\n");
-        bfin_write32(IMEM_CONTROL, val);
-        __builtin_bfin_ssync();
-        local_irq_restore(flags);
-
-}
+extern void bfin_write_IMEM_CONTROL(unsigned int val);
 #else
 #define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
 #endif