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authorBryan Wu <bryan.wu@analog.com>2007-05-06 17:50:22 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-07 15:12:58 -0400
commit1394f03221790a988afc3e4b3cb79f2e477246a9 (patch)
tree2c1963c9a4f2d84a5e021307fde240c5d567cf70 /include/asm-blackfin/mach-common/def_LPBlackfin.h
parent73243284463a761e04d69d22c7516b2be7de096c (diff)
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-blackfin/mach-common/def_LPBlackfin.h')
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h691
1 files changed, 691 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
new file mode 100644
index 000000000000..76103526aec1
--- /dev/null
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -0,0 +1,691 @@
1 /*
2 * File: include/asm-blackfin/mach-common/def_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
30
31#ifndef _DEF_LPBLACKFIN_H
32#define _DEF_LPBLACKFIN_H
33
34#include <asm/mach/anomaly.h>
35
36/*#if !defined(__ADSPLPBLACKFIN__)
37#warning def_LPBlackfin.h should only be included for 532 compatible chips.
38#endif
39*/
40
41#define MK_BMSK_(x) (1<<x)
42
43#if defined(ANOMALY_05000198)
44
45#define bfin_read16(addr) ({ unsigned __v; \
46 __asm__ __volatile__ ("NOP;\n\t"\
47 "%0 = w[%1] (z);\n\t"\
48 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
49
50#define bfin_read32(addr) ({ unsigned __v; \
51 __asm__ __volatile__ ("NOP;\n\t"\
52 "%0 = [%1];\n\t"\
53 : "=d"(__v) : "a"(addr)); __v; })
54
55#define bfin_write16(addr,val) ({\
56 __asm__ __volatile__ ("NOP;\n\t"\
57 "w[%0] = %1;\n\t"\
58 : : "a"(addr) , "d"(val) : "memory");})
59
60#define bfin_write32(addr,val) ({\
61 __asm__ __volatile__ ("NOP;\n\t"\
62 "[%0] = %1;\n\t"\
63 : : "a"(addr) , "d"(val) : "memory");})
64
65#else
66
67#define bfin_read16(addr) ({ unsigned __v; \
68 __asm__ __volatile__ (\
69 "%0 = w[%1] (z);\n\t"\
70 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
71
72#define bfin_read32(addr) ({ unsigned __v; \
73 __asm__ __volatile__ (\
74 "%0 = [%1];\n\t"\
75 : "=d"(__v) : "a"(addr)); __v; })
76
77#define bfin_write16(addr,val) ({\
78 __asm__ __volatile__ (\
79 "w[%0] = %1;\n\t"\
80 : : "a"(addr) , "d"(val) : "memory");})
81
82#define bfin_write32(addr,val) ({\
83 __asm__ __volatile__ (\
84 "[%0] = %1;\n\t"\
85 : : "a"(addr) , "d"(val) : "memory");})
86
87#endif
88
89/**************************************************
90 * System Register Bits
91 **************************************************/
92
93/**************************************************
94 * ASTAT register
95 **************************************************/
96
97/* definitions of ASTAT bit positions*/
98
99/*Result of last ALU0 or shifter operation is zero*/
100#define ASTAT_AZ_P 0x00000000
101/*Result of last ALU0 or shifter operation is negative*/
102#define ASTAT_AN_P 0x00000001
103/*Condition Code, used for holding comparison results*/
104#define ASTAT_CC_P 0x00000005
105/*Quotient Bit*/
106#define ASTAT_AQ_P 0x00000006
107/*Rounding mode, set for biased, clear for unbiased*/
108#define ASTAT_RND_MOD_P 0x00000008
109/*Result of last ALU0 operation generated a carry*/
110#define ASTAT_AC0_P 0x0000000C
111/*Result of last ALU0 operation generated a carry*/
112#define ASTAT_AC0_COPY_P 0x00000002
113/*Result of last ALU1 operation generated a carry*/
114#define ASTAT_AC1_P 0x0000000D
115/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
116#define ASTAT_AV0_P 0x00000010
117/*Sticky version of ASTAT_AV0 */
118#define ASTAT_AV0S_P 0x00000011
119/*Result of last MAC1 operation overflowed, sticky for MAC*/
120#define ASTAT_AV1_P 0x00000012
121/*Sticky version of ASTAT_AV1 */
122#define ASTAT_AV1S_P 0x00000013
123/*Result of last ALU0 or MAC0 operation overflowed*/
124#define ASTAT_V_P 0x00000018
125/*Result of last ALU0 or MAC0 operation overflowed*/
126#define ASTAT_V_COPY_P 0x00000003
127/*Sticky version of ASTAT_V*/
128#define ASTAT_VS_P 0x00000019
129
130/* Masks */
131
132/*Result of last ALU0 or shifter operation is zero*/
133#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
134/*Result of last ALU0 or shifter operation is negative*/
135#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
136/*Result of last ALU0 operation generated a carry*/
137#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
138/*Result of last ALU0 operation generated a carry*/
139#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
140/*Result of last ALU0 operation generated a carry*/
141#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
142/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
143#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
144/*Result of last MAC1 operation overflowed, sticky for MAC*/
145#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
146/*Condition Code, used for holding comparison results*/
147#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
148/*Quotient Bit*/
149#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
150/*Rounding mode, set for biased, clear for unbiased*/
151#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
152/*Overflow Bit*/
153#define ASTAT_V MK_BMSK_(ASTAT_V_P)
154/*Overflow Bit*/
155#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
156
157/**************************************************
158 * SEQSTAT register
159 **************************************************/
160
161/* Bit Positions */
162#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
163#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
164#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
165#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
166#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
167#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
168#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
169 * set by IDLE instruction.
170 */
171#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
172 * reset was a software reset
173 * (=1)
174 */
175#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
176#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
177#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
178#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
179#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
180/* Masks */
181/* Exception cause */
182#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
183 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
184 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
185 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
186 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
187 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
188 0)
189
190/* Indicates whether the last reset was a software reset (=1) */
191#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
192
193/* Last hw error cause */
194#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
195 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
196 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
197 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
198 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
199 0)
200
201/* Translate bits to something useful */
202
203/* Last hw error cause */
204#define SEQSTAT_HWERRCAUSE_SHIFT (14)
205#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
206#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
207#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
208#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
209
210/**************************************************
211 * SYSCFG register
212 **************************************************/
213
214/* Bit Positions */
215#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
216 * set it forces an exception
217 * for each instruction executed
218 */
219#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
220#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
221
222/* Masks */
223
224/* Supervisor single step, when set it forces an exception for each
225 *instruction executed
226 */
227#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
228/* Enable cycle counter (=1) */
229#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
230/* Self Nesting Interrupt Enable */
231#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
232/* Backward-compatibility for typos in prior releases */
233#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
234#define SYSCFG_CCCEN SYSCFG_CCEN
235
236/****************************************************
237 * Core MMR Register Map
238 ****************************************************/
239
240/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
241
242#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
243#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
244#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
245 * Buffer Status
246 */
247#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
248#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
249 * Buffer Fault Address
250 */
251#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
252 * Buffer 0
253 */
254#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
255 * Buffer 1
256 */
257#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
258 * Buffer 2
259 */
260#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
261 * Lookaside Buffer 3
262 */
263#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
264 * Lookaside Buffer 4
265 */
266#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
267 * Lookaside Buffer 5
268 */
269#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
270 * Lookaside Buffer 6
271 */
272#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
273 * Lookaside Buffer 7
274 */
275#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
276 * Lookaside Buffer 8
277 */
278#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
279 * Lookaside Buffer 9
280 */
281#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
282 * Lookaside Buffer 10
283 */
284#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
285 * Lookaside Buffer 11
286 */
287#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
288 * Lookaside Buffer 12
289 */
290#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
291 * Lookaside Buffer 13
292 */
293#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
294 * Lookaside Buffer 14
295 */
296#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
297 * Lookaside Buffer 15
298 */
299#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
300#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
301#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
302#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
303#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
304#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
305#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
306#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
307#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
308#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
309#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
310#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
311#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
312#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
313#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
314#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
315#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
316
317#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
318#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
319#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
320
321/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
322
323#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
324#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
325#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
326#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
327#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
328#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
329 * Protection Lookaside Buffer 0
330 */
331#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
332 * Protection Lookaside Buffer 1
333 */
334#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
335 * Protection Lookaside Buffer 2
336 */
337#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
338 * Protection Lookaside Buffer 3
339 */
340#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
341 * Protection Lookaside Buffer 4
342 */
343#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
344 * Protection Lookaside Buffer 5
345 */
346#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
347 * Protection Lookaside Buffer 6
348 */
349#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
350 * Protection Lookaside Buffer 7
351 */
352#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
353 * Protection Lookaside Buffer 8
354 */
355#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
356 * Protection Lookaside Buffer 9
357 */
358#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
359 * Protection Lookaside Buffer 10
360 */
361#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
362 * Protection Lookaside Buffer 11
363 */
364#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
365 * Protection Lookaside Buffer 12
366 */
367#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
368 * Protection Lookaside Buffer 13
369 */
370#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
371 * Protection Lookaside Buffer 14
372 */
373#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
374 * Protection Lookaside Buffer 15
375 */
376#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
377#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
378#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
379#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
380#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
381#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
382#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
383#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
384#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
385#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
386#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
387#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
388#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
389#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
390#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
391#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
392#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
393#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
394#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
395
396/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
397
398#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
399#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
400#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
401#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
402#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
403#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
404#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
405#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
406#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
407#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
408#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
409#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
410#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
411#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
412#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
413#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
414#define IMASK 0xFFE02104 /* Interrupt Mask Register */
415#define IPEND 0xFFE02108 /* Interrupt Pending Register */
416#define ILAT 0xFFE0210C /* Interrupt Latch Register */
417#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
418
419/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
420
421#define TCNTL 0xFFE03000 /* Core Timer Control Register */
422#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
423#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
424#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
425
426/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
427#define DSPID 0xFFE05000 /* DSP Processor ID Register for
428 * MP implementations
429 */
430
431#define DBGSTAT 0xFFE05008 /* Debug Status Register */
432
433/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
434
435#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
436#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
437#define TBUF 0xFFE06100 /* Trace Buffer */
438
439/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
440
441/* Watchpoint Instruction Address Control Register */
442#define WPIACTL 0xFFE07000
443/* Watchpoint Instruction Address Register 0 */
444#define WPIA0 0xFFE07040
445/* Watchpoint Instruction Address Register 1 */
446#define WPIA1 0xFFE07044
447/* Watchpoint Instruction Address Register 2 */
448#define WPIA2 0xFFE07048
449/* Watchpoint Instruction Address Register 3 */
450#define WPIA3 0xFFE0704C
451/* Watchpoint Instruction Address Register 4 */
452#define WPIA4 0xFFE07050
453/* Watchpoint Instruction Address Register 5 */
454#define WPIA5 0xFFE07054
455/* Watchpoint Instruction Address Count Register 0 */
456#define WPIACNT0 0xFFE07080
457/* Watchpoint Instruction Address Count Register 1 */
458#define WPIACNT1 0xFFE07084
459/* Watchpoint Instruction Address Count Register 2 */
460#define WPIACNT2 0xFFE07088
461/* Watchpoint Instruction Address Count Register 3 */
462#define WPIACNT3 0xFFE0708C
463/* Watchpoint Instruction Address Count Register 4 */
464#define WPIACNT4 0xFFE07090
465/* Watchpoint Instruction Address Count Register 5 */
466#define WPIACNT5 0xFFE07094
467/* Watchpoint Data Address Control Register */
468#define WPDACTL 0xFFE07100
469/* Watchpoint Data Address Register 0 */
470#define WPDA0 0xFFE07140
471/* Watchpoint Data Address Register 1 */
472#define WPDA1 0xFFE07144
473/* Watchpoint Data Address Count Value Register 0 */
474#define WPDACNT0 0xFFE07180
475/* Watchpoint Data Address Count Value Register 1 */
476#define WPDACNT1 0xFFE07184
477/* Watchpoint Status Register */
478#define WPSTAT 0xFFE07200
479
480/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
481
482/* Performance Monitor Control Register */
483#define PFCTL 0xFFE08000
484/* Performance Monitor Counter Register 0 */
485#define PFCNTR0 0xFFE08100
486/* Performance Monitor Counter Register 1 */
487#define PFCNTR1 0xFFE08104
488
489/****************************************************
490 * Core MMR Register Bits
491 ****************************************************/
492
493/**************************************************
494 * EVT registers (ILAT, IMASK, and IPEND).
495 **************************************************/
496
497/* Bit Positions */
498#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
499#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
500#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
501#define EVT_EVX_P 0x00000003 /* Exception bit position */
502#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
503#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
504#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
505#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
506#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
507#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
508#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
509#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
510#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
511#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
512#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
513#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
514
515/* Masks */
516#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
517#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
518#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
519#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
520#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
521#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
522#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
523#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
524#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
525#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
526#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
527#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
528#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
529#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
530#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
531#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
532
533/**************************************************
534 * DMEM_CONTROL Register
535 **************************************************/
536/* Bit Positions */
537#define ENDM_P 0x00 /* (doesn't really exist) Enable
538 *Data Memory L1
539 */
540#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
541
542#define ENDCPLB_P 0x01 /* Enable DCPLBS */
543#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
544#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
545#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
546#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
547#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
548#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
549#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
550#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
551
552/* Masks */
553#define ENDM 0x00000001 /* (doesn't really exist) Enable
554 * Data Memory L1
555 */
556#define ENDCPLB 0x00000002 /* Enable DCPLB */
557#define ASRAM_BSRAM 0x00000000
558#define ACACHE_BSRAM 0x00000008
559#define ACACHE_BCACHE 0x0000000C
560#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
561#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
562#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
563
564/* IMEM_CONTROL Register */
565/* Bit Positions */
566#define ENIM_P 0x00 /* Enable L1 Code Memory */
567#define IMCTL_ENIM_P 0x00 /* "" (older define) */
568#define ENICPLB_P 0x01 /* Enable ICPLB */
569#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
570#define IMC_P 0x02 /* Enable */
571#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
572 * cache (0=SRAM)
573 */
574#define ILOC0_P 0x03 /* Lock Way 0 */
575#define ILOC1_P 0x04 /* Lock Way 1 */
576#define ILOC2_P 0x05 /* Lock Way 2 */
577#define ILOC3_P 0x06 /* Lock Way 3 */
578#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
579 * Priority
580 */
581/* Masks */
582#define ENIM 0x00000001 /* Enable L1 Code Memory */
583#define ENICPLB 0x00000002 /* Enable ICPLB */
584#define IMC 0x00000004 /* Configure L1 code memory as
585 * cache (0=SRAM)
586 */
587#define ILOC0 0x00000008 /* Lock Way 0 */
588#define ILOC1 0x00000010 /* Lock Way 1 */
589#define ILOC2 0x00000020 /* Lock Way 2 */
590#define ILOC3 0x00000040 /* Lock Way 3 */
591#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
592 * Priority
593 */
594
595/* TCNTL Masks */
596#define TMPWR 0x00000001 /* Timer Low Power Control,
597 * 0=low power mode, 1=active state
598 */
599#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
600#define TAUTORLD 0x00000004 /* Timer auto reload */
601#define TINT 0x00000008 /* Timer generated interrupt 0=no
602 * interrupt has been generated,
603 * 1=interrupt has been generated
604 * (sticky)
605 */
606
607/* DCPLB_DATA and ICPLB_DATA Registers */
608/* Bit Positions */
609#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
610#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
611 * locked
612 */
613#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
614 * allowed (user mode)
615 */
616/* Masks */
617#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
618#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
619 * locked
620 */
621#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
622 * allowed (user mode)
623 */
624#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
625#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
626#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
627#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
628#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
629 * mapped to L1
630 */
631#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
632 * priority port
633 */
634#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
635 * in L1
636 */
637/* ICPLB_DATA only */
638#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
639 * 1=priority for non-replacement
640 */
641/* DCPLB_DATA only */
642#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
643 * access allowed (user mode)
644 */
645#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
646 * access allowed (supervisor mode)
647 */
648#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
649#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
650 * write-through writes,
651 * 1= allocate cache lines on
652 * write-through writes.
653 */
654#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
655
656/* TBUFCTL Masks */
657#define TBUFPWR 0x0001
658#define TBUFEN 0x0002
659#define TBUFOVF 0x0004
660#define TBUFCMPLP_SINGLE 0x0008
661#define TBUFCMPLP_DOUBLE 0x0010
662#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
663
664/* TBUFSTAT Masks */
665#define TBUFCNT 0x001F
666
667/* ITEST_COMMAND and DTEST_COMMAND Registers */
668/* Masks */
669#define TEST_READ 0x00000000 /* Read Access */
670#define TEST_WRITE 0x00000002 /* Write Access */
671#define TEST_TAG 0x00000000 /* Access TAG */
672#define TEST_DATA 0x00000004 /* Access DATA */
673#define TEST_DW0 0x00000000 /* Select Double Word 0 */
674#define TEST_DW1 0x00000008 /* Select Double Word 1 */
675#define TEST_DW2 0x00000010 /* Select Double Word 2 */
676#define TEST_DW3 0x00000018 /* Select Double Word 3 */
677#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
678#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
679#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
680#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
681#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
682#define TEST_WAY0 0x00000000 /* Access Way0 */
683#define TEST_WAY1 0x04000000 /* Access Way1 */
684/* ITEST_COMMAND only */
685#define TEST_WAY2 0x08000000 /* Access Way2 */
686#define TEST_WAY3 0x0C000000 /* Access Way3 */
687/* DTEST_COMMAND only */
688#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
689#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
690
691#endif /* _DEF_LPBLACKFIN_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 11:26:21 -0500