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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-11 22:11:51 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-11 22:11:51 -0400
commit1ef3e36251e4edc77a48967d015a87ca3c4283ea (patch)
tree2ee6c869d752c13a56ee2259d115210135f5d5de /include/asm-blackfin/mach-common/def_LPBlackfin.h
parentc634920abaf9c0a93266a57beff6fce9d3852cb2 (diff)
parentbbf275f092b1b2a9bc8a504500ec387f9ddff859 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (74 commits) Blackfin serial driver: pending a unique anomaly id, tie the break flood issue to ANOMALY_05000230 blackfin enable arbitary speed serial setting Blackfin arch: Remove cruft - CONFIG_DEBUG_SERIAL_EARLY_INIT and DEBUG_KERNEL_START Blackfin arch: fix typo in register name Blackfin arch: trim the Blackfin arch MAINTAINERS list Blackfin arch: fix bug libstdc++ calling writev with an iovec containing { NULL, 0 } fails on Blackfin Blackfin arch: Export strcpy - occasionally get module link failures otherwise Blackfin arch: the load address is not safe to point to as a workaround for ANOMALY 05000281 Blackfin arch: show_mem can not be marked as init, since it is called during OOM condition Blackfin arch: flush/inv the correct range when using write back cache and fix bugs find by dmacopy Blackfin arch: update kgdb patch Blackfin arch: Comply with revised Anomaly Workarounds for BF533 05000311 and BF561 05000323 Blackfin arch: Print out debug info, as early as possible Blackfin arch: Enable earlyprintk earlier - so any error after our interrupt tables are set up will print out Blackfin arch: fix endless loop bug when a double fault happens Blackfin arch: Initial patch to add earlyprintk support Blackfin arch: add TWIx_REGBASE and SPIx_REGBASE to specific CPU header files, use the new REGBASE for board platform resources Blackfin arch: modify the insX/outsX and dma_insX/dma_outsX to be compatible with other archs Blackfin arch: add more common defines for output sections Blackfin arch: cleanup IO and DMA_IO API function definitions according to other arches ...
Diffstat (limited to 'include/asm-blackfin/mach-common/def_LPBlackfin.h')
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h135
1 files changed, 67 insertions, 68 deletions
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index be1ece8c0c27..c1d8c4a78fcf 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -33,81 +33,77 @@
33 33
34#include <asm/mach/anomaly.h> 34#include <asm/mach/anomaly.h>
35 35
36/*#if !defined(__ADSPLPBLACKFIN__)
37#warning def_LPBlackfin.h should only be included for 532 compatible chips.
38#endif
39*/
40
41#define MK_BMSK_(x) (1<<x) 36#define MK_BMSK_(x) (1<<x)
42 37
43#if defined(ANOMALY_05000198) 38#ifndef __ASSEMBLY__
44
45#define bfin_read8(addr) ({ unsigned char __v; \
46 __asm__ __volatile__ ("NOP;\n\t" \
47 "%0 = b[%1] (z);\n\t" \
48 : "=d"(__v) : "a"(addr)); \
49 __v; })
50
51#define bfin_read16(addr) ({ unsigned __v; \
52 __asm__ __volatile__ ("NOP;\n\t"\
53 "%0 = w[%1] (z);\n\t"\
54 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
55
56#define bfin_read32(addr) ({ unsigned __v; \
57 __asm__ __volatile__ ("NOP;\n\t"\
58 "%0 = [%1];\n\t"\
59 : "=d"(__v) : "a"(addr)); __v; })
60
61#define bfin_write8(addr, val) ({ \
62 __asm__ __volatile__ ("NOP;\n\t" \
63 "b[%0] = %1;\n\t" \
64 : : "a"(addr), "d"(val) : "memory");})
65 39
66#define bfin_write16(addr,val) ({\ 40#include <linux/types.h>
67 __asm__ __volatile__ ("NOP;\n\t"\
68 "w[%0] = %1;\n\t"\
69 : : "a"(addr) , "d"(val) : "memory");})
70
71#define bfin_write32(addr,val) ({\
72 __asm__ __volatile__ ("NOP;\n\t"\
73 "[%0] = %1;\n\t"\
74 : : "a"(addr) , "d"(val) : "memory");})
75 41
42#if ANOMALY_05000198
43# define NOP_PAD_ANOMALY_05000198 "nop;"
76#else 44#else
77 45# define NOP_PAD_ANOMALY_05000198
78#define bfin_read8(addr) ({ unsigned char __v; \
79 __asm__ __volatile__ ( \
80 "%0 = b[%1] (z);\n\t" \
81 :"=d"(__v) : "a"(addr)); \
82 __v; })
83
84#define bfin_read16(addr) ({ unsigned __v; \
85 __asm__ __volatile__ (\
86 "%0 = w[%1] (z);\n\t"\
87 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
88
89#define bfin_read32(addr) ({ unsigned __v; \
90 __asm__ __volatile__ (\
91 "%0 = [%1];\n\t"\
92 : "=d"(__v) : "a"(addr)); __v; })
93
94#define bfin_write8(addr, val) ({ \
95 __asm__ __volatile__ ( \
96 "b[%0] = %1; \n\t" \
97 ::"a"(addr), "d"(val) : "memory");})
98
99#define bfin_write16(addr,val) ({\
100 __asm__ __volatile__ (\
101 "w[%0] = %1;\n\t"\
102 : : "a"(addr) , "d"(val) : "memory");})
103
104#define bfin_write32(addr,val) ({\
105 __asm__ __volatile__ (\
106 "[%0] = %1;\n\t"\
107 : : "a"(addr) , "d"(val) : "memory");})
108
109#endif 46#endif
110 47
48#define bfin_read8(addr) ({ \
49 uint8_t __v; \
50 __asm__ __volatile__( \
51 NOP_PAD_ANOMALY_05000198 \
52 "%0 = b[%1] (z);" \
53 : "=d" (__v) \
54 : "a" (addr) \
55 ); \
56 __v; })
57
58#define bfin_read16(addr) ({ \
59 uint16_t __v; \
60 __asm__ __volatile__( \
61 NOP_PAD_ANOMALY_05000198 \
62 "%0 = w[%1] (z);" \
63 : "=d" (__v) \
64 : "a" (addr) \
65 ); \
66 __v; })
67
68#define bfin_read32(addr) ({ \
69 uint32_t __v; \
70 __asm__ __volatile__( \
71 NOP_PAD_ANOMALY_05000198 \
72 "%0 = [%1];" \
73 : "=d" (__v) \
74 : "a" (addr) \
75 ); \
76 __v; })
77
78#define bfin_write8(addr, val) \
79 __asm__ __volatile__( \
80 NOP_PAD_ANOMALY_05000198 \
81 "b[%0] = %1;" \
82 : \
83 : "a" (addr), "d" (val) \
84 : "memory" \
85 )
86
87#define bfin_write16(addr, val) \
88 __asm__ __volatile__( \
89 NOP_PAD_ANOMALY_05000198 \
90 "w[%0] = %1;" \
91 : \
92 : "a" (addr), "d" (val) \
93 : "memory" \
94 )
95
96#define bfin_write32(addr, val) \
97 __asm__ __volatile__( \
98 NOP_PAD_ANOMALY_05000198 \
99 "[%0] = %1;" \
100 : \
101 : "a" (addr), "d" (val) \
102 : "memory" \
103 )
104
105#endif /* __ASSEMBLY__ */
106
111/************************************************** 107/**************************************************
112 * System Register Bits 108 * System Register Bits
113 **************************************************/ 109 **************************************************/
@@ -643,6 +639,7 @@
643#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access 639#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
644 * allowed (user mode) 640 * allowed (user mode)
645 */ 641 */
642
646#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ 643#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
647#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ 644#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
648#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ 645#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
@@ -675,6 +672,8 @@
675 */ 672 */
676#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ 673#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
677 674
675#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
676
678/* TBUFCTL Masks */ 677/* TBUFCTL Masks */
679#define TBUFPWR 0x0001 678#define TBUFPWR 0x0001
680#define TBUFEN 0x0002 679#define TBUFEN 0x0002