diff options
| author | Michael Hennerich <michael.hennerich@analog.com> | 2007-07-12 00:32:52 -0400 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-07-12 00:32:52 -0400 |
| commit | 5610db61cf2945a5e74667e952f2792c96ba53a1 (patch) | |
| tree | 982c8cdb8267ac0a162b4de5d3d3b545adcff602 /include/asm-blackfin/mach-bf561 | |
| parent | 520473b0775ce046d179afa686fb3222884c389d (diff) | |
Blackfin arch: Add Support for Peripheral PortMux and resouce allocation
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf561')
| -rw-r--r-- | include/asm-blackfin/mach-bf561/portmux.h | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h new file mode 100644 index 000000000000..10d11d5ffe23 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/portmux.h | |||
| @@ -0,0 +1,87 @@ | |||
| 1 | #ifndef _MACH_PORTMUX_H_ | ||
| 2 | #define _MACH_PORTMUX_H_ | ||
| 3 | |||
| 4 | #define P_PPI0_CLK (P_DONTCARE) | ||
| 5 | #define P_PPI0_FS1 (P_DONTCARE) | ||
| 6 | #define P_PPI0_FS2 (P_DONTCARE) | ||
| 7 | #define P_PPI0_FS3 (P_DONTCARE) | ||
| 8 | #define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47)) | ||
| 9 | #define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46)) | ||
| 10 | #define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45)) | ||
| 11 | #define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44)) | ||
| 12 | #define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43)) | ||
| 13 | #define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42)) | ||
| 14 | #define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41)) | ||
| 15 | #define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40)) | ||
| 16 | #define P_PPI0_D0 (P_DONTCARE) | ||
| 17 | #define P_PPI0_D1 (P_DONTCARE) | ||
| 18 | #define P_PPI0_D2 (P_DONTCARE) | ||
| 19 | #define P_PPI0_D3 (P_DONTCARE) | ||
| 20 | #define P_PPI0_D4 (P_DONTCARE) | ||
| 21 | #define P_PPI0_D5 (P_DONTCARE) | ||
| 22 | #define P_PPI0_D6 (P_DONTCARE) | ||
| 23 | #define P_PPI0_D7 (P_DONTCARE) | ||
| 24 | #define P_PPI1_CLK (P_DONTCARE) | ||
| 25 | #define P_PPI1_FS1 (P_DONTCARE) | ||
| 26 | #define P_PPI1_FS2 (P_DONTCARE) | ||
| 27 | #define P_PPI1_FS3 (P_DONTCARE) | ||
| 28 | #define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39)) | ||
| 29 | #define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38)) | ||
| 30 | #define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37)) | ||
| 31 | #define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36)) | ||
| 32 | #define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35)) | ||
| 33 | #define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34)) | ||
| 34 | #define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33)) | ||
| 35 | #define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32)) | ||
| 36 | #define P_PPI1_D0 (P_DONTCARE) | ||
| 37 | #define P_PPI1_D1 (P_DONTCARE) | ||
| 38 | #define P_PPI1_D2 (P_DONTCARE) | ||
| 39 | #define P_PPI1_D3 (P_DONTCARE) | ||
| 40 | #define P_PPI1_D4 (P_DONTCARE) | ||
| 41 | #define P_PPI1_D5 (P_DONTCARE) | ||
| 42 | #define P_PPI1_D6 (P_DONTCARE) | ||
| 43 | #define P_PPI1_D7 (P_DONTCARE) | ||
| 44 | #define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31)) | ||
| 45 | #define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30)) | ||
| 46 | #define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29)) | ||
| 47 | #define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28)) | ||
| 48 | #define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27)) | ||
| 49 | #define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26)) | ||
| 50 | #define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25)) | ||
| 51 | #define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24)) | ||
| 52 | #define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23)) | ||
| 53 | #define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22)) | ||
| 54 | #define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21)) | ||
| 55 | #define P_SPORT1_DRPRI (P_DONTCARE) | ||
| 56 | #define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20)) | ||
| 57 | #define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19)) | ||
| 58 | #define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18)) | ||
| 59 | #define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17)) | ||
| 60 | #define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16)) | ||
| 61 | #define P_SPORT0_DRPRI (P_DONTCARE) | ||
| 62 | #define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15)) | ||
| 63 | #define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) | ||
| 64 | #define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) | ||
| 65 | #define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) | ||
| 66 | #define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) | ||
| 67 | #define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) | ||
| 68 | #define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) | ||
| 69 | #define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) | ||
| 70 | #define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) | ||
| 71 | #define P_TMR11 (P_DONTCARE) | ||
| 72 | #define P_TMR10 (P_DONTCARE) | ||
| 73 | #define P_TMR9 (P_DONTCARE) | ||
| 74 | #define P_TMR8 (P_DONTCARE) | ||
| 75 | #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7)) | ||
| 76 | #define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6)) | ||
| 77 | #define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5)) | ||
| 78 | #define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4)) | ||
| 79 | #define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3)) | ||
| 80 | #define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2)) | ||
| 81 | #define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) | ||
| 82 | #define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) | ||
| 83 | #define P_SPI0_MOSI (P_DONTCARE) | ||
| 84 | #define P_SPI0_MIS0 (P_DONTCARE) | ||
| 85 | #define P_SPI0_SCK (P_DONTCARE) | ||
| 86 | |||
| 87 | #endif /* _MACH_PORTMUX_H_ */ | ||