diff options
author | Michael Hennerich <michael.hennerich@analog.com> | 2008-05-06 23:41:26 -0400 |
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committer | Bryan Wu <cooloney@kernel.org> | 2008-05-06 23:41:26 -0400 |
commit | c2f9527979c14a21bbaa31c12a14204aabeb6e45 (patch) | |
tree | d60ec334a6ccc5804c87f22d721eb5b986f99ccb /include/asm-blackfin/mach-bf561 | |
parent | 67dea022d84f7c2b1e4d8c74a16fb07bf1a7d8f0 (diff) |
[Blackfin] arch: Equalize include files: Add VR_CTL masks
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf561')
-rw-r--r-- | include/asm-blackfin/mach-bf561/defBF561.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index 366c9b9a0cb7..1ab50e906fe7 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h | |||
@@ -868,6 +868,34 @@ | |||
868 | #define CHIPID_FAMILY 0x0FFFF000 | 868 | #define CHIPID_FAMILY 0x0FFFF000 |
869 | #define CHIPID_MANUFACTURE 0x00000FFE | 869 | #define CHIPID_MANUFACTURE 0x00000FFE |
870 | 870 | ||
871 | /* VR_CTL Masks */ | ||
872 | #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ | ||
873 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | ||
874 | #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ | ||
875 | #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ | ||
876 | #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ | ||
877 | |||
878 | #define GAIN 0x000C /* Voltage Level Gain */ | ||
879 | #define GAIN_5 0x0000 /* GAIN = 5*/ | ||
880 | #define GAIN_10 0x0004 /* GAIN = 1*/ | ||
881 | #define GAIN_20 0x0008 /* GAIN = 2*/ | ||
882 | #define GAIN_50 0x000C /* GAIN = 5*/ | ||
883 | |||
884 | #define VLEV 0x00F0 /* Internal Voltage Level */ | ||
885 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ | ||
886 | #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ | ||
887 | #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ | ||
888 | #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ | ||
889 | #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ | ||
890 | #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ | ||
891 | #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ | ||
892 | #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ | ||
893 | #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ | ||
894 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ | ||
895 | |||
896 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | ||
897 | #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ | ||
898 | |||
871 | /* PLL_DIV Masks */ | 899 | /* PLL_DIV Masks */ |
872 | #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ | 900 | #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ |
873 | 901 | ||