diff options
| author | Mike Frysinger <michael.frysinger@analog.com> | 2007-11-12 11:31:33 -0500 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-11-12 11:31:33 -0500 |
| commit | fa43cd8b100e9c6182f872d0fc4bb3964e100808 (patch) | |
| tree | 44e8d735cc0f86421839116506b6b4a4aa5554ca /include/asm-blackfin/mach-bf561/defBF561.h | |
| parent | 53f8a252df515639de6cc0f43f8c5d5c234adc6b (diff) | |
Blackfin arch: add a compatible DOUBLE_FAULT define to enable resets on double faults in either core
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf561/defBF561.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf561/defBF561.h | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index 7945e8a3a841..66f199608445 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h | |||
| @@ -55,6 +55,7 @@ | |||
| 55 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ | 55 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ |
| 56 | #define SWRST SICA_SWRST | 56 | #define SWRST SICA_SWRST |
| 57 | #define SYSCR SICA_SYSCR | 57 | #define SYSCR SICA_SYSCR |
| 58 | #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) | ||
| 58 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) | 59 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) |
| 59 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) | 60 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) |
| 60 | #define RESET_SOFTWARE (SWRST_OCCURRED) | 61 | #define RESET_SOFTWARE (SWRST_OCCURRED) |
| @@ -877,12 +878,14 @@ | |||
| 877 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | 878 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ |
| 878 | 879 | ||
| 879 | /* SWRST Mask */ | 880 | /* SWRST Mask */ |
| 880 | #define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ | 881 | #define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ |
| 881 | #define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */ | 882 | #define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ |
| 882 | #define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */ | 883 | #define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */ |
| 883 | #define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */ | 884 | #define SWRST_DBL_FAULT_B 0x0800 /* SWRST Core B Double Fault */ |
| 884 | #define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */ | 885 | #define SWRST_DBL_FAULT_A 0x1000 /* SWRST Core A Double Fault */ |
| 885 | #define SWRST_OCCURRED 0x00008000 /* SWRST Status */ | 886 | #define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */ |
| 887 | #define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */ | ||
| 888 | #define SWRST_OCCURRED 0x8000 /* SWRST Status */ | ||
| 886 | 889 | ||
| 887 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ | 890 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ |
| 888 | 891 | ||