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authorMichael Hennerich <michael.hennerich@analog.com>2007-07-11 23:58:44 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-11 23:58:44 -0400
commit9be343c5bcd1cf285c2150f363bc9dd7aab8b7fb (patch)
tree7c58ca04e9030de9d5fd54be6ddd05cf2a2221ad /include/asm-blackfin/mach-bf548
parent9401e618c8f70920f34893946239e24d40a3519a (diff)
Blackfin arch: There is no CDPRIO Bit in the EBIU_AMGCTL Register of BF54x arch
However there are similar things in the EBIU_DDRQUE Register Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf548')
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h17
1 files changed, 1 insertions, 16 deletions
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 163c79e3d230..9498313a2cb7 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -32,16 +32,6 @@
32 32
33#define SUPPORTED_REVID 0 33#define SUPPORTED_REVID 0
34 34
35/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
36
37#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
38#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
39#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
41#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
42#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | \
43 RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
44
45#define OFFSET_(x) ((x) & 0x0000FFFF) 35#define OFFSET_(x) ((x) & 0x0000FFFF)
46 36
47/*some misc defines*/ 37/*some misc defines*/
@@ -113,13 +103,8 @@
113#else 103#else
114#define V_AMCKEN 0x0 104#define V_AMCKEN 0x0
115#endif 105#endif
116#ifdef CONFIG_C_CDPRIO
117#define V_CDPRIO 0x100
118#else
119#define V_CDPRIO 0x0
120#endif
121 106
122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) 107#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
123 108
124#define MAX_VC 650000000 109#define MAX_VC 650000000
125#define MIN_VC 50000000 110#define MIN_VC 50000000