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authorGraf Yang <graf.yang@analog.com>2008-04-23 16:43:14 -0400
committerBryan Wu <cooloney@kernel.org>2008-04-23 16:43:14 -0400
commit6ed839423073251b513664fdadb180634aed704b (patch)
tree073350299070ba091f4fb4fb146b9a931edc44b8 /include/asm-blackfin/mach-bf548
parentdb68254f0639a357309f02cf8707490265fa7a31 (diff)
[Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg.
Signed-off-by: Graf Yang <graf.yang@analog.com> Cc: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf548')
-rw-r--r--include/asm-blackfin/mach-bf548/blackfin.h23
1 files changed, 12 insertions, 11 deletions
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
index 3bd67da86053..b8509c16ecd4 100644
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -153,17 +153,18 @@
153#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) 153#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
154#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() 154#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
155#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) 155#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
156#define UART_THR UART1_THR 156
157#define UART_RBR UART1_RBR 157#define BFIN_UART_THR UART1_THR
158#define UART_DLL UART1_DLL 158#define BFIN_UART_RBR UART1_RBR
159#define UART_IER UART1_IER 159#define BFIN_UART_DLL UART1_DLL
160#define UART_DLH UART1_DLH 160#define BFIN_UART_IER UART1_IER
161#define UART_IIR UART1_IIR 161#define BFIN_UART_DLH UART1_DLH
162#define UART_LCR UART1_LCR 162#define BFIN_UART_IIR UART1_IIR
163#define UART_MCR UART1_MCR 163#define BFIN_UART_LCR UART1_LCR
164#define UART_LSR UART1_LSR 164#define BFIN_UART_MCR UART1_MCR
165#define UART_SCR UART1_SCR 165#define BFIN_UART_LSR UART1_LSR
166#define UART_GCTL UART1_GCTL 166#define BFIN_UART_SCR UART1_SCR
167#define BFIN_UART_GCTL UART1_GCTL
167 168
168/* PLL_DIV Masks */ 169/* PLL_DIV Masks */
169#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ 170#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */