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authorBryan Wu <cooloney@kernel.org>2008-08-26 22:51:02 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-26 22:51:02 -0400
commit639f6571458948b5112be2cf00c0c2c04db2897d (patch)
treea4dd7af33d0e92c935ba1e904f6fb7e923ac825e /include/asm-blackfin/mach-bf548
parent3d9b7a5ce534f3963afcf8f4777267e5899fe007 (diff)
Blackfin arch: move include/asm-blackfin header files to arch/blackfin
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf548')
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h100
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h127
-rw-r--r--include/asm-blackfin/mach-bf548/bf54x-lq043.h30
-rw-r--r--include/asm-blackfin/mach-bf548/bf54x_keys.h17
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h220
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_sir.h166
-rw-r--r--include/asm-blackfin/mach-bf548/blackfin.h190
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF542.h590
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF544.h945
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF547.h832
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF548.h1577
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF549.h1863
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h2750
-rw-r--r--include/asm-blackfin/mach-bf548/defBF542.h925
-rw-r--r--include/asm-blackfin/mach-bf548/defBF544.h707
-rw-r--r--include/asm-blackfin/mach-bf548/defBF547.h1244
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h1627
-rw-r--r--include/asm-blackfin/mach-bf548/defBF549.h2737
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h3956
-rw-r--r--include/asm-blackfin/mach-bf548/dma.h76
-rw-r--r--include/asm-blackfin/mach-bf548/gpio.h219
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h501
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h255
-rw-r--r--include/asm-blackfin/mach-bf548/mem_map.h111
-rw-r--r--include/asm-blackfin/mach-bf548/portmux.h286
25 files changed, 0 insertions, 22051 deletions
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
deleted file mode 100644
index 3ad59655881a..000000000000
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2007 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
17#define ANOMALY_05000074 (1)
18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
19#define ANOMALY_05000119 (1)
20/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
21#define ANOMALY_05000122 (1)
22/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
23#define ANOMALY_05000245 (1)
24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
25#define ANOMALY_05000265 (1)
26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
27#define ANOMALY_05000272 (1)
28/* False Hardware Error Exception when ISR context is not restored */
29#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
31#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
33#define ANOMALY_05000310 (1)
34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
35#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
36/* TWI Slave Boot Mode Is Not Functional */
37#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
38/* External FIFO Boot Mode Is Not Functional */
39#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
41#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
42/* Incorrect Access of OTP_STATUS During otp_write() Function */
43#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
44/* Synchronous Burst Flash Boot Mode Is Not Functional */
45#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
46/* Host DMA Boot Mode Is Not Functional */
47#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
49#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
50/* Inadequate Rotary Debounce Logic Duration */
51#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
53#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
55#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
57#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
59#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
61#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
62/* USB Calibration Value Is Not Intialized */
63#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
65#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
66/* Data Lost when Core Reads SDH Data FIFO */
67#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
68/* PLL Status Register Is Inaccurate */
69#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
70/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
71#define ANOMALY_05000357 (1)
72/* External Memory Read Access Hangs Core With PLL Bypass */
73#define ANOMALY_05000360 (1)
74/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
75#define ANOMALY_05000365 (1)
76/* Addressing Conflict between Boot ROM and Asynchronous Memory */
77#define ANOMALY_05000369 (1)
78/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
79#define ANOMALY_05000371 (1)
80/* Mobile DDR Operation Not Functional */
81#define ANOMALY_05000377 (1)
82/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
83#define ANOMALY_05000378 (1)
84
85/* Anomalies that don't exist on this proc */
86#define ANOMALY_05000125 (0)
87#define ANOMALY_05000158 (0)
88#define ANOMALY_05000183 (0)
89#define ANOMALY_05000198 (0)
90#define ANOMALY_05000230 (0)
91#define ANOMALY_05000244 (0)
92#define ANOMALY_05000261 (0)
93#define ANOMALY_05000263 (0)
94#define ANOMALY_05000266 (0)
95#define ANOMALY_05000273 (0)
96#define ANOMALY_05000311 (0)
97#define ANOMALY_05000323 (0)
98#define ANOMALY_05000363 (0)
99
100#endif
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
deleted file mode 100644
index e748588e8930..000000000000
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/bf548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: System MMR register and memory map for ADSP-BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF548_H__
31#define __MACH_BF548_H__
32
33#define SUPPORTED_REVID 0
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54
55#define BFIN_DSUBBANKS 4
56#define BFIN_DWAYS 2
57#define BFIN_DLINES 64
58#define BFIN_ISUBBANKS 4
59#define BFIN_IWAYS 4
60#define BFIN_ILINES 32
61
62#define WAY0_L 0x1
63#define WAY1_L 0x2
64#define WAY01_L 0x3
65#define WAY2_L 0x4
66#define WAY02_L 0x5
67#define WAY12_L 0x6
68#define WAY012_L 0x7
69
70#define WAY3_L 0x8
71#define WAY03_L 0x9
72#define WAY13_L 0xA
73#define WAY013_L 0xB
74
75#define WAY32_L 0xC
76#define WAY320_L 0xD
77#define WAY321_L 0xE
78#define WAYALL_L 0xF
79
80#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
81
82/********************************* EBIU Settings ************************************/
83#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
84#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
85
86#ifdef CONFIG_C_AMBEN_ALL
87#define V_AMBEN AMBEN_ALL
88#endif
89#ifdef CONFIG_C_AMBEN
90#define V_AMBEN 0x0
91#endif
92#ifdef CONFIG_C_AMBEN_B0
93#define V_AMBEN AMBEN_B0
94#endif
95#ifdef CONFIG_C_AMBEN_B0_B1
96#define V_AMBEN AMBEN_B0_B1
97#endif
98#ifdef CONFIG_C_AMBEN_B0_B1_B2
99#define V_AMBEN AMBEN_B0_B1_B2
100#endif
101#ifdef CONFIG_C_AMCKEN
102#define V_AMCKEN AMCKEN
103#else
104#define V_AMCKEN 0x0
105#endif
106
107#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
108
109#if defined(CONFIG_BF542)
110# define CPU "BF542"
111# define CPUID 0x027c8000
112#elif defined(CONFIG_BF544)
113# define CPU "BF544"
114# define CPUID 0x027c8000
115#elif defined(CONFIG_BF547)
116# define CPU "BF547"
117#elif defined(CONFIG_BF548)
118# define CPU "BF548"
119# define CPUID 0x027c6000
120#elif defined(CONFIG_BF549)
121# define CPU "BF549"
122#else
123# define CPU "UNKNOWN"
124# define CPUID 0x0
125#endif
126
127#endif /* __MACH_BF48_H__ */
diff --git a/include/asm-blackfin/mach-bf548/bf54x-lq043.h b/include/asm-blackfin/mach-bf548/bf54x-lq043.h
deleted file mode 100644
index 9c7ca62a45eb..000000000000
--- a/include/asm-blackfin/mach-bf548/bf54x-lq043.h
+++ /dev/null
@@ -1,30 +0,0 @@
1#ifndef BF54X_LQ043_H
2#define BF54X_LQ043_H
3
4struct bfin_bf54xfb_val {
5 unsigned int defval;
6 unsigned int min;
7 unsigned int max;
8};
9
10struct bfin_bf54xfb_mach_info {
11 unsigned char fixed_syncs; /* do not update sync/border */
12
13 /* LCD types */
14 int type;
15
16 /* Screen size */
17 int width;
18 int height;
19
20 /* Screen info */
21 struct bfin_bf54xfb_val xres;
22 struct bfin_bf54xfb_val yres;
23 struct bfin_bf54xfb_val bpp;
24
25 /* GPIOs */
26 unsigned short disp;
27
28};
29
30#endif /* BF54X_LQ043_H */
diff --git a/include/asm-blackfin/mach-bf548/bf54x_keys.h b/include/asm-blackfin/mach-bf548/bf54x_keys.h
deleted file mode 100644
index 1fb4ec77cc25..000000000000
--- a/include/asm-blackfin/mach-bf548/bf54x_keys.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef _BFIN_KPAD_H
2#define _BFIN_KPAD_H
3
4struct bfin_kpad_platform_data {
5 int rows;
6 int cols;
7 const unsigned int *keymap;
8 unsigned short keymapsize;
9 unsigned short repeat;
10 u32 debounce_time; /* in ns */
11 u32 coldrive_time; /* in ns */
12 u32 keyup_test_interval; /* in ms */
13};
14
15#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val))
16
17#endif
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
deleted file mode 100644
index 5e29446a8e03..000000000000
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
39#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
40#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
41#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
44#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
45
46#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
47#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
48#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
49#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
50#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
51#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
52#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
53#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
54#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
55#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
56
57#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
58#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
59
60#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
61#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
62#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
63#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
64#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
65
66#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
67# define CONFIG_SERIAL_BFIN_CTSRTS
68
69# ifndef CONFIG_UART0_CTS_PIN
70# define CONFIG_UART0_CTS_PIN -1
71# endif
72
73# ifndef CONFIG_UART0_RTS_PIN
74# define CONFIG_UART0_RTS_PIN -1
75# endif
76
77# ifndef CONFIG_UART1_CTS_PIN
78# define CONFIG_UART1_CTS_PIN -1
79# endif
80
81# ifndef CONFIG_UART1_RTS_PIN
82# define CONFIG_UART1_RTS_PIN -1
83# endif
84#endif
85/*
86 * The pin configuration is different from schematic
87 */
88struct bfin_serial_port {
89 struct uart_port port;
90 unsigned int old_status;
91#ifdef CONFIG_SERIAL_BFIN_DMA
92 int tx_done;
93 int tx_count;
94 struct circ_buf rx_dma_buf;
95 struct timer_list rx_dma_timer;
96 int rx_dma_nrows;
97 unsigned int tx_dma_channel;
98 unsigned int rx_dma_channel;
99 struct work_struct tx_dma_workqueue;
100#endif
101#ifdef CONFIG_SERIAL_BFIN_CTSRTS
102 struct timer_list cts_timer;
103 int cts_pin;
104 int rts_pin;
105#endif
106};
107
108struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
109struct bfin_serial_res {
110 unsigned long uart_base_addr;
111 int uart_irq;
112#ifdef CONFIG_SERIAL_BFIN_DMA
113 unsigned int uart_tx_dma_channel;
114 unsigned int uart_rx_dma_channel;
115#endif
116#ifdef CONFIG_SERIAL_BFIN_CTSRTS
117 int uart_cts_pin;
118 int uart_rts_pin;
119#endif
120};
121
122struct bfin_serial_res bfin_serial_resource[] = {
123#ifdef CONFIG_SERIAL_BFIN_UART0
124 {
125 0xFFC00400,
126 IRQ_UART0_RX,
127#ifdef CONFIG_SERIAL_BFIN_DMA
128 CH_UART0_TX,
129 CH_UART0_RX,
130#endif
131#ifdef CONFIG_BFIN_UART0_CTSRTS
132 CONFIG_UART0_CTS_PIN,
133 CONFIG_UART0_RTS_PIN,
134#endif
135 },
136#endif
137#ifdef CONFIG_SERIAL_BFIN_UART1
138 {
139 0xFFC02000,
140 IRQ_UART1_RX,
141#ifdef CONFIG_SERIAL_BFIN_DMA
142 CH_UART1_TX,
143 CH_UART1_RX,
144#endif
145 },
146#endif
147#ifdef CONFIG_SERIAL_BFIN_UART2
148 {
149 0xFFC02100,
150 IRQ_UART2_RX,
151#ifdef CONFIG_SERIAL_BFIN_DMA
152 CH_UART2_TX,
153 CH_UART2_RX,
154#endif
155#ifdef CONFIG_BFIN_UART2_CTSRTS
156 CONFIG_UART2_CTS_PIN,
157 CONFIG_UART2_RTS_PIN,
158#endif
159 },
160#endif
161#ifdef CONFIG_SERIAL_BFIN_UART3
162 {
163 0xFFC03100,
164 IRQ_UART3_RX,
165#ifdef CONFIG_SERIAL_BFIN_DMA
166 CH_UART3_TX,
167 CH_UART3_RX,
168#endif
169 },
170#endif
171};
172
173int nr_ports = ARRAY_SIZE(bfin_serial_resource);
174
175#define DRIVER_NAME "bfin-uart"
176
177static void bfin_serial_hw_init(struct bfin_serial_port *uart)
178{
179#ifdef CONFIG_SERIAL_BFIN_UART0
180 peripheral_request(P_UART0_TX, DRIVER_NAME);
181 peripheral_request(P_UART0_RX, DRIVER_NAME);
182#endif
183
184#ifdef CONFIG_SERIAL_BFIN_UART1
185 peripheral_request(P_UART1_TX, DRIVER_NAME);
186 peripheral_request(P_UART1_RX, DRIVER_NAME);
187
188#ifdef CONFIG_BFIN_UART1_CTSRTS
189 peripheral_request(P_UART1_RTS, DRIVER_NAME);
190 peripheral_request(P_UART1_CTS, DRIVER_NAME);
191#endif
192#endif
193
194#ifdef CONFIG_SERIAL_BFIN_UART2
195 peripheral_request(P_UART2_TX, DRIVER_NAME);
196 peripheral_request(P_UART2_RX, DRIVER_NAME);
197#endif
198
199#ifdef CONFIG_SERIAL_BFIN_UART3
200 peripheral_request(P_UART3_TX, DRIVER_NAME);
201 peripheral_request(P_UART3_RX, DRIVER_NAME);
202
203#ifdef CONFIG_BFIN_UART3_CTSRTS
204 peripheral_request(P_UART3_RTS, DRIVER_NAME);
205 peripheral_request(P_UART3_CTS, DRIVER_NAME);
206#endif
207#endif
208 SSYNC();
209#ifdef CONFIG_SERIAL_BFIN_CTSRTS
210 if (uart->cts_pin >= 0) {
211 gpio_request(uart->cts_pin, DRIVER_NAME);
212 gpio_direction_input(uart->cts_pin);
213 }
214
215 if (uart->rts_pin >= 0) {
216 gpio_request(uart->rts_pin, DRIVER_NAME);
217 gpio_direction_output(uart->rts_pin, 0);
218 }
219#endif
220}
diff --git a/include/asm-blackfin/mach-bf548/bfin_sir.h b/include/asm-blackfin/mach-bf548/bfin_sir.h
deleted file mode 100644
index c41f9cf00268..000000000000
--- a/include/asm-blackfin/mach-bf548/bfin_sir.h
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
21#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
27#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
28#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
29#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
30#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
31#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
32#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
33
34#ifdef CONFIG_SIR_BFIN_DMA
35struct dma_rx_buf {
36 char *buf;
37 int head;
38 int tail;
39 };
40#endif /* CONFIG_SIR_BFIN_DMA */
41
42struct bfin_sir_port {
43 unsigned char __iomem *membase;
44 unsigned int irq;
45 unsigned int lsr;
46 unsigned long clk;
47 struct net_device *dev;
48#ifdef CONFIG_SIR_BFIN_DMA
49 int tx_done;
50 struct dma_rx_buf rx_dma_buf;
51 struct timer_list rx_dma_timer;
52 int rx_dma_nrows;
53#endif /* CONFIG_SIR_BFIN_DMA */
54 unsigned int tx_dma_channel;
55 unsigned int rx_dma_channel;
56};
57
58struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
59
60struct bfin_sir_port_res {
61 unsigned long base_addr;
62 int irq;
63 unsigned int rx_dma_channel;
64 unsigned int tx_dma_channel;
65};
66
67struct bfin_sir_port_res bfin_sir_port_resource[] = {
68#ifdef CONFIG_BFIN_SIR0
69 {
70 0xFFC00400,
71 IRQ_UART0_RX,
72 CH_UART0_RX,
73 CH_UART0_TX,
74 },
75#endif
76#ifdef CONFIG_BFIN_SIR1
77 {
78 0xFFC02000,
79 IRQ_UART1_RX,
80 CH_UART1_RX,
81 CH_UART1_TX,
82 },
83#endif
84#ifdef CONFIG_BFIN_SIR2
85 {
86 0xFFC02100,
87 IRQ_UART2_RX,
88 CH_UART2_RX,
89 CH_UART2_TX,
90 },
91#endif
92#ifdef CONFIG_BFIN_SIR3
93 {
94 0xFFC03100,
95 IRQ_UART3_RX,
96 CH_UART3_RX,
97 CH_UART3_TX,
98 },
99#endif
100};
101
102int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
103
104struct bfin_sir_self {
105 struct bfin_sir_port *sir_port;
106 spinlock_t lock;
107 unsigned int open;
108 int speed;
109 int newspeed;
110
111 struct sk_buff *txskb;
112 struct sk_buff *rxskb;
113 struct net_device_stats stats;
114 struct device *dev;
115 struct irlap_cb *irlap;
116 struct qos_info qos;
117
118 iobuff_t tx_buff;
119 iobuff_t rx_buff;
120
121 struct work_struct work;
122 int mtt;
123};
124
125#define DRIVER_NAME "bfin_sir"
126
127static int bfin_sir_hw_init(void)
128{
129 int ret = -ENODEV;
130#ifdef CONFIG_BFIN_SIR0
131 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
132 if (ret)
133 return ret;
134 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
135 if (ret)
136 return ret;
137#endif
138
139#ifdef CONFIG_BFIN_SIR1
140 ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
141 if (ret)
142 return ret;
143 ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
144 if (ret)
145 return ret;
146#endif
147
148#ifdef CONFIG_BFIN_SIR2
149 ret = peripheral_request(P_UART2_TX, DRIVER_NAME);
150 if (ret)
151 return ret;
152 ret = peripheral_request(P_UART2_RX, DRIVER_NAME);
153 if (ret)
154 return ret;
155#endif
156
157#ifdef CONFIG_BFIN_SIR3
158 ret = peripheral_request(P_UART3_TX, DRIVER_NAME);
159 if (ret)
160 return ret;
161 ret = peripheral_request(P_UART3_RX, DRIVER_NAME);
162 if (ret)
163 return ret;
164#endif
165 return ret;
166}
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
deleted file mode 100644
index d6ee74ac0460..000000000000
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ /dev/null
@@ -1,190 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF548_FAMILY
36
37#include "bf548.h"
38#include "mem_map.h"
39#include "anomaly.h"
40
41#ifdef CONFIG_BF542
42#include "defBF542.h"
43#endif
44
45#ifdef CONFIG_BF544
46#include "defBF544.h"
47#endif
48
49#ifdef CONFIG_BF547
50#include "defBF547.h"
51#endif
52
53#ifdef CONFIG_BF548
54#include "defBF548.h"
55#endif
56
57#ifdef CONFIG_BF549
58#include "defBF549.h"
59#endif
60
61#if !defined(__ASSEMBLY__)
62#ifdef CONFIG_BF542
63#include "cdefBF542.h"
64#endif
65#ifdef CONFIG_BF544
66#include "cdefBF544.h"
67#endif
68#ifdef CONFIG_BF547
69#include "cdefBF547.h"
70#endif
71#ifdef CONFIG_BF548
72#include "cdefBF548.h"
73#endif
74#ifdef CONFIG_BF549
75#include "cdefBF549.h"
76#endif
77
78/* UART 1*/
79#define bfin_read_UART_THR() bfin_read_UART1_THR()
80#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
81#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
82#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
83#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
84#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
85#define bfin_read_UART_IER() bfin_read_UART1_IER()
86#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
87#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
88#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
89#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
90#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
91#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
92#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
93#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
94#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
95#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
96#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
97#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
98#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
99#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
100#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
101
102#endif
103
104/* MAP used DEFINES from BF533 to BF54x - so we don't need to change
105 * them in the driver, kernel, etc. */
106
107/* UART_IIR Register */
108#define STATUS(x) ((x << 1) & 0x06)
109#define STATUS_P1 0x02
110#define STATUS_P0 0x01
111
112/* UART 0*/
113
114/* DMA Channnel */
115#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX()
116#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val)
117#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX()
118#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val)
119#define CH_UART_RX CH_UART1_RX
120#define CH_UART_TX CH_UART1_TX
121
122/* System Interrupt Controller */
123#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX()
124#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val)
125#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX()
126#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val)
127#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR()
128#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val)
129#define IRQ_UART_RX IRQ_UART1_RX
130#define IRQ_UART_TX IRQ_UART1_TX
131#define IRQ_UART_ERROR IRQ_UART1_ERROR
132
133/* MMR Registers*/
134#define bfin_read_UART_THR() bfin_read_UART1_THR()
135#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
136#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
137#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
138#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
139#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
140#define bfin_read_UART_IER() bfin_read_UART1_IER()
141#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
142#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
143#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
144#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
145#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
146#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
147#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
148#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
149#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
150#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
151#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
152#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
153#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
154#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
155#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
156
157#define BFIN_UART_THR UART1_THR
158#define BFIN_UART_RBR UART1_RBR
159#define BFIN_UART_DLL UART1_DLL
160#define BFIN_UART_IER UART1_IER
161#define BFIN_UART_DLH UART1_DLH
162#define BFIN_UART_IIR UART1_IIR
163#define BFIN_UART_LCR UART1_LCR
164#define BFIN_UART_MCR UART1_MCR
165#define BFIN_UART_LSR UART1_LSR
166#define BFIN_UART_SCR UART1_SCR
167#define BFIN_UART_GCTL UART1_GCTL
168
169#define BFIN_UART_NR_PORTS 4
170
171#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
172#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
173#define OFFSET_GCTL 0x08 /* Global Control Register */
174#define OFFSET_LCR 0x0C /* Line Control Register */
175#define OFFSET_MCR 0x10 /* Modem Control Register */
176#define OFFSET_LSR 0x14 /* Line Status Register */
177#define OFFSET_MSR 0x18 /* Modem Status Register */
178#define OFFSET_SCR 0x1C /* SCR Scratch Register */
179#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
180#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
181#define OFFSET_THR 0x28 /* Transmit Holding register */
182#define OFFSET_RBR 0x2C /* Receive Buffer register */
183
184/* PLL_DIV Masks */
185#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
186#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
187#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
188#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
189
190#endif
diff --git a/include/asm-blackfin/mach-bf548/cdefBF542.h b/include/asm-blackfin/mach-bf548/cdefBF542.h
deleted file mode 100644
index 60b9f77576f1..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF542.h
+++ /dev/null
@@ -1,590 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF542.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF542_H
32#define _CDEF_BF542_H
33
34/* include all Core registers and bit definitions */
35#include "defBF542.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/mach-common/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
46
47/* ATAPI Registers */
48
49#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
50#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
51#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
52#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
53#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
54#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
55#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
56#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
57#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
58#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
59#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
60#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
61#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
62#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
63#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
64#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
65#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
66#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
67#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
68#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
69#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
70#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
71#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
72#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
73#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
74#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
75#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
76#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
77#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
78#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
79#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
80#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
81#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
82#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
83#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
84#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
85#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
86#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
87#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
88#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
89#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
90#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
91#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
92#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
93#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
94#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
95#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
96#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
97#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
98#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
99
100/* SDH Registers */
101
102#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
103#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
104#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
105#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
106#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
107#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
108#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
109#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
110#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
111#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
112#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
113#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
114#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
115#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
116#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
117#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
118#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
119#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
120#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
121#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
122#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
123#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
124#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
125#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
126#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
127#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
128#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
129#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
130#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
131#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
132#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
133#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
134#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
135#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
136#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
137#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
138#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
139#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
140#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
141#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
142#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
143#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
144#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
145#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
146#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
147#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
148#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
149#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
150#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
151#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
152#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
153#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
154#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
155#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
156#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
157#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
158#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
159#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
160#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
161#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
162#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
163#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
164
165/* USB Control Registers */
166
167#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
168#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
169#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
170#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
171#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
172#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
173#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
174#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
175#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
176#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
177#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
178#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
179#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
180#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
181#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
182#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
183#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
184#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
185#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
186#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
187#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
188#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
189#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
190#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
191#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
192#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
193
194/* USB Packet Control Registers */
195
196#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
197#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
198#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
199#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
200#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
201#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
202#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
203#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
204#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
205#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
206#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
207#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
208#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
209#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
210#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
211#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
212#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
213#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
214#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
215#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
216#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
217#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
218#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
219#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
220#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
221#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
222
223/* USB Endbfin_read_()oint FIFO Registers */
224
225#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
226#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
227#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
228#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
229#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
230#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
231#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
232#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
233#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
234#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
235#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
236#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
237#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
238#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
239#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
240#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
241
242/* USB OTG Control Registers */
243
244#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
245#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
246#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
247#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
248#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
249#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
250
251/* USB Phy Control Registers */
252
253#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
254#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
255#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
256#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
257#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
258#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
259#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
260#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
261#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
262#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
263
264/* (APHY_CNTRL is for ADI usage only) */
265
266#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
267#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
268
269/* (APHY_CALIB is for ADI usage only) */
270
271#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
272#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
273#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
274#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
275
276/* (PHY_TEST is for ADI usage only) */
277
278#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
279#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
280#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
281#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
282#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
283#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
284
285/* USB Endbfin_read_()oint 0 Control Registers */
286
287#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
288#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
289#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
290#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
291#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
292#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
293#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
294#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
295#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
296#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
297#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
298#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
299#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
300#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
301#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
302#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
303#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
304#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
305
306/* USB Endbfin_read_()oint 1 Control Registers */
307
308#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
309#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
310#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
311#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
312#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
313#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
314#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
315#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
316#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
317#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
318#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
319#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
320#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
321#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
322#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
323#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
324#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
325#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
326#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
327#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
328
329/* USB Endbfin_read_()oint 2 Control Registers */
330
331#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
332#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
333#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
334#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
335#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
336#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
337#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
338#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
339#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
340#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
341#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
342#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
343#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
344#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
345#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
346#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
347#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
348#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
349#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
350#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
351
352/* USB Endbfin_read_()oint 3 Control Registers */
353
354#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
355#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
356#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
357#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
358#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
359#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
360#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
361#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
362#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
363#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
364#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
365#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
366#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
367#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
368#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
369#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
370#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
371#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
372#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
373#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
374
375/* USB Endbfin_read_()oint 4 Control Registers */
376
377#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
378#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
379#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
380#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
381#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
382#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
383#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
384#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
385#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
386#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
387#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
388#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
389#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
390#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
391#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
392#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
393#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
394#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
395#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
396#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
397
398/* USB Endbfin_read_()oint 5 Control Registers */
399
400#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
401#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
402#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
403#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
404#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
405#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
406#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
407#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
408#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
409#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
410#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
411#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
412#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
413#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
414#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
415#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
416#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
417#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
418#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
419#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
420
421/* USB Endbfin_read_()oint 6 Control Registers */
422
423#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
424#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
425#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
426#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
427#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
428#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
429#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
430#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
431#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
432#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
433#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
434#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
435#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
436#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
437#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
438#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
439#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
440#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
441#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
442#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
443
444/* USB Endbfin_read_()oint 7 Control Registers */
445
446#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
447#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
448#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
449#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
450#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
451#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
452#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
453#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
454#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
455#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
456#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
457#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
458#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
459#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
460#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
461#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
462#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
463#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
464#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
465#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
466#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
467#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
468#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
469#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
470
471/* USB Channel 0 Config Registers */
472
473#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
474#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
475#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
476#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
477#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
478#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
479#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
480#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
481#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
482#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
483
484/* USB Channel 1 Config Registers */
485
486#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
487#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
488#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
489#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
490#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
491#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
492#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
493#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
494#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
495#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
496
497/* USB Channel 2 Config Registers */
498
499#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
500#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
501#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
502#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
503#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
504#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
505#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
506#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
507#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
508#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
509
510/* USB Channel 3 Config Registers */
511
512#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
513#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
514#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
515#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
516#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
517#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
518#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
519#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
520#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
521#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
522
523/* USB Channel 4 Config Registers */
524
525#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
526#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
527#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
528#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
529#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
530#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
531#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
532#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
533#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
534#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
535
536/* USB Channel 5 Config Registers */
537
538#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
539#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
540#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
541#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
542#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
543#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
544#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
545#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
546#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
547#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
548
549/* USB Channel 6 Config Registers */
550
551#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
552#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
553#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
554#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
555#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
556#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
557#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
558#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
559#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
560#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
561
562/* USB Channel 7 Config Registers */
563
564#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
565#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
566#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
567#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
568#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
569#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
570#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
571#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
572#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
573#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
574
575/* Keybfin_read_()ad Registers */
576
577#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
578#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
579#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
580#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
581#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
582#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
583#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
584#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
585#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
586#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
587#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
588#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
589
590#endif /* _CDEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h
deleted file mode 100644
index ea9b4ab496f3..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF544.h
+++ /dev/null
@@ -1,945 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF544.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF544_H
32#define _CDEF_BF544_H
33
34/* include all Core registers and bit definitions */
35#include "defBF544.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/mach-common/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* EPPI0 Registers */
84
85#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
86#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
87#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
88#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
89#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
90#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
91#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
92#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
93#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
94#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
95#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
96#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
97#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
98#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
99#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
100#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
101#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
102#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
103#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
104#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
105#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
106#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
107#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
108#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
109#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
110#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
111#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
112#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
113
114/* Two Wire Interface Registers (TWI1) */
115
116/* CAN Controller 1 Config 1 Registers */
117
118#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
119#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
120#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
121#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
122#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
123#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
124#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
125#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
126#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
127#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
128#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
129#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
130#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
131#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
132#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
133#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
134#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
135#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
136#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
137#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
138#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
139#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
140#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
141#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
142#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
143#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
144
145/* CAN Controller 1 Config 2 Registers */
146
147#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
148#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
149#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
150#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
151#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
152#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
153#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
154#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
155#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
156#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
157#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
158#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
159#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
160#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
161#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
162#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
163#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
164#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
165#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
166#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
167#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
168#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
169#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
170#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
171#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
172#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
173
174/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
175
176#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
177#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
178#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
179#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
180#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
181#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
182#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
183#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
184#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
185#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
186#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
187#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
188#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
189#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
190#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
191#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
192#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
193#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
194#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
195#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
196#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
197#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
198#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
199#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
200#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
201#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
202#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
203#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
204#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
205#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
206#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
207#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
208
209/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
210
211#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
212#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
213#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
214#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
215#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
216#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
217#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
218#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
219#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
220#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
221#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
222#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
223#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
224#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
225#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
226#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
227#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
228#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
229#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
230#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
231#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
232#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
233#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
234#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
235#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
236#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
237#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
238#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
239#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
240#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
241#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
242#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
243#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
244#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
245#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
246#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
247#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
248#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
249#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
250#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
251#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
252#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
253#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
254#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
255#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
256#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
257#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
258#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
259#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
260#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
261#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
262#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
263#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
264#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
265#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
266#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
267#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
268#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
269#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
270#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
271#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
272#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
273#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
274#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
275
276/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
277
278#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
279#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
280#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
281#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
282#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
283#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
284#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
285#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
286#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
287#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
288#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
289#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
290#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
291#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
292#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
293#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
294#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
295#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
296#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
297#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
298#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
299#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
300#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
301#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
302#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
303#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
304#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
305#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
306#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
307#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
308#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
309#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
310#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
311#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
312#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
313#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
314#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
315#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
316#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
317#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
318#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
319#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
320#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
321#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
322#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
323#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
324#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
325#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
326#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
327#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
328#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
329#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
330#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
331#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
332#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
333#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
334#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
335#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
336#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
337#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
338#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
339#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
340#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
341#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
342
343/* CAN Controller 1 Mailbox Data Registers */
344
345#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
346#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
347#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
348#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
349#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
350#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
351#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
352#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
353#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
354#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
355#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
356#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
357#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
358#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
359#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
360#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
361#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
362#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
363#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
364#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
365#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
366#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
367#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
368#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
369#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
370#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
371#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
372#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
373#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
374#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
375#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
376#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
377#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
378#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
379#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
380#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
381#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
382#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
383#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
384#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
385#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
386#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
387#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
388#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
389#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
390#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
391#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
392#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
393#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
394#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
395#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
396#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
397#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
398#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
399#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
400#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
401#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
402#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
403#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
404#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
405#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
406#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
407#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
408#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
409#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
410#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
411#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
412#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
413#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
414#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
415#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
416#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
417#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
418#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
419#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
420#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
421#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
422#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
423#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
424#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
425#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
426#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
427#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
428#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
429#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
430#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
431#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
432#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
433#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
434#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
435#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
436#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
437#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
438#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
439#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
440#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
441#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
442#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
443#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
444#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
445#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
446#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
447#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
448#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
449#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
450#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
451#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
452#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
453#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
454#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
455#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
456#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
457#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
458#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
459#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
460#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
461#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
462#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
463#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
464#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
465#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
466#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
467#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
468#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
469#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
470#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
471#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
472#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
473#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
474#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
475#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
476#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
477#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
478#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
479#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
480#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
481#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
482#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
483#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
484#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
485#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
486#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
487#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
488#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
489#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
490#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
491#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
492#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
493#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
494#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
495#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
496#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
497#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
498#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
499#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
500#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
501#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
502#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
503#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
504#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
505#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
506#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
507#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
508#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
509#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
510#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
511#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
512#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
513#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
514#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
515#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
516#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
517#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
518#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
519#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
520#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
521#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
522#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
523#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
524#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
525#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
526#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
527#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
528#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
529#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
530#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
531#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
532#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
533#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
534#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
535#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
536#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
537#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
538#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
539#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
540#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
541#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
542#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
543#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
544#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
545#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
546#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
547#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
548#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
549#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
550#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
551#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
552#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
553#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
554#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
555#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
556#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
557#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
558#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
559#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
560#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
561#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
562#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
563#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
564#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
565#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
566#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
567#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
568#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
569#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
570#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
571#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
572#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
573#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
574#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
575#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
576#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
577#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
578#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
579#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
580#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
581#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
582#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
583#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
584#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
585#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
586#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
587#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
588#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
589#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
590#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
591#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
592#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
593#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
594#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
595#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
596#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
597#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
598#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
599#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
600#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
601
602/* CAN Controller 1 Mailbox Data Registers */
603
604#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
605#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
606#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
607#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
608#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
609#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
610#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
611#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
612#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
613#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
614#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
615#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
616#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
617#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
618#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
619#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
620#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
621#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
622#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
623#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
624#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
625#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
626#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
627#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
628#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
629#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
630#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
631#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
632#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
633#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
634#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
635#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
636#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
637#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
638#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
639#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
640#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
641#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
642#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
643#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
644#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
645#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
646#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
647#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
648#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
649#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
650#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
651#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
652#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
653#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
654#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
655#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
656#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
657#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
658#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
659#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
660#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
661#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
662#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
663#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
664#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
665#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
666#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
667#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
668#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
669#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
670#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
671#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
672#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
673#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
674#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
675#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
676#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
677#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
678#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
679#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
680#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
681#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
682#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
683#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
684#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
685#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
686#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
687#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
688#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
689#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
690#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
691#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
692#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
693#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
694#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
695#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
696#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
697#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
698#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
699#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
700#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
701#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
702#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
703#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
704#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
705#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
706#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
707#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
708#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
709#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
710#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
711#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
712#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
713#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
714#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
715#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
716#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
717#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
718#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
719#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
720#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
721#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
722#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
723#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
724#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
725#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
726#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
727#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
728#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
729#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
730#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
731#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
732#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
733#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
734#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
735#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
736#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
737#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
738#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
739#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
740#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
741#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
742#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
743#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
744#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
745#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
746#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
747#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
748#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
749#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
750#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
751#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
752#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
753#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
754#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
755#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
756#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
757#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
758#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
759#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
760#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
761#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
762#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
763#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
764#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
765#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
766#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
767#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
768#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
769#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
770#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
771#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
772#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
773#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
774#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
775#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
776#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
777#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
778#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
779#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
780#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
781#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
782#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
783#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
784#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
785#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
786#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
787#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
788#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
789#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
790#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
791#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
792#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
793#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
794#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
795#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
796#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
797#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
798#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
799#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
800#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
801#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
802#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
803#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
804#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
805#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
806#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
807#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
808#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
809#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
810#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
811#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
812#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
813#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
814#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
815#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
816#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
817#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
818#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
819#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
820#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
821#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
822#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
823#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
824#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
825#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
826#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
827#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
828#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
829#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
830#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
831#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
832#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
833#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
834#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
835#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
836#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
837#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
838#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
839#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
840#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
841#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
842#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
843#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
844#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
845#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
846#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
847#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
848#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
849#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
850#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
851#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
852#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
853#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
854#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
855#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
856#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
857#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
858#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
859#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
860
861/* HOST Port Registers */
862
863#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
864#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
865#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
866#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
867#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
868#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
869
870/* Pixel Combfin_read_()ositor (PIXC) Registers */
871
872#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
873#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
874#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
875#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
876#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
877#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
878#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
879#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
880#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
881#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
882#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
883#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
884#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
885#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
886#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
887#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
888#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
889#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
890#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
891#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
892#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
893#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
894#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
895#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
896#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
897#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
898#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
899#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
900#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
901#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
902#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
903#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
904#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
905#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
906#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
907#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
908#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
909#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
910
911/* Handshake MDMA 0 Registers */
912
913#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
914#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
915#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
916#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
917#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
918#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
919#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
920#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
921#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
922#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
923#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
924#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
925#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
926#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
927
928/* Handshake MDMA 1 Registers */
929
930#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
931#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
932#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
933#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
934#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
935#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
936#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
937#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
938#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
939#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
940#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
941#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
942#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
943#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
944
945#endif /* _CDEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h
deleted file mode 100644
index ba716277c00d..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF547.h
+++ /dev/null
@@ -1,832 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF547.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF548_H
32#define _CDEF_BF548_H
33
34/* include all Core registers and bit definitions */
35#include "defBF548.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/mach-common/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* SPORT0 Registers */
84
85#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
86#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
87#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
88#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
89#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
91#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
92#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
93#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
94#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
95#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
96#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
97#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
98#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
99#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
100#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
101#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
102#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
103#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
104#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
105#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
106#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
107#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
108#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
109#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
110#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
111#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
112#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
113#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
114#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
115#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
116#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
117#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
118#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
119#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
120#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
121#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
122#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
123#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
124#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
125#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
126#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
127#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
128#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
129
130/* EPPI0 Registers */
131
132#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
133#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
134#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
135#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
136#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
137#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
138#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
139#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
140#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
141#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
142#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
143#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
144#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
145#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
146#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
147#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
148#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
149#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
150#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
151#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
152#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
153#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
154#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
155#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
156#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
157#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
158#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
159#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
160
161/* UART2 Registers */
162
163#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
164#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
165#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
166#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
167#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
168#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
169#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
170#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
171#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
172#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
173#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
174#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
175#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
176#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
177#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
178#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
179#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
180#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
181#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
182#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
183#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
184#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
185
186/* Two Wire Interface Registers (TWI1) */
187
188/* SPI2 Registers */
189
190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
191#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
192#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
193#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
194#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
195#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
196#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
197#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
198#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
199#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
200#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
201#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
202#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
203#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
204
205/* ATAPI Registers */
206
207#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
208#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
209#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
210#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
211#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
212#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
213#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
214#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
215#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
216#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
217#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
218#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
219#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
220#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
221#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
222#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
223#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
224#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
225#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
226#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
227#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
228#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
229#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
230#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
231#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
232#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
233#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
234#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
235#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
236#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
237#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
238#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
239#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
240#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
241#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
242#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
243#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
244#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
245#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
246#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
247#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
248#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
249#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
250#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
251#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
252#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
253#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
254#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
255#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
256#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
257
258/* SDH Registers */
259
260#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
261#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
262#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
263#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
264#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
265#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
266#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
267#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
268#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
269#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
270#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
271#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
272#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
273#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
274#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
275#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
276#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
277#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
278#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
279#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
280#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
281#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
282#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
283#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
284#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
285#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
286#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
287#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
288#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
289#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
290#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
291#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
292#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
293#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
294#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
295#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
296#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
297#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
298#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
299#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
300#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
301#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
302#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
303#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
304#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
305#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
306#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
307#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
308#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
309#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
310#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
311#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
312#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
313#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
314#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
315#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
316#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
317#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
318#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
319#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
320#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
321#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
322
323/* HOST Port Registers */
324
325#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
326#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
327#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
328#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
329#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
330#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
331
332/* USB Control Registers */
333
334#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
335#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
336#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
337#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
338#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
339#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
340#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
341#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
342#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
343#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
344#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
345#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
346#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
347#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
348#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
349#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
350#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
351#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
352#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
353#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
354#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
355#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
356#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
357#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
358#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
359#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
360
361/* USB Packet Control Registers */
362
363#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
364#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
365#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
366#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
367#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
368#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
369#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
370#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
371#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
372#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
373#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
374#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
375#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
376#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
377#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
378#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
379#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
380#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
381#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
382#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
383#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
384#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
385#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
386#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
387#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
388#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
389
390/* USB Endbfin_read_()oint FIFO Registers */
391
392#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
393#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
394#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
395#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
396#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
397#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
398#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
399#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
400#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
401#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
402#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
403#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
404#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
405#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
406#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
407#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
408
409/* USB OTG Control Registers */
410
411#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
412#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
413#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
414#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
415#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
416#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
417
418/* USB Phy Control Registers */
419
420#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
421#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
422#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
423#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
424#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
425#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
426#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
427#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
428#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
429#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
430
431/* (APHY_CNTRL is for ADI usage only) */
432
433#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
434#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
435
436/* (APHY_CALIB is for ADI usage only) */
437
438#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
439#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
440#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
441#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
442
443/* (PHY_TEST is for ADI usage only) */
444
445#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
446#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
447#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
448#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
449#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
450#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
451
452/* USB Endbfin_read_()oint 0 Control Registers */
453
454#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
455#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
456#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
457#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
458#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
459#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
460#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
461#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
462#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
463#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
464#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
465#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
466#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
467#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
468#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
469#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
470#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
471#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
472
473/* USB Endbfin_read_()oint 1 Control Registers */
474
475#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
476#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
477#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
478#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
479#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
480#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
481#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
482#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
483#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
484#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
485#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
486#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
487#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
488#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
489#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
490#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
491#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
492#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
493#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
494#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
495
496/* USB Endbfin_read_()oint 2 Control Registers */
497
498#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
499#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
500#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
501#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
502#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
503#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
504#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
505#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
506#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
507#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
508#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
509#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
510#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
511#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
512#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
513#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
514#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
515#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
516#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
517#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
518
519/* USB Endbfin_read_()oint 3 Control Registers */
520
521#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
522#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
523#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
524#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
525#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
526#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
527#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
528#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
529#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
530#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
531#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
532#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
533#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
534#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
535#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
536#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
537#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
538#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
539#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
540#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
541
542/* USB Endbfin_read_()oint 4 Control Registers */
543
544#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
545#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
546#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
547#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
548#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
549#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
550#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
551#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
552#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
553#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
554#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
555#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
556#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
557#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
558#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
559#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
560#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
561#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
562#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
563#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
564
565/* USB Endbfin_read_()oint 5 Control Registers */
566
567#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
568#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
569#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
570#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
571#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
572#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
573#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
574#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
575#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
576#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
577#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
578#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
579#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
580#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
581#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
582#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
583#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
584#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
585#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
586#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
587
588/* USB Endbfin_read_()oint 6 Control Registers */
589
590#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
591#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
592#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
593#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
594#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
595#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
596#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
597#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
598#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
599#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
600#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
601#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
602#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
603#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
604#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
605#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
606#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
607#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
608#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
609#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
610
611/* USB Endbfin_read_()oint 7 Control Registers */
612
613#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
614#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
615#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
616#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
617#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
618#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
619#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
620#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
621#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
622#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
623#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
624#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
625#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
626#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
627#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
628#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
629#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
630#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
631#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
632#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
633#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
634#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
635#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
636#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
637
638/* USB Channel 0 Config Registers */
639
640#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
641#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
642#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
643#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
644#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
645#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
646#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
647#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
648#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
649#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
650
651/* USB Channel 1 Config Registers */
652
653#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
654#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
655#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
656#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
657#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
658#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
659#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
660#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
661#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
662#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
663
664/* USB Channel 2 Config Registers */
665
666#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
667#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
668#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
669#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
670#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
671#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
672#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
673#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
674#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
675#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
676
677/* USB Channel 3 Config Registers */
678
679#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
680#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
681#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
682#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
683#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
684#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
685#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
686#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
687#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
688#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
689
690/* USB Channel 4 Config Registers */
691
692#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
693#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
694#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
695#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
696#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
697#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
698#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
699#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
700#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
701#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
702
703/* USB Channel 5 Config Registers */
704
705#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
706#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
707#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
708#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
709#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
710#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
711#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
712#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
713#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
714#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
715
716/* USB Channel 6 Config Registers */
717
718#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
719#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
720#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
721#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
722#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
723#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
724#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
725#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
726#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
727#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
728
729/* USB Channel 7 Config Registers */
730
731#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
732#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
733#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
734#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
735#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
736#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
737#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
738#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
739#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
740#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
741
742/* Keybfin_read_()ad Registers */
743
744#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
745#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
746#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
747#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
748#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
749#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
750#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
751#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
752#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
753#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
754#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
755#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
756
757/* Pixel Combfin_read_()ositor (PIXC) Registers */
758
759#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
760#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
761#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
762#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
763#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
764#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
765#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
766#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
767#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
768#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
769#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
770#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
771#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
772#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
773#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
774#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
775#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
776#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
777#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
778#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
779#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
780#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
781#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
782#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
783#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
784#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
785#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
786#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
787#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
788#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
789#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
790#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
791#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
792#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
793#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
794#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
795#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
796#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
797
798/* Handshake MDMA 0 Registers */
799
800#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
801#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
802#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
803#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
804#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
805#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
806#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
807#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
808#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
809#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
810#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
811#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
812#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
813#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
814
815/* Handshake MDMA 1 Registers */
816
817#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
818#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
819#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
820#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
821#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
822#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
823#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
824#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
825#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
826#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
827#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
828#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
829#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
830#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
831
832#endif /* _CDEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h
deleted file mode 100644
index ae971ebff6a0..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF548.h
+++ /dev/null
@@ -1,1577 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF548_H
32#define _CDEF_BF548_H
33
34/* include all Core registers and bit definitions */
35#include "defBF548.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/mach-common/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* SPORT0 Registers */
84
85#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
86#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
87#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
88#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
89#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
91#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
92#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
93#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
94#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
95#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
96#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
97#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
98#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
99#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
100#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
101#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
102#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
103#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
104#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
105#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
106#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
107#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
108#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
109#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
110#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
111#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
112#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
113#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
114#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
115#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
116#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
117#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
118#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
119#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
120#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
121#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
122#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
123#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
124#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
125#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
126#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
127#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
128#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
129
130/* EPPI0 Registers */
131
132#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
133#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
134#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
135#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
136#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
137#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
138#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
139#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
140#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
141#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
142#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
143#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
144#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
145#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
146#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
147#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
148#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
149#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
150#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
151#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
152#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
153#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
154#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
155#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
156#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
157#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
158#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
159#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
160
161/* UART2 Registers */
162
163#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
164#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
165#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
166#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
167#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
168#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
169#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
170#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
171#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
172#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
173#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
174#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
175#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
176#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
177#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
178#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
179#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
180#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
181#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
182#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
183#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
184#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
185
186/* Two Wire Interface Registers (TWI1) */
187
188/* SPI2 Registers */
189
190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
191#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
192#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
193#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
194#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
195#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
196#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
197#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
198#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
199#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
200#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
201#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
202#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
203#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
204
205/* CAN Controller 1 Config 1 Registers */
206
207#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
208#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
209#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
210#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
211#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
212#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
213#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
214#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
215#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
216#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
217#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
218#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
219#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
220#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
221#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
222#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
223#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
224#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
225#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
226#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
227#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
228#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
229#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
230#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
231#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
232#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
233
234/* CAN Controller 1 Config 2 Registers */
235
236#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
237#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
238#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
239#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
240#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
241#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
242#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
243#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
244#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
245#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
246#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
247#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
248#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
249#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
250#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
251#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
252#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
253#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
254#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
255#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
256#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
257#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
258#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
259#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
260#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
261#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
262
263/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
264
265#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
266#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
267#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
268#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
269#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
270#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
271#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
272#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
273#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
274#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
275#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
276#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
277#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
278#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
279#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
280#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
281#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
282#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
283#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
284#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
285#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
286#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
287#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
288#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
289#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
290#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
291#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
292#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
293#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
294#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
295#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
296#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
297
298/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
299
300#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
301#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
302#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
303#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
304#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
305#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
306#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
307#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
308#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
309#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
310#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
311#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
312#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
313#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
314#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
315#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
316#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
317#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
318#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
319#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
320#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
321#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
322#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
323#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
324#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
325#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
326#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
327#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
328#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
329#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
330#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
331#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
332#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
333#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
334#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
335#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
336#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
337#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
338#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
339#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
340#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
341#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
342#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
343#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
344#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
345#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
346#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
347#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
348#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
349#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
350#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
351#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
352#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
353#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
354#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
355#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
356#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
357#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
358#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
359#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
360#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
361#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
362#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
363#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
364
365/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
366
367#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
368#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
369#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
370#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
371#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
372#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
373#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
374#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
375#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
376#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
377#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
378#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
379#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
380#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
381#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
382#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
383#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
384#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
385#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
386#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
387#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
388#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
389#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
390#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
391#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
392#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
393#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
394#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
395#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
396#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
397#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
398#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
399#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
400#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
401#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
402#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
403#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
404#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
405#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
406#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
407#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
408#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
409#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
410#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
411#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
412#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
413#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
414#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
415#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
416#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
417#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
418#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
419#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
420#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
421#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
422#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
423#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
424#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
425#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
426#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
427#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
428#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
429#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
430#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
431
432/* CAN Controller 1 Mailbox Data Registers */
433
434#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
435#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
436#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
437#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
438#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
439#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
440#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
441#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
442#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
443#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
444#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
445#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
446#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
447#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
448#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
449#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
450#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
451#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
452#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
453#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
454#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
455#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
456#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
457#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
458#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
459#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
460#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
461#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
462#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
463#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
464#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
465#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
466#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
467#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
468#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
469#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
470#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
471#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
472#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
473#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
474#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
475#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
476#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
477#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
478#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
479#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
480#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
481#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
482#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
483#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
484#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
485#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
486#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
487#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
488#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
489#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
490#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
491#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
492#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
493#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
494#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
495#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
496#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
497#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
498#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
499#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
500#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
501#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
502#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
503#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
504#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
505#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
506#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
507#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
508#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
509#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
510#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
511#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
512#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
513#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
514#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
515#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
516#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
517#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
518#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
519#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
520#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
521#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
522#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
523#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
524#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
525#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
526#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
527#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
528#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
529#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
530#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
531#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
532#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
533#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
534#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
535#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
536#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
537#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
538#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
539#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
540#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
541#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
542#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
543#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
544#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
545#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
546#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
547#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
548#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
549#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
550#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
551#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
552#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
553#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
554#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
555#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
556#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
557#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
558#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
559#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
560#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
561#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
562#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
563#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
564#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
565#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
566#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
567#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
568#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
569#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
570#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
571#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
572#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
573#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
574#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
575#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
576#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
577#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
578#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
579#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
580#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
581#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
582#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
583#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
584#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
585#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
586#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
587#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
588#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
589#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
590#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
591#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
592#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
593#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
594#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
595#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
596#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
597#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
598#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
599#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
600#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
601#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
602#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
603#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
604#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
605#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
606#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
607#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
608#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
609#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
610#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
611#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
612#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
613#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
614#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
615#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
616#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
617#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
618#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
619#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
620#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
621#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
622#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
623#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
624#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
625#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
626#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
627#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
628#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
629#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
630#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
631#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
632#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
633#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
634#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
635#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
636#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
637#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
638#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
639#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
640#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
641#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
642#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
643#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
644#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
645#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
646#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
647#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
648#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
649#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
650#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
651#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
652#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
653#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
654#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
655#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
656#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
657#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
658#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
659#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
660#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
661#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
662#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
663#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
664#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
665#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
666#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
667#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
668#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
669#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
670#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
671#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
672#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
673#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
674#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
675#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
676#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
677#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
678#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
679#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
680#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
681#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
682#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
683#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
684#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
685#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
686#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
687#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
688#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
689#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
690
691/* CAN Controller 1 Mailbox Data Registers */
692
693#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
694#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
695#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
696#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
697#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
698#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
699#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
700#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
701#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
702#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
703#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
704#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
705#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
706#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
707#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
708#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
709#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
710#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
711#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
712#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
713#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
714#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
715#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
716#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
717#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
718#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
719#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
720#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
721#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
722#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
723#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
724#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
725#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
726#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
727#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
728#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
729#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
730#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
731#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
732#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
733#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
734#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
735#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
736#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
737#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
738#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
739#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
740#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
741#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
742#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
743#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
744#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
745#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
746#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
747#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
748#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
749#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
750#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
751#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
752#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
753#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
754#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
755#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
756#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
757#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
758#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
759#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
760#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
761#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
762#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
763#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
764#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
765#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
766#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
767#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
768#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
769#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
770#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
771#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
772#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
773#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
774#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
775#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
776#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
777#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
778#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
779#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
780#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
781#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
782#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
783#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
784#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
785#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
786#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
787#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
788#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
789#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
790#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
791#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
792#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
793#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
794#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
795#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
796#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
797#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
798#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
799#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
800#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
801#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
802#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
803#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
804#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
805#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
806#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
807#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
808#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
809#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
810#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
811#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
812#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
813#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
814#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
815#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
816#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
817#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
818#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
819#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
820#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
821#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
822#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
823#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
824#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
825#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
826#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
827#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
828#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
829#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
830#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
831#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
832#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
833#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
834#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
835#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
836#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
837#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
838#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
839#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
840#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
841#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
842#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
843#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
844#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
845#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
846#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
847#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
848#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
849#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
850#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
851#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
852#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
853#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
854#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
855#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
856#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
857#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
858#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
859#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
860#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
861#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
862#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
863#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
864#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
865#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
866#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
867#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
868#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
869#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
870#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
871#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
872#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
873#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
874#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
875#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
876#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
877#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
878#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
879#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
880#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
881#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
882#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
883#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
884#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
885#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
886#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
887#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
888#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
889#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
890#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
891#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
892#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
893#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
894#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
895#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
896#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
897#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
898#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
899#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
900#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
901#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
902#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
903#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
904#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
905#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
906#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
907#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
908#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
909#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
910#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
911#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
912#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
913#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
914#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
915#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
916#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
917#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
918#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
919#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
920#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
921#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
922#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
923#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
924#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
925#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
926#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
927#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
928#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
929#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
930#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
931#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
932#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
933#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
934#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
935#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
936#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
937#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
938#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
939#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
940#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
941#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
942#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
943#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
944#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
945#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
946#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
947#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
948#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
949
950/* ATAPI Registers */
951
952#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
953#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
954#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
955#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
956#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
957#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
958#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
959#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
960#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
961#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
962#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
963#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
964#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
965#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
966#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
967#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
968#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
969#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
970#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
971#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
972#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
973#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
974#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
975#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
976#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
977#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
978#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
979#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
980#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
981#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
982#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
983#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
984#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
985#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
986#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
987#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
988#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
989#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
990#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
991#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
992#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
993#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
994#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
995#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
996#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
997#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
998#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
999#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
1000#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
1001#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
1002
1003/* SDH Registers */
1004
1005#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
1006#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
1007#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
1008#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
1009#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
1010#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
1011#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
1012#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
1013#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
1014#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
1015#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
1016#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
1017#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
1018#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
1019#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
1020#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
1021#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
1022#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
1023#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1024#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1025#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1026#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1027#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1028#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1029#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1030#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1031#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1032#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1033#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1034#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1035#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1036#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1037#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1038#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1039#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1040#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1041#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1042#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1043#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1044#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1045#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1046#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1047#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1048#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1049#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1050#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1051#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1052#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1053#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1054#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1055#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1056#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1057#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1058#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1059#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1060#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1061#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1062#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1063#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1064#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1065#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1066#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1067
1068/* HOST Port Registers */
1069
1070#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1071#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1072#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1073#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1074#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1075#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1076
1077/* USB Control Registers */
1078
1079#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1080#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1081#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1082#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1083#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1084#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1085#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1086#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1087#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1088#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1089#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1090#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1091#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1092#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1093#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1094#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1095#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1096#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1097#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1098#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1099#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1100#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1101#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1102#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1103#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1104#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1105
1106/* USB Packet Control Registers */
1107
1108#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1109#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1110#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1111#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1112#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1113#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1114#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1115#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1116#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1117#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1118#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1119#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1120#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1121#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1122#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1123#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1124#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1125#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1126#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1127#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1128#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1129#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1130#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1131#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1132#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1133#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1134
1135/* USB Endbfin_read_()oint FIFO Registers */
1136
1137#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1138#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1139#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1140#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1141#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1142#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1143#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1144#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1145#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1146#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1147#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1148#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1149#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1150#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1151#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1152#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1153
1154/* USB OTG Control Registers */
1155
1156#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1157#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1158#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1159#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1160#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1161#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1162
1163/* USB Phy Control Registers */
1164
1165#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1166#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1167#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1168#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1169#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1170#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1171#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1172#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1173#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1174#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1175
1176/* (APHY_CNTRL is for ADI usage only) */
1177
1178#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1179#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1180
1181/* (APHY_CALIB is for ADI usage only) */
1182
1183#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1184#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1185#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1186#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1187
1188/* (PHY_TEST is for ADI usage only) */
1189
1190#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1191#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1192#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1193#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1194#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1195#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1196
1197/* USB Endbfin_read_()oint 0 Control Registers */
1198
1199#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1200#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1201#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1202#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1203#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1204#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1205#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1206#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1207#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1208#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1209#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1210#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1211#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1212#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1213#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1214#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1215#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1216#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1217
1218/* USB Endbfin_read_()oint 1 Control Registers */
1219
1220#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1221#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1222#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1223#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1224#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1225#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1226#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1227#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1228#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1229#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1230#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1231#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1232#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1233#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1234#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1235#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1236#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1237#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1238#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1239#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1240
1241/* USB Endbfin_read_()oint 2 Control Registers */
1242
1243#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1244#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1245#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1246#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1247#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1248#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1249#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1250#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1251#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1252#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1253#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1254#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1255#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1256#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1257#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1258#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1259#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1260#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1261#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1262#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1263
1264/* USB Endbfin_read_()oint 3 Control Registers */
1265
1266#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1267#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1268#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1269#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1270#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1271#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1272#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1273#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1274#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1275#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1276#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1277#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1278#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1279#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1280#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1281#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1282#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1283#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1284#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1285#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1286
1287/* USB Endbfin_read_()oint 4 Control Registers */
1288
1289#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1290#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1291#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1292#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1293#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1294#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1295#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1296#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1297#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1298#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1299#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1300#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1301#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1302#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1303#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1304#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1305#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1306#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1307#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1308#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1309
1310/* USB Endbfin_read_()oint 5 Control Registers */
1311
1312#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1313#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1314#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1315#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1316#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1317#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1318#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1319#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1320#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1321#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1322#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1323#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1324#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1325#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1326#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1327#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1328#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1329#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1330#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1331#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1332
1333/* USB Endbfin_read_()oint 6 Control Registers */
1334
1335#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1336#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1337#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1338#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1339#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1340#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1341#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1342#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1343#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1344#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1345#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1346#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1347#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1348#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1349#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1350#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1351#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1352#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1353#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1354#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1355
1356/* USB Endbfin_read_()oint 7 Control Registers */
1357
1358#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1359#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1360#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1361#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1362#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1363#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1364#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1365#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1366#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1367#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1368#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1369#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1370#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1371#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1372#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1373#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1374#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1375#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1376#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1377#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1378#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1379#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1380#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1381#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1382
1383/* USB Channel 0 Config Registers */
1384
1385#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1386#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1387#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1388#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1389#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1390#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1391#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1392#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1393#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1394#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1395
1396/* USB Channel 1 Config Registers */
1397
1398#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1399#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1400#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1401#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1402#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1403#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1404#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1405#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1406#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1407#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1408
1409/* USB Channel 2 Config Registers */
1410
1411#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1412#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1413#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1414#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1415#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1416#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1417#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1418#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1419#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1420#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1421
1422/* USB Channel 3 Config Registers */
1423
1424#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1425#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1426#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1427#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1428#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1429#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1430#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1431#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1432#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1433#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1434
1435/* USB Channel 4 Config Registers */
1436
1437#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1438#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1439#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1440#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1441#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1442#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1443#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1444#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1445#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1446#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1447
1448/* USB Channel 5 Config Registers */
1449
1450#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1451#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1452#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1453#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1454#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1455#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1456#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1457#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1458#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1459#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1460
1461/* USB Channel 6 Config Registers */
1462
1463#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1464#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1465#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1466#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1467#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1468#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1469#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1470#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1471#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1472#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1473
1474/* USB Channel 7 Config Registers */
1475
1476#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1477#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1478#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1479#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1480#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1481#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1482#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1483#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1484#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1485#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1486
1487/* Keybfin_read_()ad Registers */
1488
1489#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1490#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1491#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1492#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1493#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1494#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1495#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1496#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1497#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1498#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1499#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1500#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1501
1502/* Pixel Combfin_read_()ositor (PIXC) Registers */
1503
1504#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1505#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1506#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1507#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1508#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1509#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1510#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1511#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1512#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1513#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1514#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1515#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1516#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1517#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1518#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1519#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1520#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1521#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1522#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1523#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1524#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1525#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1526#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1527#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1528#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1529#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1530#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1531#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1532#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1533#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1534#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1535#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1536#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1537#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1538#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1539#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1540#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1541#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1542
1543/* Handshake MDMA 0 Registers */
1544
1545#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1546#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1547#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1548#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1549#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1550#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1551#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1552#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1553#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1554#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1555#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1556#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1557#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1558#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1559
1560/* Handshake MDMA 1 Registers */
1561
1562#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1563#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1564#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1565#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1566#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1567#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1568#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1569#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1570#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1571#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1572#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1573#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1574#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1575#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1576
1577#endif /* _CDEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h
deleted file mode 100644
index 92d07d961999..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF549.h
+++ /dev/null
@@ -1,1863 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf549/cdefBF549.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF549_H
32#define _CDEF_BF549_H
33
34/* include all Core registers and bit definitions */
35#include "defBF549.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/mach-common/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* SPORT0 Registers */
84
85#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
86#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
87#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
88#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
89#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
91#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
92#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
93#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
94#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
95#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
96#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
97#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
98#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
99#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
100#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
101#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
102#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
103#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
104#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
105#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
106#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
107#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
108#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
109#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
110#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
111#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
112#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
113#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
114#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
115#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
116#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
117#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
118#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
119#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
120#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
121#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
122#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
123#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
124#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
125#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
126#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
127#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
128#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
129
130/* EPPI0 Registers */
131
132#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
133#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
134#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
135#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
136#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
137#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
138#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
139#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
140#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
141#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
142#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
143#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
144#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
145#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
146#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
147#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
148#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
149#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
150#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
151#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
152#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
153#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
154#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
155#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
156#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
157#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
158#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
159#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
160
161/* UART2 Registers */
162
163#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
164#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
165#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
166#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
167#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
168#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
169#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
170#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
171#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
172#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
173#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
174#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
175#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
176#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
177#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
178#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
179#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
180#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
181#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
182#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
183#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
184#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
185
186/* Two Wire Interface Registers (TWI1) */
187
188/* SPI2 Registers */
189
190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
191#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
192#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
193#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
194#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
195#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
196#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
197#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
198#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
199#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
200#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
201#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
202#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
203#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
204
205/* MXVR Registers */
206
207#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
208#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
209#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
210#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
211#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
212#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
213#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
214#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
215#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
216#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
217#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
218#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
219#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
220#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
221#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
222#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
223#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
224#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
225#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
226#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
227#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
228#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
229#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
230#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
231#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
232#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
233#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
234#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
235
236/* MXVR Allocation Table Registers */
237
238#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
239#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
240#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
241#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
242#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
243#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
244#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
245#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
246#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
247#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
248#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
249#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
250#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
251#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
252#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
253#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
254#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
255#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
256#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
257#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
258#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
259#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
260#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
261#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
262#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
263#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
264#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
265#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
266#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
267#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
268
269/* MXVR Channel Assign Registers */
270
271#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
272#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
273#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
274#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
275#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
276#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
277#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
278#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
279#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
280#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
281#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
282#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
283#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
284#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
285#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
286#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
287
288/* MXVR DMA0 Registers */
289
290#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
291#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
292#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR)
293#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR)
294#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
295#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
296#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR)
297#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR)
298#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
299#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
300
301/* MXVR DMA1 Registers */
302
303#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
304#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
305#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR)
306#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR)
307#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
308#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
309#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR)
310#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR)
311#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
312#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
313
314/* MXVR DMA2 Registers */
315
316#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
317#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
318#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR)
319#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR)
320#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
321#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
322#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR)
323#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR)
324#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
325#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
326
327/* MXVR DMA3 Registers */
328
329#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
330#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
331#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR)
332#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR)
333#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
334#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
335#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR)
336#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR)
337#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
338#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
339
340/* MXVR DMA4 Registers */
341
342#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
343#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
344#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR)
345#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR)
346#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
347#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
348#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR)
349#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR)
350#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
351#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
352
353/* MXVR DMA5 Registers */
354
355#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
356#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
357#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR)
358#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR)
359#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
360#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
361#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR)
362#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR)
363#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
364#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
365
366/* MXVR DMA6 Registers */
367
368#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
369#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
370#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR)
371#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR)
372#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
373#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
374#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR)
375#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR)
376#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
377#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
378
379/* MXVR DMA7 Registers */
380
381#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
382#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
383#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR)
384#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR)
385#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
386#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
387#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR)
388#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR)
389#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
390#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
391
392/* MXVR Asynch Packet Registers */
393
394#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
395#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
396#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR)
397#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR)
398#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR)
399#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR)
400#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR)
401#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR)
402#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR)
403#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR)
404
405/* MXVR Control Message Registers */
406
407#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
408#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
409#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR)
410#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR)
411#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR)
412#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR)
413#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR)
414#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR)
415#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR)
416#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR)
417
418/* MXVR Remote Read Registers */
419
420#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR)
421#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR)
422#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR)
423#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR)
424
425/* MXVR Pattern Data Registers */
426
427#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
428#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
429#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
430#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
431#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
432#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
433#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
434#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
435
436/* MXVR Frame Counter Registers */
437
438#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
439#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
440#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
441#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
442
443/* MXVR Routing Table Registers */
444
445#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
446#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
447#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
448#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
449#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
450#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
451#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
452#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
453#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
454#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
455#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
456#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
457#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
458#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
459#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
460#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
461#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
462#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
463#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
464#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
465#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
466#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
467#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
468#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
469#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
470#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
471#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
472#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
473#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
474#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
475
476/* MXVR Counter-Clock-Control Registers */
477
478#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
479#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
480#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
481#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
482#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
483#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
484#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
485#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
486#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
487#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
488#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
489#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
490
491/* CAN Controller 1 Config 1 Registers */
492
493#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
494#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
495#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
496#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
497#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
498#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
499#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
500#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
501#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
502#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
503#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
504#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
505#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
506#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
507#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
508#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
509#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
510#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
511#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
512#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
513#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
514#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
515#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
516#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
517#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
518#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
519
520/* CAN Controller 1 Config 2 Registers */
521
522#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
523#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
524#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
525#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
526#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
527#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
528#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
529#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
530#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
531#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
532#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
533#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
534#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
535#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
536#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
537#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
538#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
539#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
540#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
541#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
542#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
543#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
544#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
545#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
546#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
547#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
548
549/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
550
551#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
552#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
553#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
554#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
555#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
556#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
557#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
558#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
559#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
560#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
561#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
562#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
563#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
564#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
565#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
566#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
567#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
568#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
569#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
570#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
571#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
572#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
573#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
574#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
575#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
576#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
577#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
578#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
579#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
580#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
581#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
582#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
583
584/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
585
586#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
587#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
588#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
589#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
590#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
591#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
592#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
593#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
594#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
595#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
596#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
597#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
598#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
599#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
600#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
601#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
602#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
603#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
604#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
605#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
606#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
607#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
608#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
609#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
610#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
611#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
612#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
613#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
614#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
615#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
616#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
617#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
618#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
619#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
620#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
621#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
622#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
623#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
624#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
625#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
626#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
627#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
628#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
629#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
630#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
631#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
632#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
633#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
634#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
635#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
636#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
637#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
638#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
639#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
640#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
641#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
642#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
643#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
644#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
645#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
646#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
647#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
648#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
649#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
650
651/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
652
653#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
654#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
655#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
656#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
657#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
658#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
659#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
660#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
661#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
662#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
663#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
664#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
665#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
666#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
667#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
668#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
669#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
670#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
671#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
672#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
673#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
674#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
675#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
676#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
677#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
678#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
679#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
680#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
681#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
682#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
683#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
684#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
685#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
686#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
687#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
688#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
689#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
690#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
691#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
692#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
693#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
694#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
695#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
696#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
697#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
698#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
699#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
700#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
701#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
702#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
703#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
704#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
705#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
706#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
707#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
708#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
709#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
710#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
711#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
712#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
713#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
714#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
715#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
716#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
717
718/* CAN Controller 1 Mailbox Data Registers */
719
720#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
721#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
722#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
723#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
724#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
725#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
726#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
727#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
728#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
729#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
730#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
731#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
732#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
733#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
734#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
735#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
736#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
737#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
738#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
739#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
740#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
741#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
742#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
743#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
744#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
745#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
746#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
747#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
748#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
749#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
750#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
751#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
752#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
753#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
754#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
755#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
756#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
757#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
758#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
759#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
760#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
761#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
762#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
763#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
764#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
765#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
766#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
767#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
768#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
769#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
770#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
771#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
772#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
773#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
774#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
775#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
776#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
777#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
778#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
779#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
780#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
781#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
782#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
783#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
784#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
785#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
786#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
787#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
788#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
789#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
790#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
791#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
792#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
793#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
794#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
795#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
796#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
797#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
798#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
799#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
800#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
801#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
802#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
803#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
804#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
805#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
806#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
807#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
808#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
809#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
810#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
811#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
812#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
813#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
814#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
815#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
816#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
817#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
818#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
819#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
820#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
821#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
822#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
823#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
824#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
825#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
826#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
827#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
828#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
829#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
830#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
831#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
832#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
833#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
834#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
835#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
836#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
837#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
838#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
839#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
840#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
841#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
842#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
843#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
844#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
845#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
846#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
847#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
848#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
849#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
850#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
851#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
852#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
853#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
854#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
855#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
856#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
857#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
858#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
859#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
860#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
861#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
862#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
863#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
864#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
865#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
866#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
867#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
868#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
869#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
870#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
871#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
872#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
873#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
874#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
875#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
876#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
877#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
878#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
879#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
880#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
881#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
882#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
883#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
884#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
885#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
886#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
887#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
888#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
889#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
890#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
891#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
892#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
893#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
894#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
895#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
896#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
897#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
898#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
899#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
900#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
901#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
902#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
903#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
904#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
905#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
906#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
907#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
908#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
909#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
910#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
911#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
912#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
913#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
914#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
915#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
916#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
917#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
918#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
919#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
920#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
921#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
922#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
923#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
924#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
925#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
926#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
927#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
928#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
929#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
930#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
931#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
932#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
933#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
934#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
935#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
936#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
937#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
938#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
939#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
940#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
941#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
942#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
943#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
944#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
945#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
946#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
947#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
948#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
949#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
950#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
951#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
952#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
953#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
954#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
955#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
956#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
957#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
958#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
959#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
960#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
961#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
962#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
963#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
964#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
965#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
966#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
967#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
968#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
969#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
970#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
971#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
972#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
973#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
974#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
975#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
976
977/* CAN Controller 1 Mailbox Data Registers */
978
979#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
980#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
981#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
982#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
983#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
984#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
985#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
986#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
987#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
988#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
989#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
990#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
991#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
992#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
993#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
994#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
995#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
996#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
997#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
998#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
999#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
1000#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
1001#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
1002#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
1003#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
1004#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
1005#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
1006#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
1007#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
1008#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
1009#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
1010#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
1011#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
1012#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
1013#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
1014#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
1015#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
1016#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
1017#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
1018#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
1019#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
1020#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
1021#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
1022#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
1023#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
1024#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
1025#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
1026#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
1027#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
1028#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
1029#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
1030#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
1031#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
1032#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
1033#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
1034#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
1035#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
1036#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
1037#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
1038#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
1039#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
1040#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
1041#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
1042#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
1043#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
1044#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
1045#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
1046#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
1047#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
1048#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
1049#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
1050#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
1051#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
1052#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
1053#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
1054#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
1055#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
1056#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
1057#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
1058#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
1059#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
1060#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
1061#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
1062#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
1063#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
1064#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
1065#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
1066#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
1067#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
1068#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
1069#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
1070#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
1071#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
1072#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
1073#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
1074#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
1075#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
1076#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
1077#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
1078#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
1079#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
1080#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
1081#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
1082#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
1083#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
1084#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
1085#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
1086#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
1087#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
1088#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
1089#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
1090#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
1091#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
1092#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
1093#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
1094#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
1095#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
1096#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
1097#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
1098#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
1099#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
1100#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
1101#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
1102#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
1103#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
1104#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
1105#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
1106#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
1107#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
1108#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
1109#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
1110#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
1111#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
1112#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
1113#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
1114#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
1115#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
1116#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
1117#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
1118#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
1119#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
1120#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
1121#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
1122#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
1123#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
1124#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
1125#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
1126#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
1127#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
1128#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
1129#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
1130#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
1131#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
1132#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
1133#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
1134#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
1135#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
1136#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
1137#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
1138#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
1139#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
1140#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
1141#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
1142#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
1143#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
1144#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
1145#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
1146#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
1147#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
1148#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
1149#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
1150#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
1151#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
1152#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
1153#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
1154#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
1155#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
1156#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
1157#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
1158#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
1159#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
1160#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
1161#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
1162#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
1163#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
1164#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
1165#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
1166#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
1167#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
1168#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
1169#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
1170#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
1171#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
1172#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
1173#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
1174#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
1175#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
1176#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
1177#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
1178#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
1179#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
1180#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
1181#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
1182#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
1183#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
1184#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
1185#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
1186#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
1187#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
1188#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
1189#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
1190#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
1191#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
1192#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
1193#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
1194#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
1195#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
1196#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
1197#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
1198#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
1199#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
1200#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
1201#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
1202#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
1203#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
1204#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
1205#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
1206#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
1207#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
1208#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
1209#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
1210#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
1211#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
1212#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
1213#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
1214#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
1215#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
1216#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
1217#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
1218#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
1219#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
1220#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
1221#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
1222#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
1223#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
1224#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
1225#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
1226#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
1227#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
1228#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
1229#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
1230#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
1231#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
1232#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
1233#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
1234#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
1235
1236/* ATAPI Registers */
1237
1238#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
1239#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
1240#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
1241#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
1242#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
1243#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
1244#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
1245#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
1246#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
1247#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
1248#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
1249#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
1250#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
1251#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
1252#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
1253#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
1254#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
1255#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
1256#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
1257#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
1258#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
1259#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
1260#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
1261#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
1262#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
1263#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
1264#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
1265#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
1266#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
1267#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
1268#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
1269#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
1270#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
1271#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
1272#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
1273#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
1274#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
1275#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
1276#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
1277#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
1278#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
1279#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
1280#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
1281#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
1282#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
1283#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
1284#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
1285#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
1286#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
1287#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
1288
1289/* SDH Registers */
1290
1291#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
1292#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
1293#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
1294#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
1295#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
1296#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
1297#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
1298#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
1299#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
1300#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
1301#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
1302#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
1303#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
1304#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
1305#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
1306#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
1307#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
1308#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
1309#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1310#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1311#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1312#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1313#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1314#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1315#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1316#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1317#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1318#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1319#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1320#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1321#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1322#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1323#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1324#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1325#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1326#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1327#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1328#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1329#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1330#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1331#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1332#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1333#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1334#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1335#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1336#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1337#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1338#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1339#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1340#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1341#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1342#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1343#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1344#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1345#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1346#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1347#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1348#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1349#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1350#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1351#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1352#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1353
1354/* HOST Port Registers */
1355
1356#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1357#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1358#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1359#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1360#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1361#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1362
1363/* USB Control Registers */
1364
1365#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1366#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1367#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1368#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1369#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1370#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1371#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1372#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1373#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1374#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1375#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1376#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1377#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1378#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1379#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1380#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1381#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1382#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1383#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1384#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1385#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1386#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1387#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1388#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1389#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1390#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1391
1392/* USB Packet Control Registers */
1393
1394#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1395#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1396#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1397#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1398#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1399#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1400#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1401#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1402#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1403#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1404#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1405#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1406#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1407#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1408#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1409#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1410#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1411#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1412#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1413#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1414#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1415#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1416#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1417#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1418#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1419#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1420
1421/* USB Endbfin_read_()oint FIFO Registers */
1422
1423#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1424#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1425#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1426#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1427#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1428#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1429#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1430#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1431#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1432#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1433#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1434#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1435#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1436#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1437#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1438#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1439
1440/* USB OTG Control Registers */
1441
1442#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1443#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1444#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1445#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1446#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1447#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1448
1449/* USB Phy Control Registers */
1450
1451#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1452#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1453#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1454#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1455#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1456#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1457#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1458#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1459#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1460#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1461
1462/* (APHY_CNTRL is for ADI usage only) */
1463
1464#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1465#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1466
1467/* (APHY_CALIB is for ADI usage only) */
1468
1469#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1470#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1471#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1472#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1473
1474/* (PHY_TEST is for ADI usage only) */
1475
1476#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1477#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1478#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1479#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1480#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1481#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1482
1483/* USB Endbfin_read_()oint 0 Control Registers */
1484
1485#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1486#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1487#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1488#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1489#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1490#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1491#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1492#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1493#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1494#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1495#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1496#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1497#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1498#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1499#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1500#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1501#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1502#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1503
1504/* USB Endbfin_read_()oint 1 Control Registers */
1505
1506#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1507#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1508#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1509#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1510#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1511#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1512#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1513#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1514#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1515#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1516#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1517#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1518#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1519#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1520#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1521#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1522#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1523#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1524#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1525#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1526
1527/* USB Endbfin_read_()oint 2 Control Registers */
1528
1529#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1530#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1531#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1532#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1533#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1534#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1535#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1536#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1537#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1538#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1539#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1540#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1541#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1542#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1543#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1544#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1545#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1546#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1547#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1548#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1549
1550/* USB Endbfin_read_()oint 3 Control Registers */
1551
1552#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1553#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1554#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1555#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1556#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1557#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1558#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1559#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1560#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1561#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1562#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1563#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1564#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1565#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1566#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1567#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1568#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1569#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1570#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1571#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1572
1573/* USB Endbfin_read_()oint 4 Control Registers */
1574
1575#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1576#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1577#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1578#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1579#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1580#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1581#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1582#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1583#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1584#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1585#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1586#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1587#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1588#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1589#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1590#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1591#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1592#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1593#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1594#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1595
1596/* USB Endbfin_read_()oint 5 Control Registers */
1597
1598#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1599#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1600#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1601#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1602#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1603#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1604#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1605#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1606#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1607#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1608#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1609#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1610#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1611#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1612#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1613#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1614#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1615#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1616#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1617#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1618
1619/* USB Endbfin_read_()oint 6 Control Registers */
1620
1621#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1622#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1623#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1624#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1625#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1626#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1627#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1628#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1629#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1630#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1631#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1632#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1633#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1634#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1635#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1636#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1637#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1638#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1639#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1640#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1641
1642/* USB Endbfin_read_()oint 7 Control Registers */
1643
1644#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1645#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1646#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1647#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1648#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1649#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1650#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1651#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1652#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1653#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1654#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1655#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1656#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1657#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1658#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1659#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1660#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1661#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1662#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1663#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1664#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1665#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1666#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1667#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1668
1669/* USB Channel 0 Config Registers */
1670
1671#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1672#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1673#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1674#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1675#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1676#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1677#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1678#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1679#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1680#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1681
1682/* USB Channel 1 Config Registers */
1683
1684#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1685#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1686#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1687#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1688#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1689#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1690#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1691#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1692#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1693#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1694
1695/* USB Channel 2 Config Registers */
1696
1697#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1698#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1699#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1700#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1701#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1702#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1703#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1704#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1705#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1706#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1707
1708/* USB Channel 3 Config Registers */
1709
1710#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1711#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1712#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1713#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1714#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1715#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1716#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1717#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1718#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1719#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1720
1721/* USB Channel 4 Config Registers */
1722
1723#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1724#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1725#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1726#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1727#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1728#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1729#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1730#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1731#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1732#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1733
1734/* USB Channel 5 Config Registers */
1735
1736#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1737#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1738#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1739#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1740#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1741#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1742#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1743#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1744#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1745#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1746
1747/* USB Channel 6 Config Registers */
1748
1749#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1750#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1751#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1752#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1753#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1754#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1755#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1756#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1757#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1758#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1759
1760/* USB Channel 7 Config Registers */
1761
1762#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1763#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1764#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1765#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1766#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1767#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1768#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1769#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1770#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1771#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1772
1773/* Keybfin_read_()ad Registers */
1774
1775#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1776#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1777#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1778#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1779#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1780#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1781#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1782#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1783#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1784#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1785#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1786#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1787
1788/* Pixel Combfin_read_()ositor (PIXC) Registers */
1789
1790#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1791#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1792#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1793#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1794#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1795#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1796#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1797#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1798#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1799#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1800#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1801#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1802#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1803#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1804#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1805#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1806#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1807#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1808#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1809#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1810#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1811#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1812#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1813#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1814#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1815#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1816#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1817#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1818#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1819#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1820#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1821#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1822#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1823#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1824#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1825#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1826#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1827#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1828
1829/* Handshake MDMA 0 Registers */
1830
1831#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1832#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1833#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1834#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1835#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1836#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1837#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1838#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1839#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1840#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1841#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1842#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1843#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1844#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1845
1846/* Handshake MDMA 1 Registers */
1847
1848#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1849#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1850#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1851#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1852#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1853#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1854#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1855#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1856#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1857#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1858#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1859#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1860#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1861#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1862
1863#endif /* _CDEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
deleted file mode 100644
index 57ac8cb9b1f6..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ /dev/null
@@ -1,2750 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF54x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF54X_H
32#define _CDEF_BF54X_H
33
34#include <asm/blackfin.h>
35
36#include "defBF54x_base.h"
37#include <asm/system.h>
38
39/* ************************************************************** */
40/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
41/* ************************************************************** */
42
43/* PLL Registers */
44
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1, iwr2;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 iwr2 = bfin_read32(SIC_IWR2);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62 bfin_write32(SIC_IWR2, 0);
63
64 bfin_write16(PLL_CTL, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2);
71 local_irq_restore(flags);
72}
73#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
74#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
75#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
76/* Writing to VR_CTL initiates a PLL relock sequence. */
77static __inline__ void bfin_write_VR_CTL(unsigned int val)
78{
79 unsigned long flags, iwr0, iwr1, iwr2;
80
81 if (val == bfin_read_VR_CTL())
82 return;
83
84 local_irq_save(flags);
85 /* Enable the PLL Wakeup bit in SIC IWR */
86 iwr0 = bfin_read32(SIC_IWR0);
87 iwr1 = bfin_read32(SIC_IWR1);
88 iwr2 = bfin_read32(SIC_IWR2);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
91 bfin_write32(SIC_IWR1, 0);
92 bfin_write32(SIC_IWR2, 0);
93
94 bfin_write16(VR_CTL, val);
95 SSYNC();
96 asm("IDLE;");
97
98 bfin_write32(SIC_IWR0, iwr0);
99 bfin_write32(SIC_IWR1, iwr1);
100 bfin_write32(SIC_IWR2, iwr2);
101 local_irq_restore(flags);
102}
103#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
104#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
105#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
106#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
107
108/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
109
110#define bfin_read_CHIPID() bfin_read32(CHIPID)
111#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
112
113/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
114
115#define bfin_read_SWRST() bfin_read16(SWRST)
116#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
117#define bfin_read_SYSCR() bfin_read16(SYSCR)
118#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
119
120/* SIC Registers */
121
122#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
123#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
124#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
125#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
126#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
127#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
128#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
129#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
130
131#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
132#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
133#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
134#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
135#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
136#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
137#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
138#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
139
140#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
141#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
142#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
143#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
144#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
145#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
146#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
147#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
148#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
149#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
150#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
151#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
152#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
153#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
154#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
155#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
156#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
157#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
158#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
159#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
160#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
161#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
162#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
163#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
164#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
165#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
166#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
167#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
168#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
169#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
170
171/* Watchdog Timer Registers */
172
173#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
174#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
175#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
176#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
177#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
178#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
179
180/* RTC Registers */
181
182#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
183#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
184#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
185#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
186#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
187#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
188#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
189#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
190#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
191#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
192#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
193#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
194
195/* UART0 Registers */
196
197#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
198#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
199#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
200#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
201#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
202#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
203#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
204#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
205#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
206#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
207#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
208#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
209#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
210#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
211#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
212#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
213#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
214#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
215#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
216#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
217#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
218#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
219#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
220#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
221
222/* SPI0 Registers */
223
224#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
225#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
226#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
227#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
228#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
229#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
230#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
231#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
232#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
233#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
234#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
235#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
236#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
237#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
238
239/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
240
241/* Two Wire Interface Registers (TWI0) */
242
243/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
244
245/* SPORT1 Registers */
246
247#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
248#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
249#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
250#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
251#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
252#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
253#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
254#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
255#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
256#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
257#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
258#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
259#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
260#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
261#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
262#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
263#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
264#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
265#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
266#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
267#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
268#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
269#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
270#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
271#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
272#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
273#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
274#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
275#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
276#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
277#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
278#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
279#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
280#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
281#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
282#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
283#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
284#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
285#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
286#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
287#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
288#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
289#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
290#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
291
292/* Asynchronous Memory Control Registers */
293
294#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
295#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
296#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
297#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
298#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
299#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
300#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL)
301#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
302#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
303#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
304#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
305#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
306#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
307#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
308
309/* DDR Memory Control Registers */
310
311#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
312#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
313#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
314#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
315#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
316#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
317#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
318#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
319#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
320#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
321#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
322#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
323#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
324#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
325#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
326#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
327
328/* DDR BankRead and Write Count Registers */
329
330#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
331#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
332#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
333#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
334#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
335#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
336#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
337#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
338#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
339#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
340#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
341#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
342#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
343#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
344#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
345#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
346#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
347#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
348#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
349#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
350#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
351#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
352#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
353#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
354#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
355#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
356#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
357#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
358#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
359#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
360#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
361#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
362#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
363#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
364#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
365#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
366#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
367#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
368#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
369#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
370#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
371#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
372#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
373#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
374#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
375#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
376#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
377#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
378#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
379#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
380
381/* DMAC0 Registers */
382
383#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
384#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
385#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
386#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
387
388/* DMA Channel 0 Registers */
389
390#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
391#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
392#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
393#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
394#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
395#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
396#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
397#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
398#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
399#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
400#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
401#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
402#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
403#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
404#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
405#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
406#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
407#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
408#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
409#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
410#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
411#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
412#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
413#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
414#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
415#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
416
417/* DMA Channel 1 Registers */
418
419#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
420#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
421#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
422#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
423#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
424#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
425#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
426#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
427#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
428#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
429#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
430#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
431#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
432#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
433#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
434#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
435#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
436#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
437#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
438#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
439#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
440#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
441#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
442#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
443#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
444#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
445
446/* DMA Channel 2 Registers */
447
448#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
449#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
450#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
451#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
452#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
453#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
454#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
455#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
456#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
457#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
458#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
459#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
460#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
461#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
462#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
463#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
464#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
465#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
466#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
467#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
468#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
469#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
470#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
471#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
472#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
473#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
474
475/* DMA Channel 3 Registers */
476
477#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
478#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
479#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
480#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
481#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
482#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
483#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
484#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
485#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
486#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
487#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
488#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
489#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
490#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
491#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
492#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
493#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
494#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
495#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
496#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
497#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
498#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
499#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
500#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
501#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
502#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
503
504/* DMA Channel 4 Registers */
505
506#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
507#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
508#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
509#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
510#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
511#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
512#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
513#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
514#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
515#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
516#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
517#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
518#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
519#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
520#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
521#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
522#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
523#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
524#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
525#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
526#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
527#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
528#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
529#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
530#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
531#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
532
533/* DMA Channel 5 Registers */
534
535#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
536#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
537#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
538#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
539#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
540#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
541#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
542#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
543#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
544#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
545#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
546#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
547#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
548#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
549#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
550#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
551#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
552#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
553#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
554#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
555#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
556#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
557#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
558#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
559#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
560#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
561
562/* DMA Channel 6 Registers */
563
564#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
565#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
566#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
567#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
568#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
569#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
570#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
571#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
572#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
573#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
574#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
575#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
576#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
577#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
578#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
579#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
580#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
581#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
582#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
583#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
584#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
585#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
586#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
587#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
588#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
589#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
590
591/* DMA Channel 7 Registers */
592
593#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
594#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
595#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
596#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
597#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
598#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
599#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
600#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
601#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
602#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
603#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
604#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
605#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
606#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
607#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
608#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
609#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
610#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
611#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
612#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
613#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
614#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
615#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
616#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
617#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
618#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
619
620/* DMA Channel 8 Registers */
621
622#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
623#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
624#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
625#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
626#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
627#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
628#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
629#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
630#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
631#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
632#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
633#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
634#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
635#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
636#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
637#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
638#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
639#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
640#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
641#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
642#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
643#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
644#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
645#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
646#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
647#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
648
649/* DMA Channel 9 Registers */
650
651#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
652#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
653#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
654#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
655#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
656#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
657#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
658#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
659#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
660#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
661#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
662#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
663#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
664#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
665#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
666#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
667#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
668#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
669#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
670#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
671#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
672#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
673#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
674#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
675#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
676#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
677
678/* DMA Channel 10 Registers */
679
680#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
681#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
682#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
683#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
684#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
685#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
686#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
687#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
688#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
689#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
690#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
691#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
692#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
693#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
694#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
695#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
696#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
697#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
698#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
699#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
700#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
701#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
702#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
703#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
704#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
705#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
706
707/* DMA Channel 11 Registers */
708
709#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
710#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
711#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
712#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
713#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
714#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
715#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
716#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
717#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
718#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
719#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
720#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
721#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
722#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
723#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
724#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
725#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
726#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
727#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
728#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
729#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
730#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
731#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
732#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
733#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
734#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
735
736/* MDMA Stream 0 Registers */
737
738#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
739#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
740#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
741#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
742#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
743#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
744#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
745#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
746#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
747#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
748#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
749#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
750#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
751#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
752#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
753#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
754#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
755#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
756#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
757#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
758#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
759#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
760#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
761#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
762#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
763#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
764#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
765#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
766#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
767#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
768#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
769#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
770#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
771#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
772#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
773#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
774#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
775#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
776#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
777#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
778#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
779#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
780#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
781#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
782#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
783#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
784#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
785#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
786#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
787#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
788#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
789#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
790
791/* MDMA Stream 1 Registers */
792
793#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
794#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
795#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
796#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
797#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
798#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
799#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
800#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
801#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
802#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
803#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
804#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
805#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
806#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
807#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
808#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
809#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
810#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
811#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
812#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
813#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
814#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
815#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
816#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
817#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
818#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
819#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
820#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
821#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
822#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
823#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
824#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
825#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
826#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
827#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
828#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
829#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
830#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
831#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
832#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
833#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
834#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
835#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
836#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
837#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
838#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
839#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
840#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
841#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
842#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
843#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
844#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
845
846/* EPPI1 Registers */
847
848#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
849#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
850#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
851#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
852#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
853#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
854#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
855#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
856#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
857#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
858#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
859#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
860#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
861#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
862#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
863#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
864#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
865#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
866#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
867#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
868#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
869#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
870#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
871#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
872#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
873#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
874#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
875#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
876
877/* Port Interrubfin_read_()t 0 Registers (32-bit) */
878
879#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
880#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
881#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
882#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
883#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
884#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
885#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
886#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
887#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
888#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
889#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
890#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
891#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
892#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
893#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
894#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
895#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
896#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
897#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
898#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
899
900/* Port Interrubfin_read_()t 1 Registers (32-bit) */
901
902#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
903#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
904#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
905#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
906#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
907#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
908#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
909#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
910#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
911#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
912#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
913#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
914#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
915#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
916#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
917#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
918#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
919#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
920#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
921#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
922
923/* Port Interrubfin_read_()t 2 Registers (32-bit) */
924
925#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
926#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
927#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
928#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
929#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
930#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
931#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
932#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
933#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
934#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
935#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
936#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
937#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
938#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
939#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
940#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
941#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
942#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
943#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
944#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
945
946/* Port Interrubfin_read_()t 3 Registers (32-bit) */
947
948#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
949#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
950#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
951#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
952#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
953#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
954#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
955#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
956#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
957#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
958#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
959#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
960#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
961#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
962#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
963#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
964#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
965#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
966#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
967#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
968
969/* Port A Registers */
970
971#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
972#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
973#define bfin_read_PORTA() bfin_read16(PORTA)
974#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
975#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
976#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
977#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
978#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
979#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
980#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
981#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
982#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
983#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
984#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
985#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
986#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
987
988/* Port B Registers */
989
990#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
991#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
992#define bfin_read_PORTB() bfin_read16(PORTB)
993#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
994#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
995#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
996#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
997#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
998#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
999#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
1000#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
1001#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
1002#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
1003#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
1004#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
1005#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
1006
1007/* Port C Registers */
1008
1009#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
1010#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
1011#define bfin_read_PORTC() bfin_read16(PORTC)
1012#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
1013#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
1014#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
1015#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
1016#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
1017#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
1018#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
1019#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
1020#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
1021#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
1022#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
1023#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
1024#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
1025
1026/* Port D Registers */
1027
1028#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
1029#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
1030#define bfin_read_PORTD() bfin_read16(PORTD)
1031#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
1032#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
1033#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
1034#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
1035#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
1036#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
1037#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
1038#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
1039#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
1040#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
1041#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
1042#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
1043#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
1044
1045/* Port E Registers */
1046
1047#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
1048#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
1049#define bfin_read_PORTE() bfin_read16(PORTE)
1050#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
1051#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
1052#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
1053#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
1054#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
1055#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
1056#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
1057#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
1058#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
1059#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
1060#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
1061#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
1062#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
1063
1064/* Port F Registers */
1065
1066#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1067#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
1068#define bfin_read_PORTF() bfin_read16(PORTF)
1069#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
1070#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
1071#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
1072#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
1073#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
1074#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
1075#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
1076#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
1077#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
1078#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
1079#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
1080#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
1081#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
1082
1083/* Port G Registers */
1084
1085#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1086#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1087#define bfin_read_PORTG() bfin_read16(PORTG)
1088#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
1089#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
1090#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
1091#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
1092#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
1093#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
1094#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
1095#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
1096#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
1097#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
1098#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
1099#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
1100#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
1101
1102/* Port H Registers */
1103
1104#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1105#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1106#define bfin_read_PORTH() bfin_read16(PORTH)
1107#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
1108#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
1109#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
1110#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
1111#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
1112#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
1113#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
1114#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
1115#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
1116#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
1117#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
1118#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
1119#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
1120
1121/* Port I Registers */
1122
1123#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
1124#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
1125#define bfin_read_PORTI() bfin_read16(PORTI)
1126#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
1127#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
1128#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
1129#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
1130#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
1131#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
1132#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
1133#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
1134#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
1135#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
1136#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
1137#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
1138#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
1139
1140/* Port J Registers */
1141
1142#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
1143#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
1144#define bfin_read_PORTJ() bfin_read16(PORTJ)
1145#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
1146#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
1147#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
1148#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
1149#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
1150#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
1151#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
1152#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
1153#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
1154#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
1155#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
1156#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
1157#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
1158
1159/* PWM Timer Registers */
1160
1161#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
1162#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
1163#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
1164#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
1165#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
1166#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
1167#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
1168#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
1169#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
1170#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
1171#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
1172#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
1173#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
1174#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
1175#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
1176#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
1177#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
1178#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
1179#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
1180#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
1181#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
1182#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
1183#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
1184#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
1185#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
1186#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
1187#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
1188#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
1189#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
1190#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
1191#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
1192#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
1193#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
1194#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
1195#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
1196#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
1197#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
1198#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
1199#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
1200#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
1201#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
1202#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
1203#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
1204#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
1205#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
1206#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
1207#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
1208#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
1209#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
1210#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
1211#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
1212#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
1213#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
1214#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
1215#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
1216#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
1217#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
1218#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
1219#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
1220#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
1221#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
1222#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
1223#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
1224#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
1225
1226/* Timer Groubfin_read_() of 8 */
1227
1228#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
1229#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
1230#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
1231#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
1232#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
1233#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
1234
1235/* DMAC1 Registers */
1236
1237#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
1238#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
1239#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
1240#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
1241
1242/* DMA Channel 12 Registers */
1243
1244#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
1245#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
1246#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
1247#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
1248#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
1249#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
1250#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
1251#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
1252#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
1253#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
1254#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
1255#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
1256#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
1257#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
1258#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
1259#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
1260#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
1261#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
1262#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
1263#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
1264#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
1265#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
1266#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
1267#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
1268#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
1269#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
1270
1271/* DMA Channel 13 Registers */
1272
1273#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
1274#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
1275#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
1276#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
1277#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
1278#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
1279#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
1280#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
1281#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
1282#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
1283#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
1284#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
1285#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
1286#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
1287#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
1288#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
1289#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
1290#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
1291#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
1292#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
1293#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
1294#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
1295#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
1296#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
1297#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
1298#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
1299
1300/* DMA Channel 14 Registers */
1301
1302#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
1303#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
1304#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
1305#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
1306#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
1307#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
1308#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
1309#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
1310#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
1311#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
1312#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
1313#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
1314#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
1315#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
1316#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
1317#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
1318#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
1319#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
1320#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
1321#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
1322#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
1323#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
1324#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
1325#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
1326#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
1327#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
1328
1329/* DMA Channel 15 Registers */
1330
1331#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
1332#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
1333#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
1334#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
1335#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
1336#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
1337#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
1338#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
1339#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
1340#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
1341#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
1342#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
1343#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
1344#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
1345#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
1346#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
1347#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
1348#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
1349#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
1350#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
1351#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
1352#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
1353#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
1354#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
1355#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
1356#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
1357
1358/* DMA Channel 16 Registers */
1359
1360#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
1361#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
1362#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
1363#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
1364#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
1365#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
1366#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
1367#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
1368#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
1369#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
1370#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
1371#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
1372#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
1373#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
1374#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
1375#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
1376#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
1377#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
1378#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
1379#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
1380#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
1381#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
1382#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
1383#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
1384#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
1385#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
1386
1387/* DMA Channel 17 Registers */
1388
1389#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
1390#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
1391#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
1392#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
1393#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
1394#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
1395#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
1396#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
1397#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
1398#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
1399#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
1400#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
1401#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
1402#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
1403#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
1404#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
1405#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
1406#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
1407#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
1408#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
1409#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
1410#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
1411#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
1412#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
1413#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
1414#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
1415
1416/* DMA Channel 18 Registers */
1417
1418#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
1419#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
1420#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
1421#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
1422#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
1423#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
1424#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
1425#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
1426#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
1427#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
1428#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
1429#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
1430#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
1431#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
1432#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
1433#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
1434#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
1435#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
1436#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
1437#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
1438#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
1439#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
1440#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
1441#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
1442#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
1443#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
1444
1445/* DMA Channel 19 Registers */
1446
1447#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
1448#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
1449#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
1450#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
1451#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
1452#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
1453#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
1454#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
1455#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
1456#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
1457#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
1458#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
1459#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
1460#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
1461#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
1462#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
1463#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
1464#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
1465#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
1466#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
1467#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
1468#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
1469#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
1470#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
1471#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
1472#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
1473
1474/* DMA Channel 20 Registers */
1475
1476#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
1477#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
1478#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
1479#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
1480#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
1481#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
1482#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
1483#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
1484#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
1485#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
1486#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
1487#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
1488#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
1489#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
1490#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
1491#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
1492#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
1493#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
1494#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
1495#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
1496#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
1497#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
1498#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
1499#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
1500#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
1501#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
1502
1503/* DMA Channel 21 Registers */
1504
1505#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
1506#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
1507#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
1508#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
1509#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
1510#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
1511#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
1512#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
1513#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
1514#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
1515#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
1516#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
1517#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
1518#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
1519#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
1520#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
1521#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
1522#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
1523#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
1524#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
1525#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
1526#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
1527#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
1528#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
1529#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
1530#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
1531
1532/* DMA Channel 22 Registers */
1533
1534#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
1535#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
1536#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
1537#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
1538#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
1539#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
1540#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
1541#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
1542#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
1543#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
1544#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
1545#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
1546#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
1547#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
1548#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
1549#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
1550#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
1551#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
1552#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
1553#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
1554#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
1555#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
1556#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
1557#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
1558#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
1559#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
1560
1561/* DMA Channel 23 Registers */
1562
1563#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
1564#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
1565#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
1566#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
1567#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
1568#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
1569#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
1570#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
1571#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
1572#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
1573#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
1574#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
1575#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
1576#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
1577#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
1578#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
1579#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
1580#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
1581#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
1582#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
1583#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
1584#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
1585#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
1586#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
1587#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
1588#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
1589
1590/* MDMA Stream 2 Registers */
1591
1592#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
1593#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
1594#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
1595#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
1596#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
1597#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1598#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
1599#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1600#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
1601#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
1602#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
1603#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1604#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
1605#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
1606#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
1607#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
1608#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
1609#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
1610#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1611#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1612#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
1613#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
1614#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
1615#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
1616#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
1617#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1618#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
1619#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
1620#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
1621#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
1622#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
1623#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1624#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
1625#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1626#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
1627#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
1628#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
1629#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1630#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
1631#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
1632#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
1633#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
1634#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
1635#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
1636#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
1637#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1638#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
1639#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
1640#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
1641#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
1642#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
1643#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
1644
1645/* MDMA Stream 3 Registers */
1646
1647#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
1648#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
1649#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
1650#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
1651#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
1652#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1653#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
1654#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1655#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
1656#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
1657#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
1658#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1659#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
1660#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
1661#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
1662#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
1663#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
1664#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
1665#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
1666#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1667#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
1668#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
1669#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
1670#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
1671#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
1672#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1673#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
1674#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
1675#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
1676#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
1677#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
1678#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1679#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
1680#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1681#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
1682#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
1683#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
1684#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1685#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
1686#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
1687#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
1688#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
1689#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
1690#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
1691#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
1692#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1693#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
1694#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
1695#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
1696#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
1697#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
1698#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
1699
1700/* UART1 Registers */
1701
1702#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
1703#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
1704#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
1705#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
1706#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
1707#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1708#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
1709#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1710#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
1711#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1712#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
1713#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1714#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
1715#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1716#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
1717#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1718#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
1719#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
1720#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
1721#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
1722#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
1723#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
1724#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
1725#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
1726
1727/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
1728
1729/* SPI1 Registers */
1730
1731#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
1732#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
1733#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
1734#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
1735#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
1736#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
1737#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
1738#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
1739#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
1740#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
1741#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
1742#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
1743#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
1744#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
1745
1746/* SPORT2 Registers */
1747
1748#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
1749#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
1750#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
1751#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
1752#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
1753#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
1754#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
1755#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
1756#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
1757#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
1758#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
1759#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
1760#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
1761#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
1762#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
1763#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
1764#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
1765#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
1766#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
1767#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
1768#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
1769#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
1770#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
1771#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
1772#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
1773#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
1774#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
1775#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
1776#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
1777#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
1778#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
1779#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
1780#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
1781#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
1782#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
1783#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
1784#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
1785#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
1786#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
1787#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
1788#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
1789#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
1790#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
1791#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
1792
1793/* SPORT3 Registers */
1794
1795#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
1796#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
1797#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
1798#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
1799#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
1800#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
1801#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
1802#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
1803#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
1804#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
1805#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
1806#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
1807#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
1808#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
1809#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
1810#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
1811#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
1812#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
1813#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
1814#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
1815#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
1816#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
1817#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
1818#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
1819#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
1820#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
1821#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
1822#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
1823#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
1824#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
1825#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
1826#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
1827#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
1828#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
1829#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
1830#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
1831#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
1832#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
1833#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
1834#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
1835#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
1836#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
1837#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
1838#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
1839
1840/* EPPI2 Registers */
1841
1842#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
1843#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
1844#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
1845#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
1846#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
1847#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
1848#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
1849#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
1850#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
1851#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
1852#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
1853#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
1854#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
1855#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
1856#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
1857#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
1858#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
1859#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
1860#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
1861#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
1862#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
1863#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
1864#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
1865#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
1866#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
1867#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
1868#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
1869#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
1870
1871/* CAN Controller 0 Config 1 Registers */
1872
1873#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
1874#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
1875#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
1876#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
1877#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
1878#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
1879#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
1880#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
1881#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
1882#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
1883#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
1884#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
1885#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
1886#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
1887#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
1888#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
1889#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
1890#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
1891#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
1892#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
1893#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
1894#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
1895#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
1896#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
1897#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
1898#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
1899
1900/* CAN Controller 0 Config 2 Registers */
1901
1902#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
1903#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
1904#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
1905#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
1906#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
1907#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
1908#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
1909#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
1910#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
1911#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
1912#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
1913#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
1914#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
1915#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
1916#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
1917#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
1918#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
1919#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
1920#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
1921#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
1922#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
1923#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
1924#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
1925#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
1926#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
1927#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
1928
1929/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
1930
1931#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
1932#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
1933#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
1934#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
1935#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
1936#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
1937#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
1938#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
1939#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
1940#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
1941#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
1942#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
1943#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
1944#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
1945#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
1946#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
1947#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
1948#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
1949#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
1950#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
1951#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
1952#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
1953#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
1954#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
1955#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
1956#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
1957#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
1958#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
1959#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
1960#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
1961#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
1962#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
1963
1964/* CAN Controller 0 Accebfin_read_()tance Registers */
1965
1966#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
1967#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
1968#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
1969#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
1970#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
1971#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
1972#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
1973#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
1974#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
1975#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
1976#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
1977#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
1978#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
1979#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
1980#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
1981#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
1982#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
1983#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
1984#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
1985#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
1986#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
1987#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
1988#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
1989#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
1990#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
1991#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
1992#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
1993#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
1994#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
1995#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
1996#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
1997#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
1998#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
1999#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
2000#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
2001#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
2002#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
2003#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
2004#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
2005#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
2006#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
2007#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
2008#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
2009#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
2010#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
2011#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
2012#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
2013#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
2014#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
2015#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
2016#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
2017#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
2018#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
2019#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
2020#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
2021#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
2022#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
2023#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
2024#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
2025#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
2026#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
2027#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
2028#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
2029#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
2030
2031/* CAN Controller 0 Accebfin_read_()tance Registers */
2032
2033#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
2034#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
2035#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
2036#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
2037#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
2038#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
2039#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
2040#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
2041#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
2042#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
2043#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
2044#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
2045#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
2046#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
2047#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
2048#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
2049#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
2050#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
2051#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
2052#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
2053#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
2054#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
2055#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
2056#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
2057#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
2058#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
2059#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
2060#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
2061#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
2062#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
2063#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
2064#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
2065#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
2066#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
2067#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
2068#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
2069#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
2070#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
2071#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
2072#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
2073#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
2074#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
2075#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
2076#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
2077#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
2078#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
2079#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
2080#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
2081#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
2082#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
2083#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
2084#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
2085#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
2086#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
2087#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
2088#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
2089#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
2090#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
2091#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
2092#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
2093#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
2094#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
2095#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
2096#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
2097
2098/* CAN Controller 0 Mailbox Data Registers */
2099
2100#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
2101#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
2102#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
2103#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
2104#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
2105#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
2106#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
2107#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
2108#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
2109#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
2110#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
2111#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
2112#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
2113#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
2114#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
2115#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
2116#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
2117#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
2118#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
2119#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
2120#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
2121#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
2122#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
2123#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
2124#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
2125#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
2126#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
2127#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
2128#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
2129#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
2130#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
2131#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
2132#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
2133#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
2134#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
2135#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
2136#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
2137#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
2138#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
2139#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
2140#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
2141#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
2142#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
2143#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
2144#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
2145#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
2146#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
2147#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
2148#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
2149#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
2150#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
2151#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
2152#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
2153#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
2154#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
2155#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
2156#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
2157#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
2158#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
2159#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
2160#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
2161#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
2162#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
2163#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
2164#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
2165#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
2166#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
2167#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
2168#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
2169#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
2170#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
2171#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
2172#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
2173#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
2174#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
2175#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
2176#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
2177#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
2178#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
2179#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
2180#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
2181#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
2182#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
2183#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
2184#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
2185#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
2186#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
2187#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
2188#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
2189#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
2190#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
2191#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
2192#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
2193#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
2194#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
2195#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
2196#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
2197#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
2198#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
2199#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
2200#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
2201#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
2202#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
2203#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
2204#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
2205#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
2206#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
2207#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
2208#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
2209#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
2210#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
2211#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
2212#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
2213#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
2214#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
2215#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
2216#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
2217#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
2218#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
2219#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
2220#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
2221#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
2222#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
2223#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
2224#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
2225#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
2226#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
2227#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
2228#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
2229#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
2230#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
2231#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
2232#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
2233#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
2234#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
2235#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
2236#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
2237#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
2238#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
2239#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
2240#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
2241#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
2242#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
2243#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
2244#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
2245#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
2246#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
2247#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
2248#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
2249#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
2250#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
2251#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
2252#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
2253#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
2254#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
2255#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
2256#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
2257#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
2258#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
2259#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
2260#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
2261#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
2262#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
2263#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
2264#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
2265#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
2266#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
2267#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
2268#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
2269#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
2270#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
2271#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
2272#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
2273#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
2274#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
2275#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
2276#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
2277#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
2278#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
2279#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
2280#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
2281#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
2282#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
2283#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
2284#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
2285#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
2286#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
2287#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
2288#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
2289#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
2290#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
2291#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
2292#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
2293#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
2294#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
2295#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
2296#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
2297#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
2298#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
2299#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
2300#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
2301#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
2302#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
2303#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
2304#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
2305#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
2306#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
2307#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
2308#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
2309#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
2310#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
2311#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
2312#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
2313#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
2314#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
2315#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
2316#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
2317#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
2318#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
2319#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
2320#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
2321#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
2322#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
2323#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
2324#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
2325#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
2326#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
2327#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
2328#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
2329#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
2330#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
2331#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
2332#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
2333#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
2334#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
2335#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
2336#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
2337#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
2338#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
2339#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
2340#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
2341#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
2342#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
2343#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
2344#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
2345#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
2346#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
2347#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
2348#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
2349#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
2350#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
2351#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
2352#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
2353#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
2354#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
2355#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
2356
2357/* CAN Controller 0 Mailbox Data Registers */
2358
2359#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
2360#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
2361#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
2362#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
2363#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
2364#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
2365#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
2366#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
2367#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
2368#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
2369#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
2370#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
2371#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
2372#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
2373#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
2374#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
2375#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
2376#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
2377#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
2378#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
2379#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
2380#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
2381#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
2382#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
2383#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
2384#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
2385#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
2386#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
2387#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
2388#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
2389#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
2390#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
2391#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
2392#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
2393#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
2394#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
2395#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
2396#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
2397#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
2398#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
2399#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
2400#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
2401#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
2402#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
2403#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
2404#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
2405#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
2406#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
2407#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
2408#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
2409#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
2410#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
2411#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
2412#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
2413#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
2414#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
2415#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
2416#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
2417#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
2418#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
2419#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
2420#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
2421#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
2422#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
2423#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
2424#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
2425#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
2426#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
2427#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
2428#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
2429#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
2430#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
2431#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
2432#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
2433#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
2434#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
2435#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
2436#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
2437#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
2438#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
2439#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
2440#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
2441#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
2442#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
2443#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
2444#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
2445#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
2446#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
2447#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
2448#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
2449#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
2450#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
2451#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
2452#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
2453#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
2454#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
2455#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
2456#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
2457#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
2458#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
2459#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
2460#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
2461#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
2462#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
2463#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
2464#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
2465#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
2466#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
2467#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
2468#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
2469#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
2470#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
2471#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
2472#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
2473#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
2474#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
2475#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
2476#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
2477#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
2478#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
2479#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
2480#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
2481#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
2482#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
2483#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
2484#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
2485#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
2486#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
2487#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
2488#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
2489#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
2490#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
2491#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
2492#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
2493#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
2494#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
2495#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
2496#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
2497#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
2498#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
2499#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
2500#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
2501#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
2502#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
2503#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
2504#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
2505#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
2506#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
2507#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
2508#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
2509#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
2510#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
2511#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
2512#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
2513#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
2514#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
2515#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
2516#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
2517#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
2518#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
2519#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
2520#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
2521#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
2522#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
2523#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
2524#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
2525#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
2526#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
2527#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
2528#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
2529#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
2530#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
2531#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
2532#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
2533#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
2534#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
2535#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
2536#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
2537#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
2538#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
2539#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
2540#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
2541#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
2542#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
2543#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
2544#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
2545#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
2546#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
2547#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
2548#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
2549#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
2550#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
2551#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
2552#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
2553#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
2554#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
2555#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
2556#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
2557#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
2558#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
2559#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
2560#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
2561#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
2562#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
2563#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
2564#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
2565#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
2566#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
2567#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
2568#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
2569#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
2570#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
2571#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
2572#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
2573#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
2574#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
2575#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
2576#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
2577#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
2578#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
2579#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
2580#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
2581#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
2582#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
2583#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
2584#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
2585#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
2586#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
2587#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
2588#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
2589#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
2590#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
2591#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
2592#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
2593#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
2594#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
2595#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
2596#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
2597#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
2598#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
2599#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
2600#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
2601#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
2602#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
2603#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
2604#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
2605#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
2606#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
2607#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
2608#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
2609#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
2610#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
2611#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
2612#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
2613#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
2614#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
2615
2616/* UART3 Registers */
2617
2618#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
2619#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
2620#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
2621#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
2622#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
2623#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
2624#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
2625#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
2626#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
2627#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
2628#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
2629#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
2630#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
2631#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
2632#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
2633#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
2634#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
2635#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
2636#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
2637#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
2638#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
2639#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
2640#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
2641#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
2642
2643/* NFC Registers */
2644
2645#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
2646#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
2647#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
2648#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
2649#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
2650#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
2651#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
2652#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
2653#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
2654#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
2655#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
2656#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
2657#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
2658#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
2659#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
2660#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
2661#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
2662#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
2663#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
2664#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
2665#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
2666#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
2667#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
2668#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
2669#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
2670#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
2671#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
2672#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
2673#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
2674#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
2675#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
2676#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
2677
2678/* Counter Registers */
2679
2680#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
2681#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
2682#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
2683#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
2684#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
2685#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
2686#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
2687#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
2688#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
2689#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
2690#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
2691#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
2692#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
2693#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
2694#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
2695#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
2696
2697/* OTP/FUSE Registers */
2698
2699#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
2700#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
2701#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
2702#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
2703#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
2704#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
2705#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
2706#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
2707
2708/* Security Registers */
2709
2710#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
2711#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
2712#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
2713#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
2714#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
2715#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
2716
2717/* DMA Peribfin_read_()heral Mux Register */
2718
2719#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
2720#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
2721
2722/* OTP Read/Write Data Buffer Registers */
2723
2724#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
2725#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
2726#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
2727#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
2728#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
2729#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
2730#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
2731#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
2732
2733/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
2734
2735/* legacy definitions */
2736#define bfin_read_EBIU_AMCBCTL0 bfin_read_EBIU_AMBCTL0
2737#define bfin_write_EBIU_AMCBCTL0 bfin_write_EBIU_AMBCTL0
2738#define bfin_read_EBIU_AMCBCTL1 bfin_read_EBIU_AMBCTL1
2739#define bfin_write_EBIU_AMCBCTL1 bfin_write_EBIU_AMBCTL1
2740#define bfin_read_PINT0_IRQ bfin_read_PINT0_REQUEST
2741#define bfin_write_PINT0_IRQ bfin_write_PINT0_REQUEST
2742#define bfin_read_PINT1_IRQ bfin_read_PINT1_REQUEST
2743#define bfin_write_PINT1_IRQ bfin_write_PINT1_REQUEST
2744#define bfin_read_PINT2_IRQ bfin_read_PINT2_REQUEST
2745#define bfin_write_PINT2_IRQ bfin_write_PINT2_REQUEST
2746#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
2747#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
2748
2749#endif /* _CDEF_BF54X_H */
2750
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
deleted file mode 100644
index a7c809f29ede..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ /dev/null
@@ -1,925 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF542.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF542_H
32#define _DEF_BF542_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
43
44/* ATAPI Registers */
45
46#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
47#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
48#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
49#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
50#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
51#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
52#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
53#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
54#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
55#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
56#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
57#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
58#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
59#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
60#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
61#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
62#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
63#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
64#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
65#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
66#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
67#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
68#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
69#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
70#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
71
72/* SDH Registers */
73
74#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
75#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
76#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
77#define SDH_COMMAND 0xffc0390c /* SDH Command */
78#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
79#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
80#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
81#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
82#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
83#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
84#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
85#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
86#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
87#define SDH_STATUS 0xffc03934 /* SDH Status */
88#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
89#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
90#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
91#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
92#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
93#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
94#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
95#define SDH_CFG 0xffc039c8 /* SDH Configuration */
96#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
97#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
98#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
99#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
100#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
101#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
102#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
103#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
104#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
105
106/* USB Control Registers */
107
108#define USB_FADDR 0xffc03c00 /* Function address register */
109#define USB_POWER 0xffc03c04 /* Power management register */
110#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
111#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
112#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
113#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
114#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
115#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
116#define USB_FRAME 0xffc03c20 /* USB frame number */
117#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
118#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
119#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
120#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
121
122/* USB Packet Control Registers */
123
124#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
125#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
126#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
127#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
128#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
129#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
130#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
131#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
132#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
133#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
134#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
135#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
136#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
137
138/* USB Endpoint FIFO Registers */
139
140#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
141#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
142#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
143#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
144#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
145#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
146#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
147#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
148
149/* USB OTG Control Registers */
150
151#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
152#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
153#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
154
155/* USB Phy Control Registers */
156
157#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
158#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
159#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
160#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
161#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
162
163/* (APHY_CNTRL is for ADI usage only) */
164
165#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
166
167/* (APHY_CALIB is for ADI usage only) */
168
169#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
170#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
171
172/* (PHY_TEST is for ADI usage only) */
173
174#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
175#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
176#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
177
178/* USB Endpoint 0 Control Registers */
179
180#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
181#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
182#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
183#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
184#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
185#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
186#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
187#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
188#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
189
190/* USB Endpoint 1 Control Registers */
191
192#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
193#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
194#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
195#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
196#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
197#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
198#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
199#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
200#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
201#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
202
203/* USB Endpoint 2 Control Registers */
204
205#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
206#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
207#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
208#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
209#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
210#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
211#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
212#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
213#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
214#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
215
216/* USB Endpoint 3 Control Registers */
217
218#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
219#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
220#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
221#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
222#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
223#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
224#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
225#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
226#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
227#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
228
229/* USB Endpoint 4 Control Registers */
230
231#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
232#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
233#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
234#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
235#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
236#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
237#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
238#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
239#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
240#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
241
242/* USB Endpoint 5 Control Registers */
243
244#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
245#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
246#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
247#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
248#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
249#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
250#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
251#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
252#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
253#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
254
255/* USB Endpoint 6 Control Registers */
256
257#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
258#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
259#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
260#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
261#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
262#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
263#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
264#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
265#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
266#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
267
268/* USB Endpoint 7 Control Registers */
269
270#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
271#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
272#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
273#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
274#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
275#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
276#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
277#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
278#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
279#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
280#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
281#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
282
283/* USB Channel 0 Config Registers */
284
285#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
286#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
287#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
288#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
289#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
290
291/* USB Channel 1 Config Registers */
292
293#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
294#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
295#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
296#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
297#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
298
299/* USB Channel 2 Config Registers */
300
301#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
302#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
303#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
304#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
305#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
306
307/* USB Channel 3 Config Registers */
308
309#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
310#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
311#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
312#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
313#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
314
315/* USB Channel 4 Config Registers */
316
317#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
318#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
319#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
320#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
321#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
322
323/* USB Channel 5 Config Registers */
324
325#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
326#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
327#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
328#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
329#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
330
331/* USB Channel 6 Config Registers */
332
333#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
334#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
335#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
336#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
337#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
338
339/* USB Channel 7 Config Registers */
340
341#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
342#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
343#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
344#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
345#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
346
347/* Keypad Registers */
348
349#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
350#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
351#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
352#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
353#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
354#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
355
356
357/* ********************************************************** */
358/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
359/* and MULTI BIT READ MACROS */
360/* ********************************************************** */
361
362/* Bit masks for KPAD_CTL */
363
364#define KPAD_EN 0x1 /* Keypad Enable */
365#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
366#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
367#define KPAD_COLEN 0xe000 /* Column Enable Width */
368
369/* Bit masks for KPAD_PRESCALE */
370
371#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
372
373/* Bit masks for KPAD_MSEL */
374
375#define DBON_SCALE 0xff /* Debounce Scale Value */
376#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
377
378/* Bit masks for KPAD_ROWCOL */
379
380#define KPAD_ROW 0xff /* Rows Pressed */
381#define KPAD_COL 0xff00 /* Columns Pressed */
382
383/* Bit masks for KPAD_STAT */
384
385#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
386#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
387#define KPAD_PRESSED 0x8 /* Key press current status */
388
389/* Bit masks for KPAD_SOFTEVAL */
390
391#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
392
393/* Bit masks for SDH_COMMAND */
394
395#define CMD_IDX 0x3f /* Command Index */
396#define CMD_RSP 0x40 /* Response */
397#define CMD_L_RSP 0x80 /* Long Response */
398#define CMD_INT_E 0x100 /* Command Interrupt */
399#define CMD_PEND_E 0x200 /* Command Pending */
400#define CMD_E 0x400 /* Command Enable */
401
402/* Bit masks for SDH_PWR_CTL */
403
404#define PWR_ON 0x3 /* Power On */
405#if 0
406#define TBD 0x3c /* TBD */
407#endif
408#define SD_CMD_OD 0x40 /* Open Drain Output */
409#define ROD_CTL 0x80 /* Rod Control */
410
411/* Bit masks for SDH_CLK_CTL */
412
413#define CLKDIV 0xff /* MC_CLK Divisor */
414#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
415#define PWR_SV_E 0x200 /* Power Save Enable */
416#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
417#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
418
419/* Bit masks for SDH_RESP_CMD */
420
421#define RESP_CMD 0x3f /* Response Command */
422
423/* Bit masks for SDH_DATA_CTL */
424
425#define DTX_E 0x1 /* Data Transfer Enable */
426#define DTX_DIR 0x2 /* Data Transfer Direction */
427#define DTX_MODE 0x4 /* Data Transfer Mode */
428#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
429#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
430
431/* Bit masks for SDH_STATUS */
432
433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
435#define CMD_TIME_OUT 0x4 /* CMD Time Out */
436#define DAT_TIME_OUT 0x8 /* Data Time Out */
437#define TX_UNDERRUN 0x10 /* Transmit Underrun */
438#define RX_OVERRUN 0x20 /* Receive Overrun */
439#define CMD_RESP_END 0x40 /* CMD Response End */
440#define CMD_SENT 0x80 /* CMD Sent */
441#define DAT_END 0x100 /* Data End */
442#define START_BIT_ERR 0x200 /* Start Bit Error */
443#define DAT_BLK_END 0x400 /* Data Block End */
444#define CMD_ACT 0x800 /* CMD Active */
445#define TX_ACT 0x1000 /* Transmit Active */
446#define RX_ACT 0x2000 /* Receive Active */
447#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
448#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
449#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
450#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
451#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
452#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
453#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
454#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
455
456/* Bit masks for SDH_STATUS_CLR */
457
458#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
459#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
460#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
461#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
462#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
463#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
464#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
465#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
466#define DAT_END_STAT 0x100 /* Data End Status */
467#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
468#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
469
470/* Bit masks for SDH_MASK0 */
471
472#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
473#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
474#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
475#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
476#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
477#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
478#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
479#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
480#define DAT_END_MASK 0x100 /* Data End Mask */
481#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
482#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
483#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
484#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
485#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
486#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
487#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
488#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
489#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
490#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
491#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
492#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
493#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
494
495/* Bit masks for SDH_FIFO_CNT */
496
497#define FIFO_COUNT 0x7fff /* FIFO Count */
498
499/* Bit masks for SDH_E_STATUS */
500
501#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
502#define SD_CARD_DET 0x10 /* SD Card Detect */
503
504/* Bit masks for SDH_E_MASK */
505
506#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
507#define SCD_MSK 0x40 /* Mask Card Detect */
508
509/* Bit masks for SDH_CFG */
510
511#define CLKS_EN 0x1 /* Clocks Enable */
512#define SD4E 0x4 /* SDIO 4-Bit Enable */
513#define MWE 0x8 /* Moving Window Enable */
514#define SD_RST 0x10 /* SDMMC Reset */
515#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
516#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
517#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
518
519/* Bit masks for SDH_RD_WAIT_EN */
520
521#define RWR 0x1 /* Read Wait Request */
522
523/* Bit masks for ATAPI_CONTROL */
524
525#define PIO_START 0x1 /* Start PIO/Reg Op */
526#define MULTI_START 0x2 /* Start Multi-DMA Op */
527#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
528#define XFER_DIR 0x8 /* Transfer Direction */
529#define IORDY_EN 0x10 /* IORDY Enable */
530#define FIFO_FLUSH 0x20 /* Flush FIFOs */
531#define SOFT_RST 0x40 /* Soft Reset */
532#define DEV_RST 0x80 /* Device Reset */
533#define TFRCNT_RST 0x100 /* Trans Count Reset */
534#define END_ON_TERM 0x200 /* End/Terminate Select */
535#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
536#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
537
538/* Bit masks for ATAPI_STATUS */
539
540#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
541#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
542#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
543#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
544
545/* Bit masks for ATAPI_DEV_ADDR */
546
547#define DEV_ADDR 0x1f /* Device Address */
548
549/* Bit masks for ATAPI_INT_MASK */
550
551#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
552#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
553#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
554#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
555#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
556#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
557#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
558#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
559#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
560
561/* Bit masks for ATAPI_INT_STATUS */
562
563#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
564#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
565#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
566#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
567#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
568#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
569#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
570#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
571#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
572
573/* Bit masks for ATAPI_LINE_STATUS */
574
575#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
576#define ATAPI_DASP 0x2 /* Device dasp to host line status */
577#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
578#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
579#define ATAPI_ADDR 0x70 /* ATAPI address line status */
580#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
581#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
582#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
583#define ATAPI_DIORN 0x400 /* ATAPI read line status */
584#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
585
586/* Bit masks for ATAPI_SM_STATE */
587
588#define PIO_CSTATE 0xf /* PIO mode state machine current state */
589#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
590#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
591#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
592
593/* Bit masks for ATAPI_TERMINATE */
594
595#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
596
597/* Bit masks for ATAPI_REG_TIM_0 */
598
599#define T2_REG 0xff /* End of cycle time for register access transfers */
600#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
601
602/* Bit masks for ATAPI_PIO_TIM_0 */
603
604#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
605#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
606#define T4_REG 0xf000 /* DIOW data hold */
607
608/* Bit masks for ATAPI_PIO_TIM_1 */
609
610#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
611
612/* Bit masks for ATAPI_MULTI_TIM_0 */
613
614#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
615#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
616
617/* Bit masks for ATAPI_MULTI_TIM_1 */
618
619#define TKW 0xff /* Selects DIOW negated pulsewidth */
620#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
621
622/* Bit masks for ATAPI_MULTI_TIM_2 */
623
624#define TH 0xff /* Selects DIOW data hold */
625#define TEOC 0xff00 /* Selects end of cycle for DMA */
626
627/* Bit masks for ATAPI_ULTRA_TIM_0 */
628
629#define TACK 0xff /* Selects setup and hold times for TACK */
630#define TENV 0xff00 /* Selects envelope time */
631
632/* Bit masks for ATAPI_ULTRA_TIM_1 */
633
634#define TDVS 0xff /* Selects data valid setup time */
635#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
636
637/* Bit masks for ATAPI_ULTRA_TIM_2 */
638
639#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
640#define TMLI 0xff00 /* Selects interlock time */
641
642/* Bit masks for ATAPI_ULTRA_TIM_3 */
643
644#define TZAH 0xff /* Selects minimum delay required for output */
645#define READY_PAUSE 0xff00 /* Selects ready to pause */
646
647/* Bit masks for USB_FADDR */
648
649#define FUNCTION_ADDRESS 0x7f /* Function address */
650
651/* Bit masks for USB_POWER */
652
653#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
654#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
655#define RESUME_MODE 0x4 /* DMA Mode */
656#define RESET 0x8 /* Reset indicator */
657#define HS_MODE 0x10 /* High Speed mode indicator */
658#define HS_ENABLE 0x20 /* high Speed Enable */
659#define SOFT_CONN 0x40 /* Soft connect */
660#define ISO_UPDATE 0x80 /* Isochronous update */
661
662/* Bit masks for USB_INTRTX */
663
664#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
665#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
666#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
667#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
668#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
669#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
670#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
671#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
672
673/* Bit masks for USB_INTRRX */
674
675#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
676#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
677#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
678#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
679#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
680#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
681#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
682
683/* Bit masks for USB_INTRTXE */
684
685#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
686#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
687#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
688#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
689#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
690#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
691#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
692#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
693
694/* Bit masks for USB_INTRRXE */
695
696#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
697#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
698#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
699#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
700#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
701#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
702#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
703
704/* Bit masks for USB_INTRUSB */
705
706#define SUSPEND_B 0x1 /* Suspend indicator */
707#define RESUME_B 0x2 /* Resume indicator */
708#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
709#define SOF_B 0x8 /* Start of frame */
710#define CONN_B 0x10 /* Connection indicator */
711#define DISCON_B 0x20 /* Disconnect indicator */
712#define SESSION_REQ_B 0x40 /* Session Request */
713#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
714
715/* Bit masks for USB_INTRUSBE */
716
717#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
718#define RESUME_BE 0x2 /* Resume indicator int enable */
719#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
720#define SOF_BE 0x8 /* Start of frame int enable */
721#define CONN_BE 0x10 /* Connection indicator int enable */
722#define DISCON_BE 0x20 /* Disconnect indicator int enable */
723#define SESSION_REQ_BE 0x40 /* Session Request int enable */
724#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
725
726/* Bit masks for USB_FRAME */
727
728#define FRAME_NUMBER 0x7ff /* Frame number */
729
730/* Bit masks for USB_INDEX */
731
732#define SELECTED_ENDPOINT 0xf /* selected endpoint */
733
734/* Bit masks for USB_GLOBAL_CTL */
735
736#define GLOBAL_ENA 0x1 /* enables USB module */
737#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
738#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
739#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
740#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
741#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
742#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
743#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
744#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
745#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
746#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
747#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
748#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
749#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
750#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
751
752/* Bit masks for USB_OTG_DEV_CTL */
753
754#define SESSION 0x1 /* session indicator */
755#define HOST_REQ 0x2 /* Host negotiation request */
756#define HOST_MODE 0x4 /* indicates USBDRC is a host */
757#define VBUS0 0x8 /* Vbus level indicator[0] */
758#define VBUS1 0x10 /* Vbus level indicator[1] */
759#define LSDEV 0x20 /* Low-speed indicator */
760#define FSDEV 0x40 /* Full or High-speed indicator */
761#define B_DEVICE 0x80 /* A' or 'B' device indicator */
762
763/* Bit masks for USB_OTG_VBUS_IRQ */
764
765#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
766#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
767#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
768#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
769#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
770#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
771
772/* Bit masks for USB_OTG_VBUS_MASK */
773
774#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
775#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
776#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
777#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
778#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
779#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
780
781/* Bit masks for USB_CSR0 */
782
783#define RXPKTRDY 0x1 /* data packet receive indicator */
784#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
785#define STALL_SENT 0x4 /* STALL handshake sent */
786#define DATAEND 0x8 /* Data end indicator */
787#define SETUPEND 0x10 /* Setup end */
788#define SENDSTALL 0x20 /* Send STALL handshake */
789#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
790#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
791#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
792#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
793#define SETUPPKT_H 0x8 /* send Setup token host mode */
794#define ERROR_H 0x10 /* timeout error indicator host mode */
795#define REQPKT_H 0x20 /* Request an IN transaction host mode */
796#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
797#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
798
799/* Bit masks for USB_COUNT0 */
800
801#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
802
803/* Bit masks for USB_NAKLIMIT0 */
804
805#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
806
807/* Bit masks for USB_TX_MAX_PACKET */
808
809#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
810
811/* Bit masks for USB_RX_MAX_PACKET */
812
813#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
814
815/* Bit masks for USB_TXCSR */
816
817#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
818#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
819#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
820#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
821#define STALL_SEND_T 0x10 /* issue a Stall handshake */
822#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
823#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
824#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
825#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
826#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
827#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
828#define ISO_T 0x4000 /* enable Isochronous transfers */
829#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
830#define ERROR_TH 0x4 /* error condition host mode */
831#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
832#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
833
834/* Bit masks for USB_TXCOUNT */
835
836#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
837
838/* Bit masks for USB_RXCSR */
839
840#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
841#define FIFO_FULL_R 0x2 /* FIFO not empty */
842#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
843#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
844#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
845#define STALL_SEND_R 0x20 /* issue a Stall handshake */
846#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
847#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
848#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
849#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
850#define DISNYET_R 0x1000 /* disable Nyet handshakes */
851#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
852#define ISO_R 0x4000 /* enable Isochronous transfers */
853#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
854#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
855#define REQPKT_RH 0x20 /* request an IN transaction host mode */
856#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
857#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
858#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
859#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
860
861/* Bit masks for USB_RXCOUNT */
862
863#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
864
865/* Bit masks for USB_TXTYPE */
866
867#define TARGET_EP_NO_T 0xf /* EP number */
868#define PROTOCOL_T 0xc /* transfer type */
869
870/* Bit masks for USB_TXINTERVAL */
871
872#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
873
874/* Bit masks for USB_RXTYPE */
875
876#define TARGET_EP_NO_R 0xf /* EP number */
877#define PROTOCOL_R 0xc /* transfer type */
878
879/* Bit masks for USB_RXINTERVAL */
880
881#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
882
883/* Bit masks for USB_DMA_INTERRUPT */
884
885#define DMA0_INT 0x1 /* DMA0 pending interrupt */
886#define DMA1_INT 0x2 /* DMA1 pending interrupt */
887#define DMA2_INT 0x4 /* DMA2 pending interrupt */
888#define DMA3_INT 0x8 /* DMA3 pending interrupt */
889#define DMA4_INT 0x10 /* DMA4 pending interrupt */
890#define DMA5_INT 0x20 /* DMA5 pending interrupt */
891#define DMA6_INT 0x40 /* DMA6 pending interrupt */
892#define DMA7_INT 0x80 /* DMA7 pending interrupt */
893
894/* Bit masks for USB_DMAxCONTROL */
895
896#define DMA_ENA 0x1 /* DMA enable */
897#define DIRECTION 0x2 /* direction of DMA transfer */
898#define MODE 0x4 /* DMA Bus error */
899#define INT_ENA 0x8 /* Interrupt enable */
900#define EPNUM 0xf0 /* EP number */
901#define BUSERROR 0x100 /* DMA Bus error */
902
903/* Bit masks for USB_DMAxADDRHIGH */
904
905#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
906
907/* Bit masks for USB_DMAxADDRLOW */
908
909#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
910
911/* Bit masks for USB_DMAxCOUNTHIGH */
912
913#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
914
915/* Bit masks for USB_DMAxCOUNTLOW */
916
917#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
918
919
920/* ******************************************* */
921/* MULTI BIT MACRO ENUMERATIONS */
922/* ******************************************* */
923
924
925#endif /* _DEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
deleted file mode 100644
index b8b9870e2697..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ /dev/null
@@ -1,707 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF544.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF544_H
32#define _DEF_BF544_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* EPPI0 Registers */
66
67#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
68#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
69#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
70#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
71#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
72#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
73#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
74#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
75#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
76#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
77#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
78#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
79#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
80#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
81
82/* Two Wire Interface Registers (TWI1) */
83
84#define TWI1_REGBASE 0xffc02200
85#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
86#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
87#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
88#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
89#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
90#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
91#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
92#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
93#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
94#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
95#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
96#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
97#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
98#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
99#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
100#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
101
102/* CAN Controller 1 Config 1 Registers */
103
104#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
105#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
106#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
107#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
108#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
109#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
110#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
111#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
112#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
113#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
114#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
115#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
116#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
117
118/* CAN Controller 1 Config 2 Registers */
119
120#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
121#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
122#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
123#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
124#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
125#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
126#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
127#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
128#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
129#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
130#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
131#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
132#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
133
134/* CAN Controller 1 Clock/Interrupt/Counter Registers */
135
136#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
137#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
138#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
139#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
140#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
141#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
142#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
143#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
144#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
145#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
146#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
147#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
148#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
149#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
150#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
151#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
152
153/* CAN Controller 1 Mailbox Acceptance Registers */
154
155#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
156#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
157#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
158#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
159#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
160#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
161#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
162#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
163#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
164#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
165#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
166#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
167#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
168#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
169#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
170#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
171#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
172#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
173#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
174#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
175#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
176#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
177#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
178#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
179#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
180#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
181#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
182#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
183#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
184#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
185#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
186#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
187
188/* CAN Controller 1 Mailbox Acceptance Registers */
189
190#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
191#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
192#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
193#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
194#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
195#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
196#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
197#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
198#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
199#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
200#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
201#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
202#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
203#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
204#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
205#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
206#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
207#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
208#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
209#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
210#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
211#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
212#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
213#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
214#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
215#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
216#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
217#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
218#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
219#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
220#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
221#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
222
223/* CAN Controller 1 Mailbox Data Registers */
224
225#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
226#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
227#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
228#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
229#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
230#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
231#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
232#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
233#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
234#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
235#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
236#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
237#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
238#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
239#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
240#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
241#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
242#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
243#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
244#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
245#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
246#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
247#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
248#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
249#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
250#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
251#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
252#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
253#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
254#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
255#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
256#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
257#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
258#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
259#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
260#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
261#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
262#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
263#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
264#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
265#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
266#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
267#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
268#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
269#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
270#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
271#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
272#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
273#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
274#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
275#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
276#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
277#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
278#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
279#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
280#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
281#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
282#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
283#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
284#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
285#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
286#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
287#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
288#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
289#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
290#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
291#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
292#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
293#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
294#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
295#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
296#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
297#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
298#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
299#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
300#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
301#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
302#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
303#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
304#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
305#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
306#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
307#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
308#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
309#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
310#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
311#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
312#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
313#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
314#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
315#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
316#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
317#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
318#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
319#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
320#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
321#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
322#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
323#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
324#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
325#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
326#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
327#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
328#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
329#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
330#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
331#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
332#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
333#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
334#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
335#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
336#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
337#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
338#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
339#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
340#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
341#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
342#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
343#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
344#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
345#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
346#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
347#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
348#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
349#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
350#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
351#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
352#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
353
354/* CAN Controller 1 Mailbox Data Registers */
355
356#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
357#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
358#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
359#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
360#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
361#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
362#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
363#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
364#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
365#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
366#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
367#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
368#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
369#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
370#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
371#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
372#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
373#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
374#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
375#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
376#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
377#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
378#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
379#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
380#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
381#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
382#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
383#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
384#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
385#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
386#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
387#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
388#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
389#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
390#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
391#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
392#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
393#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
394#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
395#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
396#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
397#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
398#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
399#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
400#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
401#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
402#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
403#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
404#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
405#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
406#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
407#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
408#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
409#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
410#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
411#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
412#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
413#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
414#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
415#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
416#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
417#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
418#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
419#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
420#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
421#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
422#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
423#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
424#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
425#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
426#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
427#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
428#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
429#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
430#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
431#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
432#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
433#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
434#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
435#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
436#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
437#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
438#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
439#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
440#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
441#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
442#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
443#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
444#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
445#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
446#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
447#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
448#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
449#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
450#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
451#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
452#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
453#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
454#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
455#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
456#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
457#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
458#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
459#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
460#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
461#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
462#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
463#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
464#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
465#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
466#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
467#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
468#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
469#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
470#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
471#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
472#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
473#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
474#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
475#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
476#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
477#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
478#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
479#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
480#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
481#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
482#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
483#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
484
485/* HOST Port Registers */
486
487#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
488#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
489#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
490
491/* Pixel Compositor (PIXC) Registers */
492
493#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
494#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
495#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
496#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
497#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
498#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
499#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
500#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
501#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
502#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
503#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
504#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
505#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
506#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
507#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
508#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
509#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
510#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
511#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
512
513/* Handshake MDMA 0 Registers */
514
515#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
516#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
517#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
518#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
519#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
520#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
521#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
522
523/* Handshake MDMA 1 Registers */
524
525#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
526#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
527#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
528#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
529#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
530#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
531#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
532
533
534/* ********************************************************** */
535/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
536/* and MULTI BIT READ MACROS */
537/* ********************************************************** */
538
539/* Bit masks for PIXC_CTL */
540
541#define PIXC_EN 0x1 /* Pixel Compositor Enable */
542#define OVR_A_EN 0x2 /* Overlay A Enable */
543#define OVR_B_EN 0x4 /* Overlay B Enable */
544#define IMG_FORM 0x8 /* Image Data Format */
545#define OVR_FORM 0x10 /* Overlay Data Format */
546#define OUT_FORM 0x20 /* Output Data Format */
547#define UDS_MOD 0x40 /* Resampling Mode */
548#define TC_EN 0x80 /* Transparent Color Enable */
549#define IMG_STAT 0x300 /* Image FIFO Status */
550#define OVR_STAT 0xc00 /* Overlay FIFO Status */
551#define WM_LVL 0x3000 /* FIFO Watermark Level */
552
553/* Bit masks for PIXC_AHSTART */
554
555#define A_HSTART 0xfff /* Horizontal Start Coordinates */
556
557/* Bit masks for PIXC_AHEND */
558
559#define A_HEND 0xfff /* Horizontal End Coordinates */
560
561/* Bit masks for PIXC_AVSTART */
562
563#define A_VSTART 0x3ff /* Vertical Start Coordinates */
564
565/* Bit masks for PIXC_AVEND */
566
567#define A_VEND 0x3ff /* Vertical End Coordinates */
568
569/* Bit masks for PIXC_ATRANSP */
570
571#define A_TRANSP 0xf /* Transparency Value */
572
573/* Bit masks for PIXC_BHSTART */
574
575#define B_HSTART 0xfff /* Horizontal Start Coordinates */
576
577/* Bit masks for PIXC_BHEND */
578
579#define B_HEND 0xfff /* Horizontal End Coordinates */
580
581/* Bit masks for PIXC_BVSTART */
582
583#define B_VSTART 0x3ff /* Vertical Start Coordinates */
584
585/* Bit masks for PIXC_BVEND */
586
587#define B_VEND 0x3ff /* Vertical End Coordinates */
588
589/* Bit masks for PIXC_BTRANSP */
590
591#define B_TRANSP 0xf /* Transparency Value */
592
593/* Bit masks for PIXC_INTRSTAT */
594
595#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
596#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
597#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
598#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
599
600/* Bit masks for PIXC_RYCON */
601
602#define A11 0x3ff /* A11 in the Coefficient Matrix */
603#define A12 0xffc00 /* A12 in the Coefficient Matrix */
604#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
605#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
606
607/* Bit masks for PIXC_GUCON */
608
609#define A21 0x3ff /* A21 in the Coefficient Matrix */
610#define A22 0xffc00 /* A22 in the Coefficient Matrix */
611#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
612#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
613
614/* Bit masks for PIXC_BVCON */
615
616#define A31 0x3ff /* A31 in the Coefficient Matrix */
617#define A32 0xffc00 /* A32 in the Coefficient Matrix */
618#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
619#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
620
621/* Bit masks for PIXC_CCBIAS */
622
623#define A14 0x3ff /* A14 in the Bias Vector */
624#define A24 0xffc00 /* A24 in the Bias Vector */
625#define A34 0x3ff00000 /* A34 in the Bias Vector */
626
627/* Bit masks for PIXC_TC */
628
629#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
630#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
631#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
632
633/* Bit masks for HOST_CONTROL */
634
635#define HOST_EN 0x1 /* Host Enable */
636#define HOST_END 0x2 /* Host Endianess */
637#define DATA_SIZE 0x4 /* Data Size */
638#define HOST_RST 0x8 /* Host Reset */
639#define HRDY_OVR 0x20 /* Host Ready Override */
640#define INT_MODE 0x40 /* Interrupt Mode */
641#define BT_EN 0x80 /* Bus Timeout Enable */
642#define EHW 0x100 /* Enable Host Write */
643#define EHR 0x200 /* Enable Host Read */
644#define BDR 0x400 /* Burst DMA Requests */
645
646/* Bit masks for HOST_STATUS */
647
648#define DMA_READY 0x1 /* DMA Ready */
649#define FIFOFULL 0x2 /* FIFO Full */
650#define FIFOEMPTY 0x4 /* FIFO Empty */
651#define COMPLETE 0x8 /* DMA Complete */
652#define HSHK 0x10 /* Host Handshake */
653#define TIMEOUT 0x20 /* Host Timeout */
654#define HIRQ 0x40 /* Host Interrupt Request */
655#define ALLOW_CNFG 0x80 /* Allow New Configuration */
656#define DMA_DIR 0x100 /* DMA Direction */
657#define BTE 0x200 /* Bus Timeout Enabled */
658
659/* Bit masks for HOST_TIMEOUT */
660
661#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
662
663/* Bit masks for TIMER_ENABLE1 */
664
665#define TIMEN8 0x1 /* Timer 8 Enable */
666#define TIMEN9 0x2 /* Timer 9 Enable */
667#define TIMEN10 0x4 /* Timer 10 Enable */
668
669/* Bit masks for TIMER_DISABLE1 */
670
671#define TIMDIS8 0x1 /* Timer 8 Disable */
672#define TIMDIS9 0x2 /* Timer 9 Disable */
673#define TIMDIS10 0x4 /* Timer 10 Disable */
674
675/* Bit masks for TIMER_STATUS1 */
676
677#define TIMIL8 0x1 /* Timer 8 Interrupt */
678#define TIMIL9 0x2 /* Timer 9 Interrupt */
679#define TIMIL10 0x4 /* Timer 10 Interrupt */
680#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
681#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
682#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
683#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
684#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
685#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
686
687/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
688
689/* Bit masks for HMDMAx_CONTROL */
690
691#define HMDMAEN 0x1 /* Handshake MDMA Enable */
692#define REP 0x2 /* Handshake MDMA Request Polarity */
693#define UTE 0x8 /* Urgency Threshold Enable */
694#define OIE 0x10 /* Overflow Interrupt Enable */
695#define BDIE 0x20 /* Block Done Interrupt Enable */
696#define MBDI 0x40 /* Mask Block Done Interrupt */
697#define DRQ 0x300 /* Handshake MDMA Request Type */
698#define RBC 0x1000 /* Force Reload of BCOUNT */
699#define PS 0x2000 /* Pin Status */
700#define OI 0x4000 /* Overflow Interrupt Generated */
701#define BDI 0x8000 /* Block Done Interrupt Generated */
702
703/* ******************************************* */
704/* MULTI BIT MACRO ENUMERATIONS */
705/* ******************************************* */
706
707#endif /* _DEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF547.h b/include/asm-blackfin/mach-bf548/defBF547.h
deleted file mode 100644
index 3a3a18ebb10e..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF547.h
+++ /dev/null
@@ -1,1244 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF547.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF548_H
32#define _DEF_BF548_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* SPORT0 Registers */
66
67#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
68#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
69#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
70#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
71#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
72#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
73#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
74#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
75#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
76#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
77#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
78#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
79#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
80#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
81#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
82#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
83#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
84#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
85#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
86#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
87#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
88#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
89
90/* EPPI0 Registers */
91
92#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
93#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
94#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
95#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
96#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
97#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
98#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
99#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
100#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
101#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
102#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
103#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
104#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
105#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
106
107/* UART2 Registers */
108
109#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
110#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
111#define UART2_GCTL 0xffc02108 /* Global Control Register */
112#define UART2_LCR 0xffc0210c /* Line Control Register */
113#define UART2_MCR 0xffc02110 /* Modem Control Register */
114#define UART2_LSR 0xffc02114 /* Line Status Register */
115#define UART2_MSR 0xffc02118 /* Modem Status Register */
116#define UART2_SCR 0xffc0211c /* Scratch Register */
117#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
118#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
119#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
120
121/* Two Wire Interface Registers (TWI1) */
122
123#define TWI1_REGBASE 0xffc02200
124#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
125#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
126#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
127#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
128#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
129#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
130#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
131#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
132#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
133#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
134#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
135#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
136#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
137#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
138#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
139#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
140
141/* SPI2 Registers */
142
143#define SPI2_REGBASE 0xffc02400
144#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
145#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
146#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
147#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
148#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
149#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
150#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
151
152/* ATAPI Registers */
153
154#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
155#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
156#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
157#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
158#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
159#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
160#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
161#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
162#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
163#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
164#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
165#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
166#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
167#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
168#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
169#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
170#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
171#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
172#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
173#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
174#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
175#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
176#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
177#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
178#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
179
180/* SDH Registers */
181
182#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
183#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
184#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
185#define SDH_COMMAND 0xffc0390c /* SDH Command */
186#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
187#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
188#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
189#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
190#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
191#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
192#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
193#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
194#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
195#define SDH_STATUS 0xffc03934 /* SDH Status */
196#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
197#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
198#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
199#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
200#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
201#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
202#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
203#define SDH_CFG 0xffc039c8 /* SDH Configuration */
204#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
205#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
206#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
207#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
208#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
209#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
210#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
211#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
212#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
213
214/* HOST Port Registers */
215
216#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
217#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
218#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
219
220/* USB Control Registers */
221
222#define USB_FADDR 0xffc03c00 /* Function address register */
223#define USB_POWER 0xffc03c04 /* Power management register */
224#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
225#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
226#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
227#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
228#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
229#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
230#define USB_FRAME 0xffc03c20 /* USB frame number */
231#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
232#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
233#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
234#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
235
236/* USB Packet Control Registers */
237
238#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
239#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
240#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
241#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
242#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
243#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
244#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
245#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
246#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
247#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
248#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
249#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
250#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
251
252/* USB Endpoint FIFO Registers */
253
254#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
255#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
256#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
257#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
258#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
259#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
260#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
261#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
262
263/* USB OTG Control Registers */
264
265#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
266#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
267#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
268
269/* USB Phy Control Registers */
270
271#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
272#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
273#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
274#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
275#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
276
277/* (APHY_CNTRL is for ADI usage only) */
278
279#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
280
281/* (APHY_CALIB is for ADI usage only) */
282
283#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
284#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
285
286/* (PHY_TEST is for ADI usage only) */
287
288#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
289#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
290#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
291
292/* USB Endpoint 0 Control Registers */
293
294#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
295#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
296#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
297#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
298#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
299#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
300#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
301#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
302#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
303
304/* USB Endpoint 1 Control Registers */
305
306#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
307#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
308#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
309#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
310#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
311#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
312#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
313#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
314#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
315#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
316
317/* USB Endpoint 2 Control Registers */
318
319#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
320#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
321#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
322#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
323#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
324#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
325#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
326#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
327#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
328#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
329
330/* USB Endpoint 3 Control Registers */
331
332#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
333#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
334#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
335#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
336#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
337#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
338#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
339#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
340#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
341#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
342
343/* USB Endpoint 4 Control Registers */
344
345#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
346#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
347#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
348#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
349#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
350#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
351#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
352#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
353#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
354#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
355
356/* USB Endpoint 5 Control Registers */
357
358#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
359#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
360#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
361#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
362#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
363#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
364#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
365#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
366#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
367#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
368
369/* USB Endpoint 6 Control Registers */
370
371#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
372#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
373#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
374#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
375#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
376#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
377#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
378#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
379#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
380#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
381
382/* USB Endpoint 7 Control Registers */
383
384#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
385#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
386#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
387#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
388#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
389#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
390#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
391#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
392#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
393#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
394#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
395#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
396
397/* USB Channel 0 Config Registers */
398
399#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
400#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
401#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
402#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
403#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
404
405/* USB Channel 1 Config Registers */
406
407#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
408#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
409#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
410#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
411#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
412
413/* USB Channel 2 Config Registers */
414
415#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
416#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
417#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
418#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
419#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
420
421/* USB Channel 3 Config Registers */
422
423#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
424#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
425#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
426#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
427#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
428
429/* USB Channel 4 Config Registers */
430
431#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
432#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
433#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
434#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
435#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
436
437/* USB Channel 5 Config Registers */
438
439#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
440#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
441#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
442#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
443#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
444
445/* USB Channel 6 Config Registers */
446
447#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
448#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
449#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
450#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
451#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
452
453/* USB Channel 7 Config Registers */
454
455#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
456#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
457#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
458#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
459#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
460
461/* Keypad Registers */
462
463#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
464#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
465#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
466#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
467#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
468#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
469
470/* Pixel Compositor (PIXC) Registers */
471
472#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
473#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
474#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
475#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
476#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
477#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
478#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
479#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
480#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
481#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
482#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
483#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
484#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
485#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
486#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
487#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
488#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
489#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
490#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
491
492/* Handshake MDMA 0 Registers */
493
494#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
495#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
496#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
497#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
498#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
499#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
500#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
501
502/* Handshake MDMA 1 Registers */
503
504#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
505#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
506#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
507#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
508#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
509#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
510#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
511
512
513/* ********************************************************** */
514/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
515/* and MULTI BIT READ MACROS */
516/* ********************************************************** */
517
518/* Bit masks for PIXC_CTL */
519
520#define PIXC_EN 0x1 /* Pixel Compositor Enable */
521#define OVR_A_EN 0x2 /* Overlay A Enable */
522#define OVR_B_EN 0x4 /* Overlay B Enable */
523#define IMG_FORM 0x8 /* Image Data Format */
524#define OVR_FORM 0x10 /* Overlay Data Format */
525#define OUT_FORM 0x20 /* Output Data Format */
526#define UDS_MOD 0x40 /* Resampling Mode */
527#define TC_EN 0x80 /* Transparent Color Enable */
528#define IMG_STAT 0x300 /* Image FIFO Status */
529#define OVR_STAT 0xc00 /* Overlay FIFO Status */
530#define WM_LVL 0x3000 /* FIFO Watermark Level */
531
532/* Bit masks for PIXC_AHSTART */
533
534#define A_HSTART 0xfff /* Horizontal Start Coordinates */
535
536/* Bit masks for PIXC_AHEND */
537
538#define A_HEND 0xfff /* Horizontal End Coordinates */
539
540/* Bit masks for PIXC_AVSTART */
541
542#define A_VSTART 0x3ff /* Vertical Start Coordinates */
543
544/* Bit masks for PIXC_AVEND */
545
546#define A_VEND 0x3ff /* Vertical End Coordinates */
547
548/* Bit masks for PIXC_ATRANSP */
549
550#define A_TRANSP 0xf /* Transparency Value */
551
552/* Bit masks for PIXC_BHSTART */
553
554#define B_HSTART 0xfff /* Horizontal Start Coordinates */
555
556/* Bit masks for PIXC_BHEND */
557
558#define B_HEND 0xfff /* Horizontal End Coordinates */
559
560/* Bit masks for PIXC_BVSTART */
561
562#define B_VSTART 0x3ff /* Vertical Start Coordinates */
563
564/* Bit masks for PIXC_BVEND */
565
566#define B_VEND 0x3ff /* Vertical End Coordinates */
567
568/* Bit masks for PIXC_BTRANSP */
569
570#define B_TRANSP 0xf /* Transparency Value */
571
572/* Bit masks for PIXC_INTRSTAT */
573
574#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
575#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
576#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
577#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
578
579/* Bit masks for PIXC_RYCON */
580
581#define A11 0x3ff /* A11 in the Coefficient Matrix */
582#define A12 0xffc00 /* A12 in the Coefficient Matrix */
583#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
584#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
585
586/* Bit masks for PIXC_GUCON */
587
588#define A21 0x3ff /* A21 in the Coefficient Matrix */
589#define A22 0xffc00 /* A22 in the Coefficient Matrix */
590#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
591#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
592
593/* Bit masks for PIXC_BVCON */
594
595#define A31 0x3ff /* A31 in the Coefficient Matrix */
596#define A32 0xffc00 /* A32 in the Coefficient Matrix */
597#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
598#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
599
600/* Bit masks for PIXC_CCBIAS */
601
602#define A14 0x3ff /* A14 in the Bias Vector */
603#define A24 0xffc00 /* A24 in the Bias Vector */
604#define A34 0x3ff00000 /* A34 in the Bias Vector */
605
606/* Bit masks for PIXC_TC */
607
608#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
609#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
610#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
611
612/* Bit masks for HOST_CONTROL */
613
614#define HOST_EN 0x1 /* Host Enable */
615#define HOST_END 0x2 /* Host Endianess */
616#define DATA_SIZE 0x4 /* Data Size */
617#define HOST_RST 0x8 /* Host Reset */
618#define HRDY_OVR 0x20 /* Host Ready Override */
619#define INT_MODE 0x40 /* Interrupt Mode */
620#define BT_EN 0x80 /* Bus Timeout Enable */
621#define EHW 0x100 /* Enable Host Write */
622#define EHR 0x200 /* Enable Host Read */
623#define BDR 0x400 /* Burst DMA Requests */
624
625/* Bit masks for HOST_STATUS */
626
627#define DMA_READY 0x1 /* DMA Ready */
628#define FIFOFULL 0x2 /* FIFO Full */
629#define FIFOEMPTY 0x4 /* FIFO Empty */
630#define DMA_COMPLETE 0x8 /* DMA Complete */
631#define HSHK 0x10 /* Host Handshake */
632#define HSTIMEOUT 0x20 /* Host Timeout */
633#define HIRQ 0x40 /* Host Interrupt Request */
634#define ALLOW_CNFG 0x80 /* Allow New Configuration */
635#define DMA_DIR 0x100 /* DMA Direction */
636#define BTE 0x200 /* Bus Timeout Enabled */
637
638/* Bit masks for HOST_TIMEOUT */
639
640#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
641
642/* Bit masks for KPAD_CTL */
643
644#define KPAD_EN 0x1 /* Keypad Enable */
645#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
646#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
647#define KPAD_COLEN 0xe000 /* Column Enable Width */
648
649/* Bit masks for KPAD_PRESCALE */
650
651#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
652
653/* Bit masks for KPAD_MSEL */
654
655#define DBON_SCALE 0xff /* Debounce Scale Value */
656#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
657
658/* Bit masks for KPAD_ROWCOL */
659
660#define KPAD_ROW 0xff /* Rows Pressed */
661#define KPAD_COL 0xff00 /* Columns Pressed */
662
663/* Bit masks for KPAD_STAT */
664
665#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
666#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
667#define KPAD_PRESSED 0x8 /* Key press current status */
668
669/* Bit masks for KPAD_SOFTEVAL */
670
671#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
672
673/* Bit masks for SDH_COMMAND */
674
675#define CMD_IDX 0x3f /* Command Index */
676#define CMD_RSP 0x40 /* Response */
677#define CMD_L_RSP 0x80 /* Long Response */
678#define CMD_INT_E 0x100 /* Command Interrupt */
679#define CMD_PEND_E 0x200 /* Command Pending */
680#define CMD_E 0x400 /* Command Enable */
681
682/* Bit masks for SDH_PWR_CTL */
683
684#define PWR_ON 0x3 /* Power On */
685#if 0
686#define TBD 0x3c /* TBD */
687#endif
688#define SD_CMD_OD 0x40 /* Open Drain Output */
689#define ROD_CTL 0x80 /* Rod Control */
690
691/* Bit masks for SDH_CLK_CTL */
692
693#define CLKDIV 0xff /* MC_CLK Divisor */
694#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
695#define PWR_SV_E 0x200 /* Power Save Enable */
696#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
697#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
698
699/* Bit masks for SDH_RESP_CMD */
700
701#define RESP_CMD 0x3f /* Response Command */
702
703/* Bit masks for SDH_DATA_CTL */
704
705#define DTX_E 0x1 /* Data Transfer Enable */
706#define DTX_DIR 0x2 /* Data Transfer Direction */
707#define DTX_MODE 0x4 /* Data Transfer Mode */
708#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
709#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
710
711/* Bit masks for SDH_STATUS */
712
713#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
714#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
715#define CMD_TIME_OUT 0x4 /* CMD Time Out */
716#define DAT_TIME_OUT 0x8 /* Data Time Out */
717#define TX_UNDERRUN 0x10 /* Transmit Underrun */
718#define RX_OVERRUN 0x20 /* Receive Overrun */
719#define CMD_RESP_END 0x40 /* CMD Response End */
720#define CMD_SENT 0x80 /* CMD Sent */
721#define DAT_END 0x100 /* Data End */
722#define START_BIT_ERR 0x200 /* Start Bit Error */
723#define DAT_BLK_END 0x400 /* Data Block End */
724#define CMD_ACT 0x800 /* CMD Active */
725#define TX_ACT 0x1000 /* Transmit Active */
726#define RX_ACT 0x2000 /* Receive Active */
727#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
728#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
729#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
730#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
731#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
732#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
733#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
734#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
735
736/* Bit masks for SDH_STATUS_CLR */
737
738#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
739#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
740#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
741#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
742#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
743#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
744#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
745#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
746#define DAT_END_STAT 0x100 /* Data End Status */
747#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
748#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
749
750/* Bit masks for SDH_MASK0 */
751
752#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
753#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
754#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
755#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
756#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
757#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
758#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
759#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
760#define DAT_END_MASK 0x100 /* Data End Mask */
761#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
762#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
763#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
764#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
765#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
766#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
767#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
768#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
769#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
770#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
771#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
772#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
773#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
774
775/* Bit masks for SDH_FIFO_CNT */
776
777#define FIFO_COUNT 0x7fff /* FIFO Count */
778
779/* Bit masks for SDH_E_STATUS */
780
781#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
782#define SD_CARD_DET 0x10 /* SD Card Detect */
783
784/* Bit masks for SDH_E_MASK */
785
786#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
787#define SCD_MSK 0x40 /* Mask Card Detect */
788
789/* Bit masks for SDH_CFG */
790
791#define CLKS_EN 0x1 /* Clocks Enable */
792#define SD4E 0x4 /* SDIO 4-Bit Enable */
793#define MWE 0x8 /* Moving Window Enable */
794#define SD_RST 0x10 /* SDMMC Reset */
795#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
796#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
797#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
798
799/* Bit masks for SDH_RD_WAIT_EN */
800
801#define RWR 0x1 /* Read Wait Request */
802
803/* Bit masks for ATAPI_CONTROL */
804
805#define PIO_START 0x1 /* Start PIO/Reg Op */
806#define MULTI_START 0x2 /* Start Multi-DMA Op */
807#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
808#define XFER_DIR 0x8 /* Transfer Direction */
809#define IORDY_EN 0x10 /* IORDY Enable */
810#define FIFO_FLUSH 0x20 /* Flush FIFOs */
811#define SOFT_RST 0x40 /* Soft Reset */
812#define DEV_RST 0x80 /* Device Reset */
813#define TFRCNT_RST 0x100 /* Trans Count Reset */
814#define END_ON_TERM 0x200 /* End/Terminate Select */
815#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
816#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
817
818/* Bit masks for ATAPI_STATUS */
819
820#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
821#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
822#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
823#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
824
825/* Bit masks for ATAPI_DEV_ADDR */
826
827#define DEV_ADDR 0x1f /* Device Address */
828
829/* Bit masks for ATAPI_INT_MASK */
830
831#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
832#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
833#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
834#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
835#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
836#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
837#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
838#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
839#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
840
841/* Bit masks for ATAPI_INT_STATUS */
842
843#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
844#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
845#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
846#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
847#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
848#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
849#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
850#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
851#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
852
853/* Bit masks for ATAPI_LINE_STATUS */
854
855#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
856#define ATAPI_DASP 0x2 /* Device dasp to host line status */
857#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
858#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
859#define ATAPI_ADDR 0x70 /* ATAPI address line status */
860#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
861#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
862#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
863#define ATAPI_DIORN 0x400 /* ATAPI read line status */
864#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
865
866/* Bit masks for ATAPI_SM_STATE */
867
868#define PIO_CSTATE 0xf /* PIO mode state machine current state */
869#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
870#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
871#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
872
873/* Bit masks for ATAPI_TERMINATE */
874
875#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
876
877/* Bit masks for ATAPI_REG_TIM_0 */
878
879#define T2_REG 0xff /* End of cycle time for register access transfers */
880#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
881
882/* Bit masks for ATAPI_PIO_TIM_0 */
883
884#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
885#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
886#define T4_REG 0xf000 /* DIOW data hold */
887
888/* Bit masks for ATAPI_PIO_TIM_1 */
889
890#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
891
892/* Bit masks for ATAPI_MULTI_TIM_0 */
893
894#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
895#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
896
897/* Bit masks for ATAPI_MULTI_TIM_1 */
898
899#define TKW 0xff /* Selects DIOW negated pulsewidth */
900#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
901
902/* Bit masks for ATAPI_MULTI_TIM_2 */
903
904#define TH 0xff /* Selects DIOW data hold */
905#define TEOC 0xff00 /* Selects end of cycle for DMA */
906
907/* Bit masks for ATAPI_ULTRA_TIM_0 */
908
909#define TACK 0xff /* Selects setup and hold times for TACK */
910#define TENV 0xff00 /* Selects envelope time */
911
912/* Bit masks for ATAPI_ULTRA_TIM_1 */
913
914#define TDVS 0xff /* Selects data valid setup time */
915#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
916
917/* Bit masks for ATAPI_ULTRA_TIM_2 */
918
919#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
920#define TMLI 0xff00 /* Selects interlock time */
921
922/* Bit masks for ATAPI_ULTRA_TIM_3 */
923
924#define TZAH 0xff /* Selects minimum delay required for output */
925#define READY_PAUSE 0xff00 /* Selects ready to pause */
926
927/* Bit masks for TIMER_ENABLE1 */
928
929#define TIMEN8 0x1 /* Timer 8 Enable */
930#define TIMEN9 0x2 /* Timer 9 Enable */
931#define TIMEN10 0x4 /* Timer 10 Enable */
932
933/* Bit masks for TIMER_DISABLE1 */
934
935#define TIMDIS8 0x1 /* Timer 8 Disable */
936#define TIMDIS9 0x2 /* Timer 9 Disable */
937#define TIMDIS10 0x4 /* Timer 10 Disable */
938
939/* Bit masks for TIMER_STATUS1 */
940
941#define TIMIL8 0x1 /* Timer 8 Interrupt */
942#define TIMIL9 0x2 /* Timer 9 Interrupt */
943#define TIMIL10 0x4 /* Timer 10 Interrupt */
944#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
945#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
946#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
947#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
948#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
949#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
950
951/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
952
953/* Bit masks for USB_FADDR */
954
955#define FUNCTION_ADDRESS 0x7f /* Function address */
956
957/* Bit masks for USB_POWER */
958
959#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
960#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
961#define RESUME_MODE 0x4 /* DMA Mode */
962#define RESET 0x8 /* Reset indicator */
963#define HS_MODE 0x10 /* High Speed mode indicator */
964#define HS_ENABLE 0x20 /* high Speed Enable */
965#define SOFT_CONN 0x40 /* Soft connect */
966#define ISO_UPDATE 0x80 /* Isochronous update */
967
968/* Bit masks for USB_INTRTX */
969
970#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
971#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
972#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
973#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
974#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
975#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
976#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
977#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
978
979/* Bit masks for USB_INTRRX */
980
981#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
982#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
983#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
984#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
985#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
986#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
987#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
988
989/* Bit masks for USB_INTRTXE */
990
991#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
992#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
993#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
994#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
995#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
996#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
997#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
998#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
999
1000/* Bit masks for USB_INTRRXE */
1001
1002#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1003#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1004#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1005#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1006#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1007#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1008#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1009
1010/* Bit masks for USB_INTRUSB */
1011
1012#define SUSPEND_B 0x1 /* Suspend indicator */
1013#define RESUME_B 0x2 /* Resume indicator */
1014#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1015#define SOF_B 0x8 /* Start of frame */
1016#define CONN_B 0x10 /* Connection indicator */
1017#define DISCON_B 0x20 /* Disconnect indicator */
1018#define SESSION_REQ_B 0x40 /* Session Request */
1019#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1020
1021/* Bit masks for USB_INTRUSBE */
1022
1023#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1024#define RESUME_BE 0x2 /* Resume indicator int enable */
1025#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1026#define SOF_BE 0x8 /* Start of frame int enable */
1027#define CONN_BE 0x10 /* Connection indicator int enable */
1028#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1029#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1030#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1031
1032/* Bit masks for USB_FRAME */
1033
1034#define FRAME_NUMBER 0x7ff /* Frame number */
1035
1036/* Bit masks for USB_INDEX */
1037
1038#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1039
1040/* Bit masks for USB_GLOBAL_CTL */
1041
1042#define GLOBAL_ENA 0x1 /* enables USB module */
1043#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1044#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1045#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1046#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1047#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1048#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1049#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1050#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1051#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1052#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1053#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1054#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1055#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1056#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1057
1058/* Bit masks for USB_OTG_DEV_CTL */
1059
1060#define SESSION 0x1 /* session indicator */
1061#define HOST_REQ 0x2 /* Host negotiation request */
1062#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1063#define VBUS0 0x8 /* Vbus level indicator[0] */
1064#define VBUS1 0x10 /* Vbus level indicator[1] */
1065#define LSDEV 0x20 /* Low-speed indicator */
1066#define FSDEV 0x40 /* Full or High-speed indicator */
1067#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1068
1069/* Bit masks for USB_OTG_VBUS_IRQ */
1070
1071#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1072#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1073#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1074#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1075#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1076#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1077
1078/* Bit masks for USB_OTG_VBUS_MASK */
1079
1080#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1081#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1082#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1083#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1084#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1085#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1086
1087/* Bit masks for USB_CSR0 */
1088
1089#define RXPKTRDY 0x1 /* data packet receive indicator */
1090#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1091#define STALL_SENT 0x4 /* STALL handshake sent */
1092#define DATAEND 0x8 /* Data end indicator */
1093#define SETUPEND 0x10 /* Setup end */
1094#define SENDSTALL 0x20 /* Send STALL handshake */
1095#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1096#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1097#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1098#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1099#define SETUPPKT_H 0x8 /* send Setup token host mode */
1100#define ERROR_H 0x10 /* timeout error indicator host mode */
1101#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1102#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1103#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1104
1105/* Bit masks for USB_COUNT0 */
1106
1107#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1108
1109/* Bit masks for USB_NAKLIMIT0 */
1110
1111#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1112
1113/* Bit masks for USB_TX_MAX_PACKET */
1114
1115#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1116
1117/* Bit masks for USB_RX_MAX_PACKET */
1118
1119#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1120
1121/* Bit masks for USB_TXCSR */
1122
1123#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1124#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1125#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1126#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1127#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1128#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1129#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1130#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1131#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1132#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1133#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1134#define ISO_T 0x4000 /* enable Isochronous transfers */
1135#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1136#define ERROR_TH 0x4 /* error condition host mode */
1137#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1138#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1139
1140/* Bit masks for USB_TXCOUNT */
1141
1142#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1143
1144/* Bit masks for USB_RXCSR */
1145
1146#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1147#define FIFO_FULL_R 0x2 /* FIFO not empty */
1148#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1149#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1150#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1151#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1152#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1153#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1154#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1155#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1156#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1157#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1158#define ISO_R 0x4000 /* enable Isochronous transfers */
1159#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1160#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1161#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1162#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1163#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1164#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1165#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1166
1167/* Bit masks for USB_RXCOUNT */
1168
1169#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1170
1171/* Bit masks for USB_TXTYPE */
1172
1173#define TARGET_EP_NO_T 0xf /* EP number */
1174#define PROTOCOL_T 0xc /* transfer type */
1175
1176/* Bit masks for USB_TXINTERVAL */
1177
1178#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1179
1180/* Bit masks for USB_RXTYPE */
1181
1182#define TARGET_EP_NO_R 0xf /* EP number */
1183#define PROTOCOL_R 0xc /* transfer type */
1184
1185/* Bit masks for USB_RXINTERVAL */
1186
1187#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1188
1189/* Bit masks for USB_DMA_INTERRUPT */
1190
1191#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1192#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1193#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1194#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1195#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1196#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1197#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1198#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1199
1200/* Bit masks for USB_DMAxCONTROL */
1201
1202#define DMA_ENA 0x1 /* DMA enable */
1203#define DIRECTION 0x2 /* direction of DMA transfer */
1204#define MODE 0x4 /* DMA Bus error */
1205#define INT_ENA 0x8 /* Interrupt enable */
1206#define EPNUM 0xf0 /* EP number */
1207#define BUSERROR 0x100 /* DMA Bus error */
1208
1209/* Bit masks for USB_DMAxADDRHIGH */
1210
1211#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1212
1213/* Bit masks for USB_DMAxADDRLOW */
1214
1215#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1216
1217/* Bit masks for USB_DMAxCOUNTHIGH */
1218
1219#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1220
1221/* Bit masks for USB_DMAxCOUNTLOW */
1222
1223#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1224
1225/* Bit masks for HMDMAx_CONTROL */
1226
1227#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1228#define REP 0x2 /* Handshake MDMA Request Polarity */
1229#define UTE 0x8 /* Urgency Threshold Enable */
1230#define OIE 0x10 /* Overflow Interrupt Enable */
1231#define BDIE 0x20 /* Block Done Interrupt Enable */
1232#define MBDI 0x40 /* Mask Block Done Interrupt */
1233#define DRQ 0x300 /* Handshake MDMA Request Type */
1234#define RBC 0x1000 /* Force Reload of BCOUNT */
1235#define PS 0x2000 /* Pin Status */
1236#define OI 0x4000 /* Overflow Interrupt Generated */
1237#define BDI 0x8000 /* Block Done Interrupt Generated */
1238
1239/* ******************************************* */
1240/* MULTI BIT MACRO ENUMERATIONS */
1241/* ******************************************* */
1242
1243
1244#endif /* _DEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
deleted file mode 100644
index 1d7c96edb038..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ /dev/null
@@ -1,1627 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF548_H
32#define _DEF_BF548_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* SPORT0 Registers */
66
67#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
68#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
69#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
70#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
71#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
72#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
73#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
74#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
75#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
76#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
77#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
78#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
79#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
80#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
81#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
82#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
83#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
84#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
85#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
86#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
87#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
88#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
89
90/* EPPI0 Registers */
91
92#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
93#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
94#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
95#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
96#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
97#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
98#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
99#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
100#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
101#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
102#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
103#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
104#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
105#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
106
107/* UART2 Registers */
108
109#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
110#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
111#define UART2_GCTL 0xffc02108 /* Global Control Register */
112#define UART2_LCR 0xffc0210c /* Line Control Register */
113#define UART2_MCR 0xffc02110 /* Modem Control Register */
114#define UART2_LSR 0xffc02114 /* Line Status Register */
115#define UART2_MSR 0xffc02118 /* Modem Status Register */
116#define UART2_SCR 0xffc0211c /* Scratch Register */
117#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
118#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
119#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
120
121/* Two Wire Interface Registers (TWI1) */
122
123#define TWI1_REGBASE 0xffc02200
124#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
125#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
126#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
127#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
128#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
129#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
130#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
131#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
132#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
133#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
134#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
135#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
136#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
137#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
138#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
139#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
140
141/* SPI2 Registers */
142
143#define SPI2_REGBASE 0xffc02400
144#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
145#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
146#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
147#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
148#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
149#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
150#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
151
152/* CAN Controller 1 Config 1 Registers */
153
154#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
155#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
156#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
157#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
158#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
159#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
160#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
161#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
162#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
163#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
164#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
165#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
166#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
167
168/* CAN Controller 1 Config 2 Registers */
169
170#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
171#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
172#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
173#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
174#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
175#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
176#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
177#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
178#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
179#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
180#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
181#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
182#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
183
184/* CAN Controller 1 Clock/Interrupt/Counter Registers */
185
186#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
187#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
188#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
189#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
190#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
191#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
192#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
193#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
194#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
195#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
196#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
197#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
198#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
199#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
200#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
201#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
202
203/* CAN Controller 1 Mailbox Acceptance Registers */
204
205#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
206#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
207#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
208#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
209#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
210#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
211#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
212#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
213#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
214#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
215#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
216#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
217#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
218#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
219#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
220#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
221#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
222#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
223#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
224#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
225#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
226#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
227#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
228#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
229#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
230#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
231#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
232#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
233#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
234#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
235#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
236#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
237
238/* CAN Controller 1 Mailbox Acceptance Registers */
239
240#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
241#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
242#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
243#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
244#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
245#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
246#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
247#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
248#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
249#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
250#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
251#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
252#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
253#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
254#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
255#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
256#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
257#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
258#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
259#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
260#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
261#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
262#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
263#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
264#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
265#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
266#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
267#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
268#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
269#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
270#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
271#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
272
273/* CAN Controller 1 Mailbox Data Registers */
274
275#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
276#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
277#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
278#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
279#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
280#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
281#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
282#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
283#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
284#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
285#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
286#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
287#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
288#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
289#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
290#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
291#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
292#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
293#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
294#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
295#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
296#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
297#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
298#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
299#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
300#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
301#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
302#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
303#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
304#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
305#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
306#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
307#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
308#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
309#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
310#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
311#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
312#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
313#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
314#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
315#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
316#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
317#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
318#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
319#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
320#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
321#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
322#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
323#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
324#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
325#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
326#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
327#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
328#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
329#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
330#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
331#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
332#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
333#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
334#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
335#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
336#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
337#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
338#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
339#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
340#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
341#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
342#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
343#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
344#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
345#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
346#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
347#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
348#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
349#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
350#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
351#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
352#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
353#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
354#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
355#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
356#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
357#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
358#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
359#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
360#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
361#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
362#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
363#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
364#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
365#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
366#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
367#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
368#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
369#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
370#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
371#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
372#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
373#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
374#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
375#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
376#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
377#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
378#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
379#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
380#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
381#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
382#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
383#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
384#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
385#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
386#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
387#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
388#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
389#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
390#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
391#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
392#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
393#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
394#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
395#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
396#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
397#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
398#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
399#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
400#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
401#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
402#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
403
404/* CAN Controller 1 Mailbox Data Registers */
405
406#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
407#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
408#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
409#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
410#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
411#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
412#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
413#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
414#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
415#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
416#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
417#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
418#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
419#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
420#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
421#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
422#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
423#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
424#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
425#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
426#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
427#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
428#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
429#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
430#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
431#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
432#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
433#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
434#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
435#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
436#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
437#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
438#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
439#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
440#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
441#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
442#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
443#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
444#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
445#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
446#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
447#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
448#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
449#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
450#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
451#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
452#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
453#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
454#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
455#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
456#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
457#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
458#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
459#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
460#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
461#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
462#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
463#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
464#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
465#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
466#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
467#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
468#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
469#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
470#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
471#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
472#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
473#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
474#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
475#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
476#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
477#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
478#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
479#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
480#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
481#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
482#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
483#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
484#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
485#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
486#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
487#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
488#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
489#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
490#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
491#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
492#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
493#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
494#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
495#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
496#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
497#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
498#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
499#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
500#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
501#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
502#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
503#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
504#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
505#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
506#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
507#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
508#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
509#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
510#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
511#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
512#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
513#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
514#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
515#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
516#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
517#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
518#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
519#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
520#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
521#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
522#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
523#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
524#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
525#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
526#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
527#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
528#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
529#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
530#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
531#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
532#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
533#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
534
535/* ATAPI Registers */
536
537#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
538#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
539#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
540#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
541#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
542#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
543#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
544#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
545#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
546#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
547#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
548#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
549#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
550#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
551#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
552#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
553#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
554#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
555#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
556#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
557#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
558#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
559#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
560#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
561#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
562
563/* SDH Registers */
564
565#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
566#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
567#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
568#define SDH_COMMAND 0xffc0390c /* SDH Command */
569#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
570#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
571#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
572#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
573#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
574#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
575#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
576#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
577#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
578#define SDH_STATUS 0xffc03934 /* SDH Status */
579#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
580#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
581#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
582#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
583#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
584#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
585#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
586#define SDH_CFG 0xffc039c8 /* SDH Configuration */
587#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
588#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
589#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
590#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
591#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
592#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
593#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
594#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
595#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
596
597/* HOST Port Registers */
598
599#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
600#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
601#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
602
603/* USB Control Registers */
604
605#define USB_FADDR 0xffc03c00 /* Function address register */
606#define USB_POWER 0xffc03c04 /* Power management register */
607#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
608#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
609#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
610#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
611#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
612#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
613#define USB_FRAME 0xffc03c20 /* USB frame number */
614#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
615#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
616#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
617#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
618
619/* USB Packet Control Registers */
620
621#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
622#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
623#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
624#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
625#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
626#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
627#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
628#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
629#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
630#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
631#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
632#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
633#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
634
635/* USB Endpoint FIFO Registers */
636
637#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
638#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
639#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
640#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
641#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
642#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
643#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
644#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
645
646/* USB OTG Control Registers */
647
648#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
649#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
650#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
651
652/* USB Phy Control Registers */
653
654#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
655#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
656#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
657#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
658#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
659
660/* (APHY_CNTRL is for ADI usage only) */
661
662#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
663
664/* (APHY_CALIB is for ADI usage only) */
665
666#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
667#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
668
669/* (PHY_TEST is for ADI usage only) */
670
671#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
672#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
673#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
674
675/* USB Endpoint 0 Control Registers */
676
677#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
678#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
679#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
680#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
681#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
682#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
683#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
684#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
685#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
686
687/* USB Endpoint 1 Control Registers */
688
689#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
690#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
691#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
692#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
693#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
694#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
695#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
696#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
697#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
698#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
699
700/* USB Endpoint 2 Control Registers */
701
702#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
703#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
704#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
705#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
706#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
707#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
708#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
709#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
710#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
711#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
712
713/* USB Endpoint 3 Control Registers */
714
715#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
716#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
717#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
718#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
719#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
720#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
721#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
722#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
723#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
724#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
725
726/* USB Endpoint 4 Control Registers */
727
728#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
729#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
730#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
731#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
732#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
733#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
734#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
735#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
736#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
737#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
738
739/* USB Endpoint 5 Control Registers */
740
741#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
742#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
743#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
744#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
745#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
746#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
747#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
748#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
749#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
750#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
751
752/* USB Endpoint 6 Control Registers */
753
754#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
755#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
756#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
757#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
758#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
759#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
760#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
761#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
762#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
763#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
764
765/* USB Endpoint 7 Control Registers */
766
767#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
768#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
769#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
770#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
771#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
772#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
773#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
774#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
775#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
776#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
777#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
778#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
779
780/* USB Channel 0 Config Registers */
781
782#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
783#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
784#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
785#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
786#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
787
788/* USB Channel 1 Config Registers */
789
790#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
791#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
792#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
793#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
794#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
795
796/* USB Channel 2 Config Registers */
797
798#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
799#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
800#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
801#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
802#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
803
804/* USB Channel 3 Config Registers */
805
806#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
807#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
808#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
809#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
810#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
811
812/* USB Channel 4 Config Registers */
813
814#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
815#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
816#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
817#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
818#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
819
820/* USB Channel 5 Config Registers */
821
822#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
823#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
824#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
825#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
826#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
827
828/* USB Channel 6 Config Registers */
829
830#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
831#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
832#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
833#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
834#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
835
836/* USB Channel 7 Config Registers */
837
838#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
839#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
840#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
841#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
842#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
843
844/* Keypad Registers */
845
846#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
847#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
848#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
849#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
850#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
851#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
852
853/* Pixel Compositor (PIXC) Registers */
854
855#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
856#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
857#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
858#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
859#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
860#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
861#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
862#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
863#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
864#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
865#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
866#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
867#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
868#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
869#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
870#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
871#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
872#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
873#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
874
875/* Handshake MDMA 0 Registers */
876
877#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
878#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
879#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
880#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
881#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
882#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
883#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
884
885/* Handshake MDMA 1 Registers */
886
887#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
888#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
889#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
890#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
891#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
892#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
893#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
894
895
896/* ********************************************************** */
897/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
898/* and MULTI BIT READ MACROS */
899/* ********************************************************** */
900
901/* Bit masks for PIXC_CTL */
902
903#define PIXC_EN 0x1 /* Pixel Compositor Enable */
904#define OVR_A_EN 0x2 /* Overlay A Enable */
905#define OVR_B_EN 0x4 /* Overlay B Enable */
906#define IMG_FORM 0x8 /* Image Data Format */
907#define OVR_FORM 0x10 /* Overlay Data Format */
908#define OUT_FORM 0x20 /* Output Data Format */
909#define UDS_MOD 0x40 /* Resampling Mode */
910#define TC_EN 0x80 /* Transparent Color Enable */
911#define IMG_STAT 0x300 /* Image FIFO Status */
912#define OVR_STAT 0xc00 /* Overlay FIFO Status */
913#define WM_LVL 0x3000 /* FIFO Watermark Level */
914
915/* Bit masks for PIXC_AHSTART */
916
917#define A_HSTART 0xfff /* Horizontal Start Coordinates */
918
919/* Bit masks for PIXC_AHEND */
920
921#define A_HEND 0xfff /* Horizontal End Coordinates */
922
923/* Bit masks for PIXC_AVSTART */
924
925#define A_VSTART 0x3ff /* Vertical Start Coordinates */
926
927/* Bit masks for PIXC_AVEND */
928
929#define A_VEND 0x3ff /* Vertical End Coordinates */
930
931/* Bit masks for PIXC_ATRANSP */
932
933#define A_TRANSP 0xf /* Transparency Value */
934
935/* Bit masks for PIXC_BHSTART */
936
937#define B_HSTART 0xfff /* Horizontal Start Coordinates */
938
939/* Bit masks for PIXC_BHEND */
940
941#define B_HEND 0xfff /* Horizontal End Coordinates */
942
943/* Bit masks for PIXC_BVSTART */
944
945#define B_VSTART 0x3ff /* Vertical Start Coordinates */
946
947/* Bit masks for PIXC_BVEND */
948
949#define B_VEND 0x3ff /* Vertical End Coordinates */
950
951/* Bit masks for PIXC_BTRANSP */
952
953#define B_TRANSP 0xf /* Transparency Value */
954
955/* Bit masks for PIXC_INTRSTAT */
956
957#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
958#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
959#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
960#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
961
962/* Bit masks for PIXC_RYCON */
963
964#define A11 0x3ff /* A11 in the Coefficient Matrix */
965#define A12 0xffc00 /* A12 in the Coefficient Matrix */
966#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
967#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
968
969/* Bit masks for PIXC_GUCON */
970
971#define A21 0x3ff /* A21 in the Coefficient Matrix */
972#define A22 0xffc00 /* A22 in the Coefficient Matrix */
973#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
974#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
975
976/* Bit masks for PIXC_BVCON */
977
978#define A31 0x3ff /* A31 in the Coefficient Matrix */
979#define A32 0xffc00 /* A32 in the Coefficient Matrix */
980#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
981#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
982
983/* Bit masks for PIXC_CCBIAS */
984
985#define A14 0x3ff /* A14 in the Bias Vector */
986#define A24 0xffc00 /* A24 in the Bias Vector */
987#define A34 0x3ff00000 /* A34 in the Bias Vector */
988
989/* Bit masks for PIXC_TC */
990
991#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
992#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
993#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
994
995/* Bit masks for HOST_CONTROL */
996
997#define HOST_EN 0x1 /* Host Enable */
998#define HOST_END 0x2 /* Host Endianess */
999#define DATA_SIZE 0x4 /* Data Size */
1000#define HOST_RST 0x8 /* Host Reset */
1001#define HRDY_OVR 0x20 /* Host Ready Override */
1002#define INT_MODE 0x40 /* Interrupt Mode */
1003#define BT_EN 0x80 /* Bus Timeout Enable */
1004#define EHW 0x100 /* Enable Host Write */
1005#define EHR 0x200 /* Enable Host Read */
1006#define BDR 0x400 /* Burst DMA Requests */
1007
1008/* Bit masks for HOST_STATUS */
1009
1010#define DMA_READY 0x1 /* DMA Ready */
1011#define FIFOFULL 0x2 /* FIFO Full */
1012#define FIFOEMPTY 0x4 /* FIFO Empty */
1013#define DMA_COMPLETE 0x8 /* DMA Complete */
1014#define HSHK 0x10 /* Host Handshake */
1015#define HSTIMEOUT 0x20 /* Host Timeout */
1016#define HIRQ 0x40 /* Host Interrupt Request */
1017#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1018#define DMA_DIR 0x100 /* DMA Direction */
1019#define BTE 0x200 /* Bus Timeout Enabled */
1020
1021/* Bit masks for HOST_TIMEOUT */
1022
1023#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1024
1025/* Bit masks for KPAD_CTL */
1026
1027#define KPAD_EN 0x1 /* Keypad Enable */
1028#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
1029#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
1030#define KPAD_COLEN 0xe000 /* Column Enable Width */
1031
1032/* Bit masks for KPAD_PRESCALE */
1033
1034#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
1035
1036/* Bit masks for KPAD_MSEL */
1037
1038#define DBON_SCALE 0xff /* Debounce Scale Value */
1039#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
1040
1041/* Bit masks for KPAD_ROWCOL */
1042
1043#define KPAD_ROW 0xff /* Rows Pressed */
1044#define KPAD_COL 0xff00 /* Columns Pressed */
1045
1046/* Bit masks for KPAD_STAT */
1047
1048#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
1049#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
1050#define KPAD_PRESSED 0x8 /* Key press current status */
1051
1052/* Bit masks for KPAD_SOFTEVAL */
1053
1054#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
1055
1056/* Bit masks for SDH_COMMAND */
1057
1058#define CMD_IDX 0x3f /* Command Index */
1059#define CMD_RSP 0x40 /* Response */
1060#define CMD_L_RSP 0x80 /* Long Response */
1061#define CMD_INT_E 0x100 /* Command Interrupt */
1062#define CMD_PEND_E 0x200 /* Command Pending */
1063#define CMD_E 0x400 /* Command Enable */
1064
1065/* Bit masks for SDH_PWR_CTL */
1066
1067#define PWR_ON 0x3 /* Power On */
1068#if 0
1069#define TBD 0x3c /* TBD */
1070#endif
1071#define SD_CMD_OD 0x40 /* Open Drain Output */
1072#define ROD_CTL 0x80 /* Rod Control */
1073
1074/* Bit masks for SDH_CLK_CTL */
1075
1076#define CLKDIV 0xff /* MC_CLK Divisor */
1077#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
1078#define PWR_SV_E 0x200 /* Power Save Enable */
1079#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
1080#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
1081
1082/* Bit masks for SDH_RESP_CMD */
1083
1084#define RESP_CMD 0x3f /* Response Command */
1085
1086/* Bit masks for SDH_DATA_CTL */
1087
1088#define DTX_E 0x1 /* Data Transfer Enable */
1089#define DTX_DIR 0x2 /* Data Transfer Direction */
1090#define DTX_MODE 0x4 /* Data Transfer Mode */
1091#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
1092#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
1093
1094/* Bit masks for SDH_STATUS */
1095
1096#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1097#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1098#define CMD_TIME_OUT 0x4 /* CMD Time Out */
1099#define DAT_TIME_OUT 0x8 /* Data Time Out */
1100#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1101#define RX_OVERRUN 0x20 /* Receive Overrun */
1102#define CMD_RESP_END 0x40 /* CMD Response End */
1103#define CMD_SENT 0x80 /* CMD Sent */
1104#define DAT_END 0x100 /* Data End */
1105#define START_BIT_ERR 0x200 /* Start Bit Error */
1106#define DAT_BLK_END 0x400 /* Data Block End */
1107#define CMD_ACT 0x800 /* CMD Active */
1108#define TX_ACT 0x1000 /* Transmit Active */
1109#define RX_ACT 0x2000 /* Receive Active */
1110#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
1111#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
1112#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
1113#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
1114#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
1115#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
1116#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
1117#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
1118
1119/* Bit masks for SDH_STATUS_CLR */
1120
1121#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
1122#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
1123#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
1124#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
1125#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
1126#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
1127#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
1128#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
1129#define DAT_END_STAT 0x100 /* Data End Status */
1130#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
1131#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
1132
1133/* Bit masks for SDH_MASK0 */
1134
1135#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
1136#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
1137#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
1138#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
1139#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
1140#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
1141#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
1142#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
1143#define DAT_END_MASK 0x100 /* Data End Mask */
1144#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
1145#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
1146#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
1147#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
1148#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
1149#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
1150#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
1151#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
1152#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
1153#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
1154#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
1155#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
1156#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
1157
1158/* Bit masks for SDH_FIFO_CNT */
1159
1160#define FIFO_COUNT 0x7fff /* FIFO Count */
1161
1162/* Bit masks for SDH_E_STATUS */
1163
1164#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
1165#define SD_CARD_DET 0x10 /* SD Card Detect */
1166
1167/* Bit masks for SDH_E_MASK */
1168
1169#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
1170#define SCD_MSK 0x40 /* Mask Card Detect */
1171
1172/* Bit masks for SDH_CFG */
1173
1174#define CLKS_EN 0x1 /* Clocks Enable */
1175#define SD4E 0x4 /* SDIO 4-Bit Enable */
1176#define MWE 0x8 /* Moving Window Enable */
1177#define SD_RST 0x10 /* SDMMC Reset */
1178#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
1179#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
1180#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
1181
1182/* Bit masks for SDH_RD_WAIT_EN */
1183
1184#define RWR 0x1 /* Read Wait Request */
1185
1186/* Bit masks for ATAPI_CONTROL */
1187
1188#define PIO_START 0x1 /* Start PIO/Reg Op */
1189#define MULTI_START 0x2 /* Start Multi-DMA Op */
1190#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
1191#define XFER_DIR 0x8 /* Transfer Direction */
1192#define IORDY_EN 0x10 /* IORDY Enable */
1193#define FIFO_FLUSH 0x20 /* Flush FIFOs */
1194#define SOFT_RST 0x40 /* Soft Reset */
1195#define DEV_RST 0x80 /* Device Reset */
1196#define TFRCNT_RST 0x100 /* Trans Count Reset */
1197#define END_ON_TERM 0x200 /* End/Terminate Select */
1198#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
1199#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
1200
1201/* Bit masks for ATAPI_STATUS */
1202
1203#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
1204#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
1205#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
1206#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
1207
1208/* Bit masks for ATAPI_DEV_ADDR */
1209
1210#define DEV_ADDR 0x1f /* Device Address */
1211
1212/* Bit masks for ATAPI_INT_MASK */
1213
1214#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
1215#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
1216#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
1217#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
1218#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
1219#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
1220#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
1221#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
1222#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
1223
1224/* Bit masks for ATAPI_INT_STATUS */
1225
1226#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
1227#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
1228#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
1229#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
1230#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
1231#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
1232#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
1233#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
1234#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
1235
1236/* Bit masks for ATAPI_LINE_STATUS */
1237
1238#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
1239#define ATAPI_DASP 0x2 /* Device dasp to host line status */
1240#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
1241#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
1242#define ATAPI_ADDR 0x70 /* ATAPI address line status */
1243#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
1244#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
1245#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
1246#define ATAPI_DIORN 0x400 /* ATAPI read line status */
1247#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
1248
1249/* Bit masks for ATAPI_SM_STATE */
1250
1251#define PIO_CSTATE 0xf /* PIO mode state machine current state */
1252#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
1253#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
1254#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
1255
1256/* Bit masks for ATAPI_TERMINATE */
1257
1258#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
1259
1260/* Bit masks for ATAPI_REG_TIM_0 */
1261
1262#define T2_REG 0xff /* End of cycle time for register access transfers */
1263#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
1264
1265/* Bit masks for ATAPI_PIO_TIM_0 */
1266
1267#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
1268#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
1269#define T4_REG 0xf000 /* DIOW data hold */
1270
1271/* Bit masks for ATAPI_PIO_TIM_1 */
1272
1273#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
1274
1275/* Bit masks for ATAPI_MULTI_TIM_0 */
1276
1277#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
1278#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
1279
1280/* Bit masks for ATAPI_MULTI_TIM_1 */
1281
1282#define TKW 0xff /* Selects DIOW negated pulsewidth */
1283#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
1284
1285/* Bit masks for ATAPI_MULTI_TIM_2 */
1286
1287#define TH 0xff /* Selects DIOW data hold */
1288#define TEOC 0xff00 /* Selects end of cycle for DMA */
1289
1290/* Bit masks for ATAPI_ULTRA_TIM_0 */
1291
1292#define TACK 0xff /* Selects setup and hold times for TACK */
1293#define TENV 0xff00 /* Selects envelope time */
1294
1295/* Bit masks for ATAPI_ULTRA_TIM_1 */
1296
1297#define TDVS 0xff /* Selects data valid setup time */
1298#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
1299
1300/* Bit masks for ATAPI_ULTRA_TIM_2 */
1301
1302#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
1303#define TMLI 0xff00 /* Selects interlock time */
1304
1305/* Bit masks for ATAPI_ULTRA_TIM_3 */
1306
1307#define TZAH 0xff /* Selects minimum delay required for output */
1308#define READY_PAUSE 0xff00 /* Selects ready to pause */
1309
1310/* Bit masks for TIMER_ENABLE1 */
1311
1312#define TIMEN8 0x1 /* Timer 8 Enable */
1313#define TIMEN9 0x2 /* Timer 9 Enable */
1314#define TIMEN10 0x4 /* Timer 10 Enable */
1315
1316/* Bit masks for TIMER_DISABLE1 */
1317
1318#define TIMDIS8 0x1 /* Timer 8 Disable */
1319#define TIMDIS9 0x2 /* Timer 9 Disable */
1320#define TIMDIS10 0x4 /* Timer 10 Disable */
1321
1322/* Bit masks for TIMER_STATUS1 */
1323
1324#define TIMIL8 0x1 /* Timer 8 Interrupt */
1325#define TIMIL9 0x2 /* Timer 9 Interrupt */
1326#define TIMIL10 0x4 /* Timer 10 Interrupt */
1327#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
1328#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
1329#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
1330#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
1331#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
1332#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
1333
1334/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1335
1336/* Bit masks for USB_FADDR */
1337
1338#define FUNCTION_ADDRESS 0x7f /* Function address */
1339
1340/* Bit masks for USB_POWER */
1341
1342#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
1343#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
1344#define RESUME_MODE 0x4 /* DMA Mode */
1345#define RESET 0x8 /* Reset indicator */
1346#define HS_MODE 0x10 /* High Speed mode indicator */
1347#define HS_ENABLE 0x20 /* high Speed Enable */
1348#define SOFT_CONN 0x40 /* Soft connect */
1349#define ISO_UPDATE 0x80 /* Isochronous update */
1350
1351/* Bit masks for USB_INTRTX */
1352
1353#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
1354#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
1355#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
1356#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
1357#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
1358#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
1359#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
1360#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
1361
1362/* Bit masks for USB_INTRRX */
1363
1364#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
1365#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
1366#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
1367#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
1368#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
1369#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
1370#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
1371
1372/* Bit masks for USB_INTRTXE */
1373
1374#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
1375#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
1376#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
1377#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
1378#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
1379#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
1380#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
1381#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
1382
1383/* Bit masks for USB_INTRRXE */
1384
1385#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1386#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1387#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1388#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1389#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1390#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1391#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1392
1393/* Bit masks for USB_INTRUSB */
1394
1395#define SUSPEND_B 0x1 /* Suspend indicator */
1396#define RESUME_B 0x2 /* Resume indicator */
1397#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1398#define SOF_B 0x8 /* Start of frame */
1399#define CONN_B 0x10 /* Connection indicator */
1400#define DISCON_B 0x20 /* Disconnect indicator */
1401#define SESSION_REQ_B 0x40 /* Session Request */
1402#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1403
1404/* Bit masks for USB_INTRUSBE */
1405
1406#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1407#define RESUME_BE 0x2 /* Resume indicator int enable */
1408#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1409#define SOF_BE 0x8 /* Start of frame int enable */
1410#define CONN_BE 0x10 /* Connection indicator int enable */
1411#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1412#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1413#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1414
1415/* Bit masks for USB_FRAME */
1416
1417#define FRAME_NUMBER 0x7ff /* Frame number */
1418
1419/* Bit masks for USB_INDEX */
1420
1421#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1422
1423/* Bit masks for USB_GLOBAL_CTL */
1424
1425#define GLOBAL_ENA 0x1 /* enables USB module */
1426#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1427#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1428#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1429#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1430#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1431#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1432#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1433#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1434#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1435#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1436#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1437#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1438#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1439#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1440
1441/* Bit masks for USB_OTG_DEV_CTL */
1442
1443#define SESSION 0x1 /* session indicator */
1444#define HOST_REQ 0x2 /* Host negotiation request */
1445#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1446#define VBUS0 0x8 /* Vbus level indicator[0] */
1447#define VBUS1 0x10 /* Vbus level indicator[1] */
1448#define LSDEV 0x20 /* Low-speed indicator */
1449#define FSDEV 0x40 /* Full or High-speed indicator */
1450#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1451
1452/* Bit masks for USB_OTG_VBUS_IRQ */
1453
1454#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1455#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1456#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1457#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1458#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1459#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1460
1461/* Bit masks for USB_OTG_VBUS_MASK */
1462
1463#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1464#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1465#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1466#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1467#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1468#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1469
1470/* Bit masks for USB_CSR0 */
1471
1472#define RXPKTRDY 0x1 /* data packet receive indicator */
1473#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1474#define STALL_SENT 0x4 /* STALL handshake sent */
1475#define DATAEND 0x8 /* Data end indicator */
1476#define SETUPEND 0x10 /* Setup end */
1477#define SENDSTALL 0x20 /* Send STALL handshake */
1478#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1479#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1480#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1481#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1482#define SETUPPKT_H 0x8 /* send Setup token host mode */
1483#define ERROR_H 0x10 /* timeout error indicator host mode */
1484#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1485#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1486#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1487
1488/* Bit masks for USB_COUNT0 */
1489
1490#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1491
1492/* Bit masks for USB_NAKLIMIT0 */
1493
1494#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1495
1496/* Bit masks for USB_TX_MAX_PACKET */
1497
1498#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1499
1500/* Bit masks for USB_RX_MAX_PACKET */
1501
1502#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1503
1504/* Bit masks for USB_TXCSR */
1505
1506#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1507#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1508#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1509#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1510#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1511#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1512#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1513#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1514#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1515#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1516#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1517#define ISO_T 0x4000 /* enable Isochronous transfers */
1518#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1519#define ERROR_TH 0x4 /* error condition host mode */
1520#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1521#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1522
1523/* Bit masks for USB_TXCOUNT */
1524
1525#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1526
1527/* Bit masks for USB_RXCSR */
1528
1529#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1530#define FIFO_FULL_R 0x2 /* FIFO not empty */
1531#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1532#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1533#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1534#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1535#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1536#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1537#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1538#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1539#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1540#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1541#define ISO_R 0x4000 /* enable Isochronous transfers */
1542#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1543#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1544#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1545#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1546#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1547#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1548#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1549
1550/* Bit masks for USB_RXCOUNT */
1551
1552#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1553
1554/* Bit masks for USB_TXTYPE */
1555
1556#define TARGET_EP_NO_T 0xf /* EP number */
1557#define PROTOCOL_T 0xc /* transfer type */
1558
1559/* Bit masks for USB_TXINTERVAL */
1560
1561#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1562
1563/* Bit masks for USB_RXTYPE */
1564
1565#define TARGET_EP_NO_R 0xf /* EP number */
1566#define PROTOCOL_R 0xc /* transfer type */
1567
1568/* Bit masks for USB_RXINTERVAL */
1569
1570#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1571
1572/* Bit masks for USB_DMA_INTERRUPT */
1573
1574#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1575#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1576#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1577#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1578#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1579#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1580#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1581#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1582
1583/* Bit masks for USB_DMAxCONTROL */
1584
1585#define DMA_ENA 0x1 /* DMA enable */
1586#define DIRECTION 0x2 /* direction of DMA transfer */
1587#define MODE 0x4 /* DMA Bus error */
1588#define INT_ENA 0x8 /* Interrupt enable */
1589#define EPNUM 0xf0 /* EP number */
1590#define BUSERROR 0x100 /* DMA Bus error */
1591
1592/* Bit masks for USB_DMAxADDRHIGH */
1593
1594#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1595
1596/* Bit masks for USB_DMAxADDRLOW */
1597
1598#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1599
1600/* Bit masks for USB_DMAxCOUNTHIGH */
1601
1602#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1603
1604/* Bit masks for USB_DMAxCOUNTLOW */
1605
1606#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1607
1608/* Bit masks for HMDMAx_CONTROL */
1609
1610#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1611#define REP 0x2 /* Handshake MDMA Request Polarity */
1612#define UTE 0x8 /* Urgency Threshold Enable */
1613#define OIE 0x10 /* Overflow Interrupt Enable */
1614#define BDIE 0x20 /* Block Done Interrupt Enable */
1615#define MBDI 0x40 /* Mask Block Done Interrupt */
1616#define DRQ 0x300 /* Handshake MDMA Request Type */
1617#define RBC 0x1000 /* Force Reload of BCOUNT */
1618#define PS 0x2000 /* Pin Status */
1619#define OI 0x4000 /* Overflow Interrupt Generated */
1620#define BDI 0x8000 /* Block Done Interrupt Generated */
1621
1622/* ******************************************* */
1623/* MULTI BIT MACRO ENUMERATIONS */
1624/* ******************************************* */
1625
1626
1627#endif /* _DEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
deleted file mode 100644
index fcb72b41e007..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ /dev/null
@@ -1,2737 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF549.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF549_H
32#define _DEF_BF549_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37
38/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
39
40/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
41#include "defBF54x_base.h"
42
43/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
44
45/* Timer Registers */
46
47#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
48#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
49#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
50#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
51#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
52#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
53#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
54#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
55#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
56#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
57#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
58#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
59
60/* Timer Group of 3 Registers */
61
62#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
63#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
64#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
65
66/* SPORT0 Registers */
67
68#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
69#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
70#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
71#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
72#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
73#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
74#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
75#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
76#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
77#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
78#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
79#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
80#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
81#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
82#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
83#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
84#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
85#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
86#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
87#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
88#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
89#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
90
91/* EPPI0 Registers */
92
93#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
94#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
95#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
96#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
97#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
98#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
99#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
100#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
101#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
102#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
103#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
104#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
105#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
106#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
107
108/* UART2 Registers */
109
110#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
111#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
112#define UART2_GCTL 0xffc02108 /* Global Control Register */
113#define UART2_LCR 0xffc0210c /* Line Control Register */
114#define UART2_MCR 0xffc02110 /* Modem Control Register */
115#define UART2_LSR 0xffc02114 /* Line Status Register */
116#define UART2_MSR 0xffc02118 /* Modem Status Register */
117#define UART2_SCR 0xffc0211c /* Scratch Register */
118#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
119#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
120#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
121
122/* Two Wire Interface Registers (TWI1) */
123
124#define TWI1_REGBASE 0xffc02200
125#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
126#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
127#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
128#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
129#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
130#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
131#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
132#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
133#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
134#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
135#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
136#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
137#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
138#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
139#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
140#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
141
142/* SPI2 Registers */
143
144#define SPI2_REGBASE 0xffc02400
145#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
146#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
147#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
148#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
149#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
150#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
151#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
152
153/* MXVR Registers */
154
155#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */
156#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */
157#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */
158#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */
159#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */
160#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */
161#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */
162#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */
163#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */
164#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */
165#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */
166#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */
167#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */
168#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */
169
170/* MXVR Allocation Table Registers */
171
172#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */
173#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */
174#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */
175#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */
176#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */
177#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */
178#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */
179#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */
180#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */
181#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */
182#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */
183#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */
184#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */
185#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */
186#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */
187
188/* MXVR Channel Assign Registers */
189
190#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
191#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */
192#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
193#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
194#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
195#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */
196#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
197#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
198
199/* MXVR DMA0 Registers */
200
201#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */
202#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
203#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */
204#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */
205#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */
206
207/* MXVR DMA1 Registers */
208
209#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */
210#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
211#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */
212#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */
213#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */
214
215/* MXVR DMA2 Registers */
216
217#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */
218#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
219#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */
220#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */
221#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
222
223/* MXVR DMA3 Registers */
224
225#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */
226#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
227#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */
228#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */
229#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
230
231/* MXVR DMA4 Registers */
232
233#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */
234#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
235#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */
236#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */
237#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */
238
239/* MXVR DMA5 Registers */
240
241#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */
242#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
243#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */
244#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */
245#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */
246
247/* MXVR DMA6 Registers */
248
249#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
250#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
251#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
252#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
253#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
254
255/* MXVR DMA7 Registers */
256
257#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */
258#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
259#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */
260#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */
261#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */
262
263/* MXVR Asynch Packet Registers */
264
265#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */
266#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
267#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */
268#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
269#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */
270
271/* MXVR Control Message Registers */
272
273#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */
274#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
275#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */
276#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
277#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */
278
279/* MXVR Remote Read Registers */
280
281#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
282#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
283
284/* MXVR Pattern Data Registers */
285
286#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */
287#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */
288#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */
289#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */
290
291/* MXVR Frame Counter Registers */
292
293#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */
294#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */
295
296/* MXVR Routing Table Registers */
297
298#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */
299#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */
300#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */
301#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */
302#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */
303#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */
304#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */
305#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */
306#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */
307#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */
308#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */
309#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */
310#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */
311#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */
312#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */
313
314/* MXVR Counter-Clock-Control Registers */
315
316#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */
317#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */
318#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */
319#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */
320#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
321#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
322
323/* CAN Controller 1 Config 1 Registers */
324
325#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
326#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
327#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
328#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
329#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
330#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
331#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
332#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
333#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
334#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
335#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
336#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
337#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
338
339/* CAN Controller 1 Config 2 Registers */
340
341#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
342#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
343#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
344#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
345#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
346#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
347#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
348#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
349#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
350#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
351#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
352#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
353#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
354
355/* CAN Controller 1 Clock/Interrupt/Counter Registers */
356
357#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
358#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
359#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
360#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
361#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
362#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
363#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
364#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
365#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
366#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
367#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
368#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
369#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
370#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
371#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
372#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
373
374/* CAN Controller 1 Mailbox Acceptance Registers */
375
376#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
377#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
378#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
379#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
380#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
381#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
382#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
383#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
384#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
385#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
386#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
387#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
388#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
389#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
390#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
391#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
392#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
393#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
394#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
395#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
396#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
397#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
398#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
399#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
400#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
401#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
402#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
403#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
404#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
405#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
406#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
407#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
408
409/* CAN Controller 1 Mailbox Acceptance Registers */
410
411#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
412#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
413#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
414#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
415#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
416#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
417#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
418#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
419#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
420#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
421#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
422#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
423#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
424#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
425#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
426#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
427#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
428#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
429#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
430#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
431#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
432#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
433#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
434#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
435#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
436#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
437#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
438#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
439#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
440#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
441#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
442#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
443
444/* CAN Controller 1 Mailbox Data Registers */
445
446#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
447#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
448#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
449#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
450#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
451#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
452#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
453#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
454#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
455#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
456#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
457#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
458#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
459#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
460#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
461#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
462#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
463#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
464#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
465#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
466#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
467#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
468#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
469#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
470#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
471#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
472#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
473#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
474#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
475#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
476#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
477#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
478#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
479#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
480#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
481#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
482#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
483#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
484#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
485#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
486#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
487#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
488#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
489#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
490#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
491#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
492#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
493#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
494#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
495#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
496#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
497#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
498#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
499#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
500#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
501#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
502#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
503#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
504#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
505#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
506#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
507#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
508#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
509#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
510#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
511#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
512#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
513#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
514#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
515#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
516#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
517#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
518#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
519#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
520#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
521#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
522#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
523#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
524#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
525#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
526#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
527#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
528#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
529#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
530#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
531#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
532#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
533#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
534#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
535#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
536#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
537#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
538#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
539#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
540#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
541#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
542#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
543#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
544#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
545#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
546#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
547#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
548#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
549#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
550#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
551#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
552#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
553#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
554#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
555#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
556#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
557#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
558#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
559#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
560#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
561#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
562#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
563#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
564#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
565#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
566#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
567#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
568#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
569#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
570#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
571#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
572#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
573#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
574
575/* CAN Controller 1 Mailbox Data Registers */
576
577#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
578#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
579#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
580#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
581#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
582#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
583#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
584#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
585#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
586#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
587#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
588#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
589#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
590#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
591#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
592#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
593#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
594#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
595#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
596#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
597#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
598#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
599#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
600#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
601#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
602#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
603#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
604#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
605#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
606#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
607#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
608#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
609#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
610#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
611#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
612#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
613#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
614#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
615#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
616#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
617#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
618#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
619#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
620#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
621#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
622#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
623#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
624#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
625#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
626#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
627#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
628#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
629#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
630#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
631#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
632#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
633#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
634#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
635#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
636#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
637#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
638#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
639#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
640#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
641#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
642#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
643#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
644#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
645#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
646#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
647#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
648#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
649#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
650#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
651#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
652#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
653#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
654#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
655#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
656#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
657#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
658#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
659#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
660#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
661#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
662#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
663#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
664#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
665#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
666#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
667#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
668#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
669#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
670#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
671#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
672#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
673#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
674#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
675#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
676#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
677#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
678#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
679#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
680#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
681#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
682#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
683#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
684#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
685#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
686#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
687#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
688#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
689#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
690#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
691#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
692#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
693#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
694#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
695#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
696#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
697#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
698#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
699#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
700#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
701#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
702#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
703#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
704#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
705
706/* ATAPI Registers */
707
708#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
709#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
710#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
711#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
712#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
713#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
714#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
715#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
716#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
717#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
718#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
719#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
720#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
721#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
722#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
723#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
724#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
725#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
726#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
727#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
728#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
729#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
730#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
731#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
732#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
733
734/* SDH Registers */
735
736#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
737#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
738#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
739#define SDH_COMMAND 0xffc0390c /* SDH Command */
740#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
741#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
742#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
743#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
744#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
745#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
746#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
747#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
748#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
749#define SDH_STATUS 0xffc03934 /* SDH Status */
750#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
751#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
752#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
753#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
754#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
755#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
756#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
757#define SDH_CFG 0xffc039c8 /* SDH Configuration */
758#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
759#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
760#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
761#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
762#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
763#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
764#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
765#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
766#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
767
768/* HOST Port Registers */
769
770#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
771#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
772#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
773
774/* USB Control Registers */
775
776#define USB_FADDR 0xffc03c00 /* Function address register */
777#define USB_POWER 0xffc03c04 /* Power management register */
778#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
779#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
780#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
781#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
782#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
783#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
784#define USB_FRAME 0xffc03c20 /* USB frame number */
785#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
786#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
787#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
788#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
789
790/* USB Packet Control Registers */
791
792#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
793#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
794#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
795#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
796#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
797#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
798#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
799#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
800#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
801#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
802#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
803#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
804#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
805
806/* USB Endpoint FIFO Registers */
807
808#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
809#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
810#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
811#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
812#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
813#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
814#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
815#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
816
817/* USB OTG Control Registers */
818
819#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
820#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
821#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
822
823/* USB Phy Control Registers */
824
825#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
826#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
827#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
828#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
829#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
830
831/* (APHY_CNTRL is for ADI usage only) */
832
833#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
834
835/* (APHY_CALIB is for ADI usage only) */
836
837#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
838#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
839
840/* (PHY_TEST is for ADI usage only) */
841
842#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
843#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
844#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
845
846/* USB Endpoint 0 Control Registers */
847
848#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
849#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
850#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
851#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
852#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
853#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
854#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
855#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
856#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
857
858/* USB Endpoint 1 Control Registers */
859
860#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
861#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
862#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
863#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
864#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
865#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
866#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
867#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
868#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
869#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
870
871/* USB Endpoint 2 Control Registers */
872
873#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
874#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
875#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
876#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
877#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
878#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
879#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
880#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
881#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
882#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
883
884/* USB Endpoint 3 Control Registers */
885
886#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
887#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
888#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
889#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
890#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
891#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
892#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
893#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
894#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
895#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
896
897/* USB Endpoint 4 Control Registers */
898
899#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
900#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
901#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
902#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
903#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
904#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
905#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
906#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
907#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
908#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
909
910/* USB Endpoint 5 Control Registers */
911
912#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
913#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
914#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
915#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
916#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
917#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
918#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
919#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
920#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
921#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
922
923/* USB Endpoint 6 Control Registers */
924
925#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
926#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
927#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
928#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
929#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
930#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
931#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
932#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
933#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
934#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
935
936/* USB Endpoint 7 Control Registers */
937
938#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
939#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
940#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
941#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
942#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
943#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
944#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
945#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
946#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
947#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
948#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
949#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
950
951/* USB Channel 0 Config Registers */
952
953#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
954#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
955#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
956#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
957#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
958
959/* USB Channel 1 Config Registers */
960
961#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
962#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
963#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
964#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
965#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
966
967/* USB Channel 2 Config Registers */
968
969#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
970#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
971#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
972#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
973#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
974
975/* USB Channel 3 Config Registers */
976
977#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
978#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
979#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
980#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
981#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
982
983/* USB Channel 4 Config Registers */
984
985#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
986#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
987#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
988#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
989#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
990
991/* USB Channel 5 Config Registers */
992
993#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
994#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
995#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
996#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
997#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
998
999/* USB Channel 6 Config Registers */
1000
1001#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
1002#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
1003#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
1004#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
1005#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
1006
1007/* USB Channel 7 Config Registers */
1008
1009#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
1010#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
1011#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
1012#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
1013#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
1014
1015/* Keypad Registers */
1016
1017#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
1018#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
1019#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
1020#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
1021#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
1022#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
1023
1024/* Pixel Compositor (PIXC) Registers */
1025
1026#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
1027#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
1028#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
1029#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
1030#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
1031#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
1032#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
1033#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
1034#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
1035#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
1036#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
1037#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
1038#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
1039#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
1040#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
1041#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
1042#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
1043#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
1044#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
1045
1046/* Handshake MDMA 0 Registers */
1047
1048#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
1049#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
1050#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
1051#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
1052#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
1053#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
1054#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
1055
1056/* Handshake MDMA 1 Registers */
1057
1058#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
1059#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
1060#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
1061#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
1062#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
1063#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
1064#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
1065
1066
1067/* ********************************************************** */
1068/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1069/* and MULTI BIT READ MACROS */
1070/* ********************************************************** */
1071
1072/* Bit masks for PIXC_CTL */
1073
1074#define PIXC_EN 0x1 /* Pixel Compositor Enable */
1075#define OVR_A_EN 0x2 /* Overlay A Enable */
1076#define OVR_B_EN 0x4 /* Overlay B Enable */
1077#define IMG_FORM 0x8 /* Image Data Format */
1078#define OVR_FORM 0x10 /* Overlay Data Format */
1079#define OUT_FORM 0x20 /* Output Data Format */
1080#define UDS_MOD 0x40 /* Resampling Mode */
1081#define TC_EN 0x80 /* Transparent Color Enable */
1082#define IMG_STAT 0x300 /* Image FIFO Status */
1083#define OVR_STAT 0xc00 /* Overlay FIFO Status */
1084#define WM_LVL 0x3000 /* FIFO Watermark Level */
1085
1086/* Bit masks for PIXC_AHSTART */
1087
1088#define A_HSTART 0xfff /* Horizontal Start Coordinates */
1089
1090/* Bit masks for PIXC_AHEND */
1091
1092#define A_HEND 0xfff /* Horizontal End Coordinates */
1093
1094/* Bit masks for PIXC_AVSTART */
1095
1096#define A_VSTART 0x3ff /* Vertical Start Coordinates */
1097
1098/* Bit masks for PIXC_AVEND */
1099
1100#define A_VEND 0x3ff /* Vertical End Coordinates */
1101
1102/* Bit masks for PIXC_ATRANSP */
1103
1104#define A_TRANSP 0xf /* Transparency Value */
1105
1106/* Bit masks for PIXC_BHSTART */
1107
1108#define B_HSTART 0xfff /* Horizontal Start Coordinates */
1109
1110/* Bit masks for PIXC_BHEND */
1111
1112#define B_HEND 0xfff /* Horizontal End Coordinates */
1113
1114/* Bit masks for PIXC_BVSTART */
1115
1116#define B_VSTART 0x3ff /* Vertical Start Coordinates */
1117
1118/* Bit masks for PIXC_BVEND */
1119
1120#define B_VEND 0x3ff /* Vertical End Coordinates */
1121
1122/* Bit masks for PIXC_BTRANSP */
1123
1124#define B_TRANSP 0xf /* Transparency Value */
1125
1126/* Bit masks for PIXC_INTRSTAT */
1127
1128#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
1129#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
1130#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
1131#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
1132
1133/* Bit masks for PIXC_RYCON */
1134
1135#define A11 0x3ff /* A11 in the Coefficient Matrix */
1136#define A12 0xffc00 /* A12 in the Coefficient Matrix */
1137#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
1138#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
1139
1140/* Bit masks for PIXC_GUCON */
1141
1142#define A21 0x3ff /* A21 in the Coefficient Matrix */
1143#define A22 0xffc00 /* A22 in the Coefficient Matrix */
1144#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
1145#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
1146
1147/* Bit masks for PIXC_BVCON */
1148
1149#define A31 0x3ff /* A31 in the Coefficient Matrix */
1150#define A32 0xffc00 /* A32 in the Coefficient Matrix */
1151#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
1152#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
1153
1154/* Bit masks for PIXC_CCBIAS */
1155
1156#define A14 0x3ff /* A14 in the Bias Vector */
1157#define A24 0xffc00 /* A24 in the Bias Vector */
1158#define A34 0x3ff00000 /* A34 in the Bias Vector */
1159
1160/* Bit masks for PIXC_TC */
1161
1162#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
1163#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
1164#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
1165
1166/* Bit masks for HOST_CONTROL */
1167
1168#define HOST_EN 0x1 /* Host Enable */
1169#define HOST_END 0x2 /* Host Endianess */
1170#define DATA_SIZE 0x4 /* Data Size */
1171#define HOST_RST 0x8 /* Host Reset */
1172#define HRDY_OVR 0x20 /* Host Ready Override */
1173#define INT_MODE 0x40 /* Interrupt Mode */
1174#define BT_EN 0x80 /* Bus Timeout Enable */
1175#define EHW 0x100 /* Enable Host Write */
1176#define EHR 0x200 /* Enable Host Read */
1177#define BDR 0x400 /* Burst DMA Requests */
1178
1179/* Bit masks for HOST_STATUS */
1180
1181#define DMA_READY 0x1 /* DMA Ready */
1182#define FIFOFULL 0x2 /* FIFO Full */
1183#define FIFOEMPTY 0x4 /* FIFO Empty */
1184#define DMA_COMPLETE 0x8 /* DMA Complete */
1185#define HSHK 0x10 /* Host Handshake */
1186#define TIMEOUT 0x20 /* Host Timeout */
1187#define HIRQ 0x40 /* Host Interrupt Request */
1188#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1189#define DMA_DIR 0x100 /* DMA Direction */
1190#define BTE 0x200 /* Bus Timeout Enabled */
1191
1192/* Bit masks for HOST_TIMEOUT */
1193
1194#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1195
1196/* Bit masks for MXVR_CONFIG */
1197
1198#define MXVREN 0x1 /* MXVR Enable */
1199#define MMSM 0x2 /* MXVR Master/Slave Mode Select */
1200#define ACTIVE 0x4 /* Active Mode */
1201#define SDELAY 0x8 /* Synchronous Data Delay */
1202#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */
1203#define RWRRXEN 0x20 /* Remote Write Receive Enable */
1204#define MTXEN 0x40 /* MXVR Transmit Data Enable */
1205#define MTXONB 0x80 /* MXVR Phy Transmitter On */
1206#define EPARITY 0x100 /* Even Parity Select */
1207#define MSB 0x1e00 /* Master Synchronous Boundary */
1208#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */
1209#define WAKEUP 0x4000 /* Wake-Up */
1210#define LMECH 0x8000 /* Lock Mechanism Select */
1211
1212/* Bit masks for MXVR_STATE_0 */
1213
1214#define NACT 0x1 /* Network Activity */
1215#define SBLOCK 0x2 /* Super Block Lock */
1216#define FMPLLST 0xc /* Frequency Multiply PLL SM State */
1217#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */
1218#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */
1219#define APARB 0x200 /* Asynchronous Packet Arbitrating */
1220#define APTX 0x400 /* Asynchronous Packet Transmitting */
1221#define APRX 0x800 /* Receiving Asynchronous Packet */
1222#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */
1223#define CMARB 0x2000 /* Control Message Arbitrating */
1224#define CMTX 0x4000 /* Control Message Transmitting */
1225#define CMRX 0x8000 /* Receiving Control Message */
1226#define MRXONB 0x10000 /* MRXONB Pin State */
1227#define RGSIP 0x20000 /* Remote Get Source In Progress */
1228#define DALIP 0x40000 /* Resource Deallocate In Progress */
1229#define ALIP 0x80000 /* Resource Allocate In Progress */
1230#define RRDIP 0x100000 /* Remote Read In Progress */
1231#define RWRIP 0x200000 /* Remote Write In Progress */
1232#define FLOCK 0x400000 /* Frame Lock */
1233#define BLOCK 0x800000 /* Block Lock */
1234#define RSB 0xf000000 /* Received Synchronous Boundary */
1235#define DERRNUM 0xf0000000 /* DMA Error Channel Number */
1236
1237/* Bit masks for MXVR_STATE_1 */
1238
1239#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */
1240#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */
1241#define APCONT 0x100 /* Asynchronous Packet Continuation */
1242#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */
1243#define DMAACTIVE0 0x10000 /* DMA0 Active */
1244#define DMAACTIVE1 0x20000 /* DMA1 Active */
1245#define DMAACTIVE2 0x40000 /* DMA2 Active */
1246#define DMAACTIVE3 0x80000 /* DMA3 Active */
1247#define DMAACTIVE4 0x100000 /* DMA4 Active */
1248#define DMAACTIVE5 0x200000 /* DMA5 Active */
1249#define DMAACTIVE6 0x400000 /* DMA6 Active */
1250#define DMAACTIVE7 0x800000 /* DMA7 Active */
1251#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */
1252#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */
1253#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */
1254#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */
1255#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */
1256#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */
1257#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */
1258#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */
1259
1260/* Bit masks for MXVR_INT_STAT_0 */
1261
1262#define NI2A 0x1 /* Network Inactive to Active */
1263#define NA2I 0x2 /* Network Active to Inactive */
1264#define SBU2L 0x4 /* Super Block Unlock to Lock */
1265#define SBL2U 0x8 /* Super Block Lock to Unlock */
1266#define PRU 0x10 /* Position Register Updated */
1267#define MPRU 0x20 /* Maximum Position Register Updated */
1268#define DRU 0x40 /* Delay Register Updated */
1269#define MDRU 0x80 /* Maximum Delay Register Updated */
1270#define SBU 0x100 /* Synchronous Boundary Updated */
1271#define ATU 0x200 /* Allocation Table Updated */
1272#define FCZ0 0x400 /* Frame Counter 0 Zero */
1273#define FCZ1 0x800 /* Frame Counter 1 Zero */
1274#define PERR 0x1000 /* Parity Error */
1275#define MH2L 0x2000 /* MRXONB High to Low */
1276#define ML2H 0x4000 /* MRXONB Low to High */
1277#define WUP 0x8000 /* Wake-Up Preamble Received */
1278#define FU2L 0x10000 /* Frame Unlock to Lock */
1279#define FL2U 0x20000 /* Frame Lock to Unlock */
1280#define BU2L 0x40000 /* Block Unlock to Lock */
1281#define BL2U 0x80000 /* Block Lock to Unlock */
1282#define OBERR 0x100000 /* DMA Out of Bounds Error */
1283#define PFL 0x200000 /* PLL Frequency Locked */
1284#define SCZ 0x400000 /* System Clock Counter Zero */
1285#define FERR 0x800000 /* FIFO Error */
1286#define CMR 0x1000000 /* Control Message Received */
1287#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */
1288#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */
1289#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */
1290#define RWRC 0x10000000 /* Remote Write Control Message Completed */
1291#define BCZ 0x20000000 /* Block Counter Zero */
1292#define BMERR 0x40000000 /* Biphase Mark Coding Error */
1293#define DERR 0x80000000 /* DMA Error */
1294
1295/* Bit masks for MXVR_INT_STAT_1 */
1296
1297#define HDONE0 0x1 /* DMA0 Half Done */
1298#define DONE0 0x2 /* DMA0 Done */
1299#define APR 0x4 /* Asynchronous Packet Received */
1300#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */
1301#define HDONE1 0x10 /* DMA1 Half Done */
1302#define DONE1 0x20 /* DMA1 Done */
1303#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */
1304#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
1305#define HDONE2 0x100 /* DMA2 Half Done */
1306#define DONE2 0x200 /* DMA2 Done */
1307#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */
1308#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */
1309#define HDONE3 0x1000 /* DMA3 Half Done */
1310#define DONE3 0x2000 /* DMA3 Done */
1311#define HDONE4 0x10000 /* DMA4 Half Done */
1312#define DONE4 0x20000 /* DMA4 Done */
1313#define HDONE5 0x100000 /* DMA5 Half Done */
1314#define DONE5 0x200000 /* DMA5 Done */
1315#define HDONE6 0x1000000 /* DMA6 Half Done */
1316#define DONE6 0x2000000 /* DMA6 Done */
1317#define HDONE7 0x10000000 /* DMA7 Half Done */
1318#define DONE7 0x20000000 /* DMA7 Done */
1319
1320/* Bit masks for MXVR_INT_EN_0 */
1321
1322#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */
1323#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */
1324#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */
1325#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */
1326#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */
1327#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */
1328#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */
1329#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */
1330#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */
1331#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */
1332#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */
1333#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */
1334#define PERREN 0x1000 /* Parity Error Interrupt Enable */
1335#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */
1336#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */
1337#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */
1338#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */
1339#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */
1340#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */
1341#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */
1342#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */
1343#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */
1344#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */
1345#define FERREN 0x800000 /* FIFO Error Interrupt Enable */
1346#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */
1347#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */
1348#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
1349#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
1350#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
1351#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */
1352#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
1353#define DERREN 0x80000000 /* DMA Error Interrupt Enable */
1354
1355/* Bit masks for MXVR_INT_EN_1 */
1356
1357#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */
1358#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */
1359#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */
1360#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
1361#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */
1362#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */
1363#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
1364#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
1365#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */
1366#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */
1367#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */
1368#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */
1369#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */
1370#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */
1371#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */
1372#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */
1373#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */
1374#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */
1375#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */
1376#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */
1377#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */
1378#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */
1379
1380/* Bit masks for MXVR_POSITION */
1381
1382#define POSITION 0x3f /* Node Position */
1383#define PVALID 0x8000 /* Node Position Valid */
1384
1385/* Bit masks for MXVR_MAX_POSITION */
1386
1387#define MPOSITION 0x3f /* Maximum Node Position */
1388#define MPVALID 0x8000 /* Maximum Node Position Valid */
1389
1390/* Bit masks for MXVR_DELAY */
1391
1392#define DELAY 0x3f /* Node Frame Delay */
1393#define DVALID 0x8000 /* Node Frame Delay Valid */
1394
1395/* Bit masks for MXVR_MAX_DELAY */
1396
1397#define MDELAY 0x3f /* Maximum Node Frame Delay */
1398#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */
1399
1400/* Bit masks for MXVR_LADDR */
1401
1402#define LADDR 0xffff /* Logical Address */
1403#define LVALID 0x80000000 /* Logical Address Valid */
1404
1405/* Bit masks for MXVR_GADDR */
1406
1407#define GADDRL 0xff /* Group Address Lower Byte */
1408#define GVALID 0x8000 /* Group Address Valid */
1409
1410/* Bit masks for MXVR_AADDR */
1411
1412#define AADDR 0xffff /* Alternate Address */
1413#define AVALID 0x80000000 /* Alternate Address Valid */
1414
1415/* Bit masks for MXVR_ALLOC_0 */
1416
1417#define CL0 0x7f /* Channel 0 Connection Label */
1418#define CIU0 0x80 /* Channel 0 In Use */
1419#define CL1 0x7f00 /* Channel 0 Connection Label */
1420#define CIU1 0x8000 /* Channel 0 In Use */
1421#define CL2 0x7f0000 /* Channel 0 Connection Label */
1422#define CIU2 0x800000 /* Channel 0 In Use */
1423#define CL3 0x7f000000 /* Channel 0 Connection Label */
1424#define CIU3 0x80000000 /* Channel 0 In Use */
1425
1426/* Bit masks for MXVR_ALLOC_1 */
1427
1428#define CL4 0x7f /* Channel 4 Connection Label */
1429#define CIU4 0x80 /* Channel 4 In Use */
1430#define CL5 0x7f00 /* Channel 5 Connection Label */
1431#define CIU5 0x8000 /* Channel 5 In Use */
1432#define CL6 0x7f0000 /* Channel 6 Connection Label */
1433#define CIU6 0x800000 /* Channel 6 In Use */
1434#define CL7 0x7f000000 /* Channel 7 Connection Label */
1435#define CIU7 0x80000000 /* Channel 7 In Use */
1436
1437/* Bit masks for MXVR_ALLOC_2 */
1438
1439#define CL8 0x7f /* Channel 8 Connection Label */
1440#define CIU8 0x80 /* Channel 8 In Use */
1441#define CL9 0x7f00 /* Channel 9 Connection Label */
1442#define CIU9 0x8000 /* Channel 9 In Use */
1443#define CL10 0x7f0000 /* Channel 10 Connection Label */
1444#define CIU10 0x800000 /* Channel 10 In Use */
1445#define CL11 0x7f000000 /* Channel 11 Connection Label */
1446#define CIU11 0x80000000 /* Channel 11 In Use */
1447
1448/* Bit masks for MXVR_ALLOC_3 */
1449
1450#define CL12 0x7f /* Channel 12 Connection Label */
1451#define CIU12 0x80 /* Channel 12 In Use */
1452#define CL13 0x7f00 /* Channel 13 Connection Label */
1453#define CIU13 0x8000 /* Channel 13 In Use */
1454#define CL14 0x7f0000 /* Channel 14 Connection Label */
1455#define CIU14 0x800000 /* Channel 14 In Use */
1456#define CL15 0x7f000000 /* Channel 15 Connection Label */
1457#define CIU15 0x80000000 /* Channel 15 In Use */
1458
1459/* Bit masks for MXVR_ALLOC_4 */
1460
1461#define CL16 0x7f /* Channel 16 Connection Label */
1462#define CIU16 0x80 /* Channel 16 In Use */
1463#define CL17 0x7f00 /* Channel 17 Connection Label */
1464#define CIU17 0x8000 /* Channel 17 In Use */
1465#define CL18 0x7f0000 /* Channel 18 Connection Label */
1466#define CIU18 0x800000 /* Channel 18 In Use */
1467#define CL19 0x7f000000 /* Channel 19 Connection Label */
1468#define CIU19 0x80000000 /* Channel 19 In Use */
1469
1470/* Bit masks for MXVR_ALLOC_5 */
1471
1472#define CL20 0x7f /* Channel 20 Connection Label */
1473#define CIU20 0x80 /* Channel 20 In Use */
1474#define CL21 0x7f00 /* Channel 21 Connection Label */
1475#define CIU21 0x8000 /* Channel 21 In Use */
1476#define CL22 0x7f0000 /* Channel 22 Connection Label */
1477#define CIU22 0x800000 /* Channel 22 In Use */
1478#define CL23 0x7f000000 /* Channel 23 Connection Label */
1479#define CIU23 0x80000000 /* Channel 23 In Use */
1480
1481/* Bit masks for MXVR_ALLOC_6 */
1482
1483#define CL24 0x7f /* Channel 24 Connection Label */
1484#define CIU24 0x80 /* Channel 24 In Use */
1485#define CL25 0x7f00 /* Channel 25 Connection Label */
1486#define CIU25 0x8000 /* Channel 25 In Use */
1487#define CL26 0x7f0000 /* Channel 26 Connection Label */
1488#define CIU26 0x800000 /* Channel 26 In Use */
1489#define CL27 0x7f000000 /* Channel 27 Connection Label */
1490#define CIU27 0x80000000 /* Channel 27 In Use */
1491
1492/* Bit masks for MXVR_ALLOC_7 */
1493
1494#define CL28 0x7f /* Channel 28 Connection Label */
1495#define CIU28 0x80 /* Channel 28 In Use */
1496#define CL29 0x7f00 /* Channel 29 Connection Label */
1497#define CIU29 0x8000 /* Channel 29 In Use */
1498#define CL30 0x7f0000 /* Channel 30 Connection Label */
1499#define CIU30 0x800000 /* Channel 30 In Use */
1500#define CL31 0x7f000000 /* Channel 31 Connection Label */
1501#define CIU31 0x80000000 /* Channel 31 In Use */
1502
1503/* Bit masks for MXVR_ALLOC_8 */
1504
1505#define CL32 0x7f /* Channel 32 Connection Label */
1506#define CIU32 0x80 /* Channel 32 In Use */
1507#define CL33 0x7f00 /* Channel 33 Connection Label */
1508#define CIU33 0x8000 /* Channel 33 In Use */
1509#define CL34 0x7f0000 /* Channel 34 Connection Label */
1510#define CIU34 0x800000 /* Channel 34 In Use */
1511#define CL35 0x7f000000 /* Channel 35 Connection Label */
1512#define CIU35 0x80000000 /* Channel 35 In Use */
1513
1514/* Bit masks for MXVR_ALLOC_9 */
1515
1516#define CL36 0x7f /* Channel 36 Connection Label */
1517#define CIU36 0x80 /* Channel 36 In Use */
1518#define CL37 0x7f00 /* Channel 37 Connection Label */
1519#define CIU37 0x8000 /* Channel 37 In Use */
1520#define CL38 0x7f0000 /* Channel 38 Connection Label */
1521#define CIU38 0x800000 /* Channel 38 In Use */
1522#define CL39 0x7f000000 /* Channel 39 Connection Label */
1523#define CIU39 0x80000000 /* Channel 39 In Use */
1524
1525/* Bit masks for MXVR_ALLOC_10 */
1526
1527#define CL40 0x7f /* Channel 40 Connection Label */
1528#define CIU40 0x80 /* Channel 40 In Use */
1529#define CL41 0x7f00 /* Channel 41 Connection Label */
1530#define CIU41 0x8000 /* Channel 41 In Use */
1531#define CL42 0x7f0000 /* Channel 42 Connection Label */
1532#define CIU42 0x800000 /* Channel 42 In Use */
1533#define CL43 0x7f000000 /* Channel 43 Connection Label */
1534#define CIU43 0x80000000 /* Channel 43 In Use */
1535
1536/* Bit masks for MXVR_ALLOC_11 */
1537
1538#define CL44 0x7f /* Channel 44 Connection Label */
1539#define CIU44 0x80 /* Channel 44 In Use */
1540#define CL45 0x7f00 /* Channel 45 Connection Label */
1541#define CIU45 0x8000 /* Channel 45 In Use */
1542#define CL46 0x7f0000 /* Channel 46 Connection Label */
1543#define CIU46 0x800000 /* Channel 46 In Use */
1544#define CL47 0x7f000000 /* Channel 47 Connection Label */
1545#define CIU47 0x80000000 /* Channel 47 In Use */
1546
1547/* Bit masks for MXVR_ALLOC_12 */
1548
1549#define CL48 0x7f /* Channel 48 Connection Label */
1550#define CIU48 0x80 /* Channel 48 In Use */
1551#define CL49 0x7f00 /* Channel 49 Connection Label */
1552#define CIU49 0x8000 /* Channel 49 In Use */
1553#define CL50 0x7f0000 /* Channel 50 Connection Label */
1554#define CIU50 0x800000 /* Channel 50 In Use */
1555#define CL51 0x7f000000 /* Channel 51 Connection Label */
1556#define CIU51 0x80000000 /* Channel 51 In Use */
1557
1558/* Bit masks for MXVR_ALLOC_13 */
1559
1560#define CL52 0x7f /* Channel 52 Connection Label */
1561#define CIU52 0x80 /* Channel 52 In Use */
1562#define CL53 0x7f00 /* Channel 53 Connection Label */
1563#define CIU53 0x8000 /* Channel 53 In Use */
1564#define CL54 0x7f0000 /* Channel 54 Connection Label */
1565#define CIU54 0x800000 /* Channel 54 In Use */
1566#define CL55 0x7f000000 /* Channel 55 Connection Label */
1567#define CIU55 0x80000000 /* Channel 55 In Use */
1568
1569/* Bit masks for MXVR_ALLOC_14 */
1570
1571#define CL56 0x7f /* Channel 56 Connection Label */
1572#define CIU56 0x80 /* Channel 56 In Use */
1573#define CL57 0x7f00 /* Channel 57 Connection Label */
1574#define CIU57 0x8000 /* Channel 57 In Use */
1575#define CL58 0x7f0000 /* Channel 58 Connection Label */
1576#define CIU58 0x800000 /* Channel 58 In Use */
1577#define CL59 0x7f000000 /* Channel 59 Connection Label */
1578#define CIU59 0x80000000 /* Channel 59 In Use */
1579
1580/* MXVR_SYNC_LCHAN_0 Masks */
1581
1582#define LCHANPC0 0x0000000Flu
1583#define LCHANPC1 0x000000F0lu
1584#define LCHANPC2 0x00000F00lu
1585#define LCHANPC3 0x0000F000lu
1586#define LCHANPC4 0x000F0000lu
1587#define LCHANPC5 0x00F00000lu
1588#define LCHANPC6 0x0F000000lu
1589#define LCHANPC7 0xF0000000lu
1590
1591
1592/* MXVR_SYNC_LCHAN_1 Masks */
1593
1594#define LCHANPC8 0x0000000Flu
1595#define LCHANPC9 0x000000F0lu
1596#define LCHANPC10 0x00000F00lu
1597#define LCHANPC11 0x0000F000lu
1598#define LCHANPC12 0x000F0000lu
1599#define LCHANPC13 0x00F00000lu
1600#define LCHANPC14 0x0F000000lu
1601#define LCHANPC15 0xF0000000lu
1602
1603
1604/* MXVR_SYNC_LCHAN_2 Masks */
1605
1606#define LCHANPC16 0x0000000Flu
1607#define LCHANPC17 0x000000F0lu
1608#define LCHANPC18 0x00000F00lu
1609#define LCHANPC19 0x0000F000lu
1610#define LCHANPC20 0x000F0000lu
1611#define LCHANPC21 0x00F00000lu
1612#define LCHANPC22 0x0F000000lu
1613#define LCHANPC23 0xF0000000lu
1614
1615
1616/* MXVR_SYNC_LCHAN_3 Masks */
1617
1618#define LCHANPC24 0x0000000Flu
1619#define LCHANPC25 0x000000F0lu
1620#define LCHANPC26 0x00000F00lu
1621#define LCHANPC27 0x0000F000lu
1622#define LCHANPC28 0x000F0000lu
1623#define LCHANPC29 0x00F00000lu
1624#define LCHANPC30 0x0F000000lu
1625#define LCHANPC31 0xF0000000lu
1626
1627
1628/* MXVR_SYNC_LCHAN_4 Masks */
1629
1630#define LCHANPC32 0x0000000Flu
1631#define LCHANPC33 0x000000F0lu
1632#define LCHANPC34 0x00000F00lu
1633#define LCHANPC35 0x0000F000lu
1634#define LCHANPC36 0x000F0000lu
1635#define LCHANPC37 0x00F00000lu
1636#define LCHANPC38 0x0F000000lu
1637#define LCHANPC39 0xF0000000lu
1638
1639
1640/* MXVR_SYNC_LCHAN_5 Masks */
1641
1642#define LCHANPC40 0x0000000Flu
1643#define LCHANPC41 0x000000F0lu
1644#define LCHANPC42 0x00000F00lu
1645#define LCHANPC43 0x0000F000lu
1646#define LCHANPC44 0x000F0000lu
1647#define LCHANPC45 0x00F00000lu
1648#define LCHANPC46 0x0F000000lu
1649#define LCHANPC47 0xF0000000lu
1650
1651
1652/* MXVR_SYNC_LCHAN_6 Masks */
1653
1654#define LCHANPC48 0x0000000Flu
1655#define LCHANPC49 0x000000F0lu
1656#define LCHANPC50 0x00000F00lu
1657#define LCHANPC51 0x0000F000lu
1658#define LCHANPC52 0x000F0000lu
1659#define LCHANPC53 0x00F00000lu
1660#define LCHANPC54 0x0F000000lu
1661#define LCHANPC55 0xF0000000lu
1662
1663
1664/* MXVR_SYNC_LCHAN_7 Masks */
1665
1666#define LCHANPC56 0x0000000Flu
1667#define LCHANPC57 0x000000F0lu
1668#define LCHANPC58 0x00000F00lu
1669#define LCHANPC59 0x0000F000lu
1670
1671/* Bit masks for MXVR_DMAx_CONFIG */
1672
1673#define MDMAEN 0x1 /* DMA Channel Enable */
1674#define DMADD 0x2 /* DMA Channel Direction */
1675#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
1676#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
1677#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
1678#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */
1679#define MFLOW 0x7000 /* DMA Channel Operation Flow */
1680#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */
1681#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */
1682#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */
1683#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */
1684
1685/* Bit masks for MXVR_AP_CTL */
1686
1687#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */
1688#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */
1689#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */
1690#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */
1691#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */
1692
1693/* Bit masks for MXVR_APRB_START_ADDR */
1694
1695#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */
1696
1697/* Bit masks for MXVR_APRB_CURR_ADDR */
1698
1699#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
1700
1701/* Bit masks for MXVR_APTB_START_ADDR */
1702
1703#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */
1704
1705/* Bit masks for MXVR_APTB_CURR_ADDR */
1706
1707#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
1708
1709/* Bit masks for MXVR_CM_CTL */
1710
1711#define STARTCM 0x1 /* Start Control Message Transmission */
1712#define CANCELCM 0x2 /* Cancel Control Message Transmission */
1713#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */
1714#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */
1715#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */
1716#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */
1717#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */
1718#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */
1719#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */
1720#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */
1721#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */
1722#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */
1723#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */
1724#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */
1725#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */
1726#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */
1727#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */
1728#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */
1729
1730/* Bit masks for MXVR_CMRB_START_ADDR */
1731
1732#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */
1733
1734/* Bit masks for MXVR_CMRB_CURR_ADDR */
1735
1736#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */
1737
1738/* Bit masks for MXVR_CMTB_START_ADDR */
1739
1740#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */
1741
1742/* Bit masks for MXVR_CMTB_CURR_ADDR */
1743
1744#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */
1745
1746/* Bit masks for MXVR_RRDB_START_ADDR */
1747
1748#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */
1749
1750/* Bit masks for MXVR_RRDB_CURR_ADDR */
1751
1752#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */
1753
1754/* Bit masks for MXVR_PAT_DATAx */
1755
1756#define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */
1757#define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */
1758#define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */
1759#define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */
1760
1761/* Bit masks for MXVR_PAT_EN_0 */
1762
1763#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
1764#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
1765#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
1766#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
1767#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
1768#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
1769#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
1770#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
1771#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
1772#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
1773#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
1774#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
1775#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
1776#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
1777#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
1778#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
1779#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
1780#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
1781#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
1782#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
1783#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
1784#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
1785#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
1786#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
1787#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
1788#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
1789#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
1790#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
1791#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
1792#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
1793#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
1794#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
1795
1796/* Bit masks for MXVR_PAT_EN_1 */
1797
1798#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
1799#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
1800#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
1801#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
1802#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
1803#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
1804#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
1805#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
1806#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
1807#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
1808#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
1809#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
1810#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
1811#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
1812#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
1813#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
1814#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
1815#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
1816#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
1817#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
1818#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
1819#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
1820#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
1821#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
1822#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
1823#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
1824#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
1825#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
1826#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
1827#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
1828#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
1829#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
1830
1831/* Bit masks for MXVR_FRAME_CNT_0 */
1832
1833#define FCNT 0xffff /* Frame Count */
1834
1835/* Bit masks for MXVR_FRAME_CNT_1 */
1836
1837#define FCNT 0xffff /* Frame Count */
1838
1839/* Bit masks for MXVR_ROUTING_0 */
1840
1841#define TX_CH0 0x3f /* Transmit Channel 0 */
1842#define MUTE_CH0 0x80 /* Mute Channel 0 */
1843#define TX_CH1 0x3f00 /* Transmit Channel 0 */
1844#define MUTE_CH1 0x8000 /* Mute Channel 0 */
1845#define TX_CH2 0x3f0000 /* Transmit Channel 0 */
1846#define MUTE_CH2 0x800000 /* Mute Channel 0 */
1847#define TX_CH3 0x3f000000 /* Transmit Channel 0 */
1848#define MUTE_CH3 0x80000000 /* Mute Channel 0 */
1849
1850/* Bit masks for MXVR_ROUTING_1 */
1851
1852#define TX_CH4 0x3f /* Transmit Channel 4 */
1853#define MUTE_CH4 0x80 /* Mute Channel 4 */
1854#define TX_CH5 0x3f00 /* Transmit Channel 5 */
1855#define MUTE_CH5 0x8000 /* Mute Channel 5 */
1856#define TX_CH6 0x3f0000 /* Transmit Channel 6 */
1857#define MUTE_CH6 0x800000 /* Mute Channel 6 */
1858#define TX_CH7 0x3f000000 /* Transmit Channel 7 */
1859#define MUTE_CH7 0x80000000 /* Mute Channel 7 */
1860
1861/* Bit masks for MXVR_ROUTING_2 */
1862
1863#define TX_CH8 0x3f /* Transmit Channel 8 */
1864#define MUTE_CH8 0x80 /* Mute Channel 8 */
1865#define TX_CH9 0x3f00 /* Transmit Channel 9 */
1866#define MUTE_CH9 0x8000 /* Mute Channel 9 */
1867#define TX_CH10 0x3f0000 /* Transmit Channel 10 */
1868#define MUTE_CH10 0x800000 /* Mute Channel 10 */
1869#define TX_CH11 0x3f000000 /* Transmit Channel 11 */
1870#define MUTE_CH11 0x80000000 /* Mute Channel 11 */
1871
1872/* Bit masks for MXVR_ROUTING_3 */
1873
1874#define TX_CH12 0x3f /* Transmit Channel 12 */
1875#define MUTE_CH12 0x80 /* Mute Channel 12 */
1876#define TX_CH13 0x3f00 /* Transmit Channel 13 */
1877#define MUTE_CH13 0x8000 /* Mute Channel 13 */
1878#define TX_CH14 0x3f0000 /* Transmit Channel 14 */
1879#define MUTE_CH14 0x800000 /* Mute Channel 14 */
1880#define TX_CH15 0x3f000000 /* Transmit Channel 15 */
1881#define MUTE_CH15 0x80000000 /* Mute Channel 15 */
1882
1883/* Bit masks for MXVR_ROUTING_4 */
1884
1885#define TX_CH16 0x3f /* Transmit Channel 16 */
1886#define MUTE_CH16 0x80 /* Mute Channel 16 */
1887#define TX_CH17 0x3f00 /* Transmit Channel 17 */
1888#define MUTE_CH17 0x8000 /* Mute Channel 17 */
1889#define TX_CH18 0x3f0000 /* Transmit Channel 18 */
1890#define MUTE_CH18 0x800000 /* Mute Channel 18 */
1891#define TX_CH19 0x3f000000 /* Transmit Channel 19 */
1892#define MUTE_CH19 0x80000000 /* Mute Channel 19 */
1893
1894/* Bit masks for MXVR_ROUTING_5 */
1895
1896#define TX_CH20 0x3f /* Transmit Channel 20 */
1897#define MUTE_CH20 0x80 /* Mute Channel 20 */
1898#define TX_CH21 0x3f00 /* Transmit Channel 21 */
1899#define MUTE_CH21 0x8000 /* Mute Channel 21 */
1900#define TX_CH22 0x3f0000 /* Transmit Channel 22 */
1901#define MUTE_CH22 0x800000 /* Mute Channel 22 */
1902#define TX_CH23 0x3f000000 /* Transmit Channel 23 */
1903#define MUTE_CH23 0x80000000 /* Mute Channel 23 */
1904
1905/* Bit masks for MXVR_ROUTING_6 */
1906
1907#define TX_CH24 0x3f /* Transmit Channel 24 */
1908#define MUTE_CH24 0x80 /* Mute Channel 24 */
1909#define TX_CH25 0x3f00 /* Transmit Channel 25 */
1910#define MUTE_CH25 0x8000 /* Mute Channel 25 */
1911#define TX_CH26 0x3f0000 /* Transmit Channel 26 */
1912#define MUTE_CH26 0x800000 /* Mute Channel 26 */
1913#define TX_CH27 0x3f000000 /* Transmit Channel 27 */
1914#define MUTE_CH27 0x80000000 /* Mute Channel 27 */
1915
1916/* Bit masks for MXVR_ROUTING_7 */
1917
1918#define TX_CH28 0x3f /* Transmit Channel 28 */
1919#define MUTE_CH28 0x80 /* Mute Channel 28 */
1920#define TX_CH29 0x3f00 /* Transmit Channel 29 */
1921#define MUTE_CH29 0x8000 /* Mute Channel 29 */
1922#define TX_CH30 0x3f0000 /* Transmit Channel 30 */
1923#define MUTE_CH30 0x800000 /* Mute Channel 30 */
1924#define TX_CH31 0x3f000000 /* Transmit Channel 31 */
1925#define MUTE_CH31 0x80000000 /* Mute Channel 31 */
1926
1927/* Bit masks for MXVR_ROUTING_8 */
1928
1929#define TX_CH32 0x3f /* Transmit Channel 32 */
1930#define MUTE_CH32 0x80 /* Mute Channel 32 */
1931#define TX_CH33 0x3f00 /* Transmit Channel 33 */
1932#define MUTE_CH33 0x8000 /* Mute Channel 33 */
1933#define TX_CH34 0x3f0000 /* Transmit Channel 34 */
1934#define MUTE_CH34 0x800000 /* Mute Channel 34 */
1935#define TX_CH35 0x3f000000 /* Transmit Channel 35 */
1936#define MUTE_CH35 0x80000000 /* Mute Channel 35 */
1937
1938/* Bit masks for MXVR_ROUTING_9 */
1939
1940#define TX_CH36 0x3f /* Transmit Channel 36 */
1941#define MUTE_CH36 0x80 /* Mute Channel 36 */
1942#define TX_CH37 0x3f00 /* Transmit Channel 37 */
1943#define MUTE_CH37 0x8000 /* Mute Channel 37 */
1944#define TX_CH38 0x3f0000 /* Transmit Channel 38 */
1945#define MUTE_CH38 0x800000 /* Mute Channel 38 */
1946#define TX_CH39 0x3f000000 /* Transmit Channel 39 */
1947#define MUTE_CH39 0x80000000 /* Mute Channel 39 */
1948
1949/* Bit masks for MXVR_ROUTING_10 */
1950
1951#define TX_CH40 0x3f /* Transmit Channel 40 */
1952#define MUTE_CH40 0x80 /* Mute Channel 40 */
1953#define TX_CH41 0x3f00 /* Transmit Channel 41 */
1954#define MUTE_CH41 0x8000 /* Mute Channel 41 */
1955#define TX_CH42 0x3f0000 /* Transmit Channel 42 */
1956#define MUTE_CH42 0x800000 /* Mute Channel 42 */
1957#define TX_CH43 0x3f000000 /* Transmit Channel 43 */
1958#define MUTE_CH43 0x80000000 /* Mute Channel 43 */
1959
1960/* Bit masks for MXVR_ROUTING_11 */
1961
1962#define TX_CH44 0x3f /* Transmit Channel 44 */
1963#define MUTE_CH44 0x80 /* Mute Channel 44 */
1964#define TX_CH45 0x3f00 /* Transmit Channel 45 */
1965#define MUTE_CH45 0x8000 /* Mute Channel 45 */
1966#define TX_CH46 0x3f0000 /* Transmit Channel 46 */
1967#define MUTE_CH46 0x800000 /* Mute Channel 46 */
1968#define TX_CH47 0x3f000000 /* Transmit Channel 47 */
1969#define MUTE_CH47 0x80000000 /* Mute Channel 47 */
1970
1971/* Bit masks for MXVR_ROUTING_12 */
1972
1973#define TX_CH48 0x3f /* Transmit Channel 48 */
1974#define MUTE_CH48 0x80 /* Mute Channel 48 */
1975#define TX_CH49 0x3f00 /* Transmit Channel 49 */
1976#define MUTE_CH49 0x8000 /* Mute Channel 49 */
1977#define TX_CH50 0x3f0000 /* Transmit Channel 50 */
1978#define MUTE_CH50 0x800000 /* Mute Channel 50 */
1979#define TX_CH51 0x3f000000 /* Transmit Channel 51 */
1980#define MUTE_CH51 0x80000000 /* Mute Channel 51 */
1981
1982/* Bit masks for MXVR_ROUTING_13 */
1983
1984#define TX_CH52 0x3f /* Transmit Channel 52 */
1985#define MUTE_CH52 0x80 /* Mute Channel 52 */
1986#define TX_CH53 0x3f00 /* Transmit Channel 53 */
1987#define MUTE_CH53 0x8000 /* Mute Channel 53 */
1988#define TX_CH54 0x3f0000 /* Transmit Channel 54 */
1989#define MUTE_CH54 0x800000 /* Mute Channel 54 */
1990#define TX_CH55 0x3f000000 /* Transmit Channel 55 */
1991#define MUTE_CH55 0x80000000 /* Mute Channel 55 */
1992
1993/* Bit masks for MXVR_ROUTING_14 */
1994
1995#define TX_CH56 0x3f /* Transmit Channel 56 */
1996#define MUTE_CH56 0x80 /* Mute Channel 56 */
1997#define TX_CH57 0x3f00 /* Transmit Channel 57 */
1998#define MUTE_CH57 0x8000 /* Mute Channel 57 */
1999#define TX_CH58 0x3f0000 /* Transmit Channel 58 */
2000#define MUTE_CH58 0x800000 /* Mute Channel 58 */
2001#define TX_CH59 0x3f000000 /* Transmit Channel 59 */
2002#define MUTE_CH59 0x80000000 /* Mute Channel 59 */
2003
2004/* Bit masks for MXVR_BLOCK_CNT */
2005
2006#define BCNT 0xffff /* Block Count */
2007
2008/* Bit masks for MXVR_CLK_CTL */
2009
2010#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */
2011#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */
2012#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */
2013#define CLKX3SEL 0x80 /* Clock Generation Source Select */
2014#define MMCLKEN 0x100 /* Master Clock Enable */
2015#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */
2016#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */
2017#define MBCLKEN 0x10000 /* Bit Clock Enable */
2018#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */
2019#define INVRX 0x800000 /* Invert Receive Data */
2020#define MFSEN 0x1000000 /* Frame Sync Enable */
2021#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */
2022#define MFSSEL 0x60000000 /* Frame Sync Select */
2023#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */
2024
2025/* Bit masks for MXVR_CDRPLL_CTL */
2026
2027#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */
2028#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */
2029#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */
2030#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */
2031#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */
2032#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */
2033#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */
2034#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */
2035#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
2036
2037/* Bit masks for MXVR_FMPLL_CTL */
2038
2039#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */
2040#define FMRSTB 0x2 /* MXVR FMPLL Reset */
2041#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */
2042#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */
2043#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */
2044#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */
2045
2046/* Bit masks for MXVR_PIN_CTL */
2047
2048#define MTXONBOD 0x1 /* MTXONB Open Drain Select */
2049#define MTXONBG 0x2 /* MTXONB Gates MTX Select */
2050#define MFSOE 0x10 /* MFS Output Enable */
2051#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */
2052#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */
2053
2054/* Bit masks for MXVR_SCLK_CNT */
2055
2056#define SCNT 0xffff /* System Clock Count */
2057
2058/* Bit masks for KPAD_CTL */
2059
2060#define KPAD_EN 0x1 /* Keypad Enable */
2061#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
2062#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
2063#define KPAD_COLEN 0xe000 /* Column Enable Width */
2064
2065/* Bit masks for KPAD_PRESCALE */
2066
2067#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
2068
2069/* Bit masks for KPAD_MSEL */
2070
2071#define DBON_SCALE 0xff /* Debounce Scale Value */
2072#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
2073
2074/* Bit masks for KPAD_ROWCOL */
2075
2076#define KPAD_ROW 0xff /* Rows Pressed */
2077#define KPAD_COL 0xff00 /* Columns Pressed */
2078
2079/* Bit masks for KPAD_STAT */
2080
2081#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
2082#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
2083#define KPAD_PRESSED 0x8 /* Key press current status */
2084
2085/* Bit masks for KPAD_SOFTEVAL */
2086
2087#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
2088
2089/* Bit masks for SDH_COMMAND */
2090
2091#define CMD_IDX 0x3f /* Command Index */
2092#define CMD_RSP 0x40 /* Response */
2093#define CMD_L_RSP 0x80 /* Long Response */
2094#define CMD_INT_E 0x100 /* Command Interrupt */
2095#define CMD_PEND_E 0x200 /* Command Pending */
2096#define CMD_E 0x400 /* Command Enable */
2097
2098/* Bit masks for SDH_PWR_CTL */
2099
2100#define PWR_ON 0x3 /* Power On */
2101#if 0
2102#define TBD 0x3c /* TBD */
2103#endif
2104#define SD_CMD_OD 0x40 /* Open Drain Output */
2105#define ROD_CTL 0x80 /* Rod Control */
2106
2107/* Bit masks for SDH_CLK_CTL */
2108
2109#define CLKDIV 0xff /* MC_CLK Divisor */
2110#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
2111#define PWR_SV_E 0x200 /* Power Save Enable */
2112#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
2113#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
2114
2115/* Bit masks for SDH_RESP_CMD */
2116
2117#define RESP_CMD 0x3f /* Response Command */
2118
2119/* Bit masks for SDH_DATA_CTL */
2120
2121#define DTX_E 0x1 /* Data Transfer Enable */
2122#define DTX_DIR 0x2 /* Data Transfer Direction */
2123#define DTX_MODE 0x4 /* Data Transfer Mode */
2124#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
2125#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
2126
2127/* Bit masks for SDH_STATUS */
2128
2129#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
2130#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
2131#define CMD_TIME_OUT 0x4 /* CMD Time Out */
2132#define DAT_TIME_OUT 0x8 /* Data Time Out */
2133#define TX_UNDERRUN 0x10 /* Transmit Underrun */
2134#define RX_OVERRUN 0x20 /* Receive Overrun */
2135#define CMD_RESP_END 0x40 /* CMD Response End */
2136#define CMD_SENT 0x80 /* CMD Sent */
2137#define DAT_END 0x100 /* Data End */
2138#define START_BIT_ERR 0x200 /* Start Bit Error */
2139#define DAT_BLK_END 0x400 /* Data Block End */
2140#define CMD_ACT 0x800 /* CMD Active */
2141#define TX_ACT 0x1000 /* Transmit Active */
2142#define RX_ACT 0x2000 /* Receive Active */
2143#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
2144#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
2145#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
2146#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
2147#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
2148#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
2149#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
2150#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
2151
2152/* Bit masks for SDH_STATUS_CLR */
2153
2154#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
2155#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
2156#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
2157#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
2158#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
2159#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
2160#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
2161#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
2162#define DAT_END_STAT 0x100 /* Data End Status */
2163#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
2164#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
2165
2166/* Bit masks for SDH_MASK0 */
2167
2168#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
2169#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
2170#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
2171#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
2172#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
2173#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
2174#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
2175#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
2176#define DAT_END_MASK 0x100 /* Data End Mask */
2177#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
2178#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
2179#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
2180#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
2181#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
2182#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
2183#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
2184#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
2185#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
2186#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
2187#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
2188#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
2189#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
2190
2191/* Bit masks for SDH_FIFO_CNT */
2192
2193#define FIFO_COUNT 0x7fff /* FIFO Count */
2194
2195/* Bit masks for SDH_E_STATUS */
2196
2197#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
2198#define SD_CARD_DET 0x10 /* SD Card Detect */
2199
2200/* Bit masks for SDH_E_MASK */
2201
2202#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
2203#define SCD_MSK 0x40 /* Mask Card Detect */
2204
2205/* Bit masks for SDH_CFG */
2206
2207#define CLKS_EN 0x1 /* Clocks Enable */
2208#define SD4E 0x4 /* SDIO 4-Bit Enable */
2209#define MWE 0x8 /* Moving Window Enable */
2210#define SD_RST 0x10 /* SDMMC Reset */
2211#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
2212#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
2213#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
2214
2215/* Bit masks for SDH_RD_WAIT_EN */
2216
2217#define RWR 0x1 /* Read Wait Request */
2218
2219/* Bit masks for ATAPI_CONTROL */
2220
2221#define PIO_START 0x1 /* Start PIO/Reg Op */
2222#define MULTI_START 0x2 /* Start Multi-DMA Op */
2223#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
2224#define XFER_DIR 0x8 /* Transfer Direction */
2225#define IORDY_EN 0x10 /* IORDY Enable */
2226#define FIFO_FLUSH 0x20 /* Flush FIFOs */
2227#define SOFT_RST 0x40 /* Soft Reset */
2228#define DEV_RST 0x80 /* Device Reset */
2229#define TFRCNT_RST 0x100 /* Trans Count Reset */
2230#define END_ON_TERM 0x200 /* End/Terminate Select */
2231#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
2232#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
2233
2234/* Bit masks for ATAPI_STATUS */
2235
2236#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
2237#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
2238#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
2239#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
2240
2241/* Bit masks for ATAPI_DEV_ADDR */
2242
2243#define DEV_ADDR 0x1f /* Device Address */
2244
2245/* Bit masks for ATAPI_INT_MASK */
2246
2247#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
2248#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
2249#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
2250#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
2251#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
2252#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
2253#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
2254#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
2255#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
2256
2257/* Bit masks for ATAPI_INT_STATUS */
2258
2259#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
2260#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
2261#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
2262#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
2263#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
2264#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
2265#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
2266#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
2267#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
2268
2269/* Bit masks for ATAPI_LINE_STATUS */
2270
2271#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
2272#define ATAPI_DASP 0x2 /* Device dasp to host line status */
2273#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
2274#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
2275#define ATAPI_ADDR 0x70 /* ATAPI address line status */
2276#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
2277#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
2278#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
2279#define ATAPI_DIORN 0x400 /* ATAPI read line status */
2280#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
2281
2282/* Bit masks for ATAPI_SM_STATE */
2283
2284#define PIO_CSTATE 0xf /* PIO mode state machine current state */
2285#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
2286#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
2287#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
2288
2289/* Bit masks for ATAPI_TERMINATE */
2290
2291#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
2292
2293/* Bit masks for ATAPI_REG_TIM_0 */
2294
2295#define T2_REG 0xff /* End of cycle time for register access transfers */
2296#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
2297
2298/* Bit masks for ATAPI_PIO_TIM_0 */
2299
2300#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
2301#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
2302#define T4_REG 0xf000 /* DIOW data hold */
2303
2304/* Bit masks for ATAPI_PIO_TIM_1 */
2305
2306#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
2307
2308/* Bit masks for ATAPI_MULTI_TIM_0 */
2309
2310#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
2311#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
2312
2313/* Bit masks for ATAPI_MULTI_TIM_1 */
2314
2315#define TKW 0xff /* Selects DIOW negated pulsewidth */
2316#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
2317
2318/* Bit masks for ATAPI_MULTI_TIM_2 */
2319
2320#define TH 0xff /* Selects DIOW data hold */
2321#define TEOC 0xff00 /* Selects end of cycle for DMA */
2322
2323/* Bit masks for ATAPI_ULTRA_TIM_0 */
2324
2325#define TACK 0xff /* Selects setup and hold times for TACK */
2326#define TENV 0xff00 /* Selects envelope time */
2327
2328/* Bit masks for ATAPI_ULTRA_TIM_1 */
2329
2330#define TDVS 0xff /* Selects data valid setup time */
2331#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
2332
2333/* Bit masks for ATAPI_ULTRA_TIM_2 */
2334
2335#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
2336#define TMLI 0xff00 /* Selects interlock time */
2337
2338/* Bit masks for ATAPI_ULTRA_TIM_3 */
2339
2340#define TZAH 0xff /* Selects minimum delay required for output */
2341#define READY_PAUSE 0xff00 /* Selects ready to pause */
2342
2343/* Bit masks for TIMER_ENABLE1 */
2344
2345#define TIMEN8 0x1 /* Timer 8 Enable */
2346#define TIMEN9 0x2 /* Timer 9 Enable */
2347#define TIMEN10 0x4 /* Timer 10 Enable */
2348
2349/* Bit masks for TIMER_DISABLE1 */
2350
2351#define TIMDIS8 0x1 /* Timer 8 Disable */
2352#define TIMDIS9 0x2 /* Timer 9 Disable */
2353#define TIMDIS10 0x4 /* Timer 10 Disable */
2354
2355/* Bit masks for TIMER_STATUS1 */
2356
2357#define TIMIL8 0x1 /* Timer 8 Interrupt */
2358#define TIMIL9 0x2 /* Timer 9 Interrupt */
2359#define TIMIL10 0x4 /* Timer 10 Interrupt */
2360#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
2361#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
2362#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
2363#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
2364#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
2365#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
2366
2367/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
2368
2369/* Bit masks for USB_FADDR */
2370
2371#define FUNCTION_ADDRESS 0x7f /* Function address */
2372
2373/* Bit masks for USB_POWER */
2374
2375#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
2376#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
2377#define RESUME_MODE 0x4 /* DMA Mode */
2378#define RESET 0x8 /* Reset indicator */
2379#define HS_MODE 0x10 /* High Speed mode indicator */
2380#define HS_ENABLE 0x20 /* high Speed Enable */
2381#define SOFT_CONN 0x40 /* Soft connect */
2382#define ISO_UPDATE 0x80 /* Isochronous update */
2383
2384/* Bit masks for USB_INTRTX */
2385
2386#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
2387#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
2388#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
2389#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
2390#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
2391#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
2392#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
2393#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
2394
2395/* Bit masks for USB_INTRRX */
2396
2397#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
2398#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
2399#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
2400#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
2401#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
2402#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
2403#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
2404
2405/* Bit masks for USB_INTRTXE */
2406
2407#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
2408#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
2409#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
2410#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
2411#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
2412#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
2413#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
2414#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
2415
2416/* Bit masks for USB_INTRRXE */
2417
2418#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
2419#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
2420#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
2421#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
2422#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
2423#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
2424#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
2425
2426/* Bit masks for USB_INTRUSB */
2427
2428#define SUSPEND_B 0x1 /* Suspend indicator */
2429#define RESUME_B 0x2 /* Resume indicator */
2430#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
2431#define SOF_B 0x8 /* Start of frame */
2432#define CONN_B 0x10 /* Connection indicator */
2433#define DISCON_B 0x20 /* Disconnect indicator */
2434#define SESSION_REQ_B 0x40 /* Session Request */
2435#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
2436
2437/* Bit masks for USB_INTRUSBE */
2438
2439#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
2440#define RESUME_BE 0x2 /* Resume indicator int enable */
2441#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
2442#define SOF_BE 0x8 /* Start of frame int enable */
2443#define CONN_BE 0x10 /* Connection indicator int enable */
2444#define DISCON_BE 0x20 /* Disconnect indicator int enable */
2445#define SESSION_REQ_BE 0x40 /* Session Request int enable */
2446#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
2447
2448/* Bit masks for USB_FRAME */
2449
2450#define FRAME_NUMBER 0x7ff /* Frame number */
2451
2452/* Bit masks for USB_INDEX */
2453
2454#define SELECTED_ENDPOINT 0xf /* selected endpoint */
2455
2456/* Bit masks for USB_GLOBAL_CTL */
2457
2458#define GLOBAL_ENA 0x1 /* enables USB module */
2459#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
2460#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
2461#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
2462#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
2463#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
2464#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
2465#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
2466#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
2467#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
2468#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
2469#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
2470#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
2471#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
2472#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
2473
2474/* Bit masks for USB_OTG_DEV_CTL */
2475
2476#define SESSION 0x1 /* session indicator */
2477#define HOST_REQ 0x2 /* Host negotiation request */
2478#define HOST_MODE 0x4 /* indicates USBDRC is a host */
2479#define VBUS0 0x8 /* Vbus level indicator[0] */
2480#define VBUS1 0x10 /* Vbus level indicator[1] */
2481#define LSDEV 0x20 /* Low-speed indicator */
2482#define FSDEV 0x40 /* Full or High-speed indicator */
2483#define B_DEVICE 0x80 /* A' or 'B' device indicator */
2484
2485/* Bit masks for USB_OTG_VBUS_IRQ */
2486
2487#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
2488#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
2489#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
2490#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
2491#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
2492#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
2493
2494/* Bit masks for USB_OTG_VBUS_MASK */
2495
2496#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
2497#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
2498#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
2499#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
2500#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
2501#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
2502
2503/* Bit masks for USB_CSR0 */
2504
2505#define RXPKTRDY 0x1 /* data packet receive indicator */
2506#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
2507#define STALL_SENT 0x4 /* STALL handshake sent */
2508#define DATAEND 0x8 /* Data end indicator */
2509#define SETUPEND 0x10 /* Setup end */
2510#define SENDSTALL 0x20 /* Send STALL handshake */
2511#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
2512#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
2513#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
2514#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
2515#define SETUPPKT_H 0x8 /* send Setup token host mode */
2516#define ERROR_H 0x10 /* timeout error indicator host mode */
2517#define REQPKT_H 0x20 /* Request an IN transaction host mode */
2518#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
2519#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
2520
2521/* Bit masks for USB_COUNT0 */
2522
2523#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
2524
2525/* Bit masks for USB_NAKLIMIT0 */
2526
2527#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
2528
2529/* Bit masks for USB_TX_MAX_PACKET */
2530
2531#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
2532
2533/* Bit masks for USB_RX_MAX_PACKET */
2534
2535#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
2536
2537/* Bit masks for USB_TXCSR */
2538
2539#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
2540#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
2541#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
2542#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
2543#define STALL_SEND_T 0x10 /* issue a Stall handshake */
2544#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
2545#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
2546#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
2547#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
2548#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
2549#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
2550#define ISO_T 0x4000 /* enable Isochronous transfers */
2551#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
2552#define ERROR_TH 0x4 /* error condition host mode */
2553#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
2554#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
2555
2556/* Bit masks for USB_TXCOUNT */
2557
2558#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
2559
2560/* Bit masks for USB_RXCSR */
2561
2562#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
2563#define FIFO_FULL_R 0x2 /* FIFO not empty */
2564#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
2565#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
2566#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
2567#define STALL_SEND_R 0x20 /* issue a Stall handshake */
2568#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
2569#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
2570#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
2571#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
2572#define DISNYET_R 0x1000 /* disable Nyet handshakes */
2573#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
2574#define ISO_R 0x4000 /* enable Isochronous transfers */
2575#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
2576#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
2577#define REQPKT_RH 0x20 /* request an IN transaction host mode */
2578#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
2579#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
2580#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
2581#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
2582
2583/* Bit masks for USB_RXCOUNT */
2584
2585#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
2586
2587/* Bit masks for USB_TXTYPE */
2588
2589#define TARGET_EP_NO_T 0xf /* EP number */
2590#define PROTOCOL_T 0xc /* transfer type */
2591
2592/* Bit masks for USB_TXINTERVAL */
2593
2594#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
2595
2596/* Bit masks for USB_RXTYPE */
2597
2598#define TARGET_EP_NO_R 0xf /* EP number */
2599#define PROTOCOL_R 0xc /* transfer type */
2600
2601/* Bit masks for USB_RXINTERVAL */
2602
2603#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
2604
2605/* Bit masks for USB_DMA_INTERRUPT */
2606
2607#define DMA0_INT 0x1 /* DMA0 pending interrupt */
2608#define DMA1_INT 0x2 /* DMA1 pending interrupt */
2609#define DMA2_INT 0x4 /* DMA2 pending interrupt */
2610#define DMA3_INT 0x8 /* DMA3 pending interrupt */
2611#define DMA4_INT 0x10 /* DMA4 pending interrupt */
2612#define DMA5_INT 0x20 /* DMA5 pending interrupt */
2613#define DMA6_INT 0x40 /* DMA6 pending interrupt */
2614#define DMA7_INT 0x80 /* DMA7 pending interrupt */
2615
2616/* Bit masks for USB_DMAxCONTROL */
2617
2618#define DMA_ENA 0x1 /* DMA enable */
2619#define DIRECTION 0x2 /* direction of DMA transfer */
2620#define MODE 0x4 /* DMA Bus error */
2621#define INT_ENA 0x8 /* Interrupt enable */
2622#define EPNUM 0xf0 /* EP number */
2623#define BUSERROR 0x100 /* DMA Bus error */
2624
2625/* Bit masks for USB_DMAxADDRHIGH */
2626
2627#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
2628
2629/* Bit masks for USB_DMAxADDRLOW */
2630
2631#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
2632
2633/* Bit masks for USB_DMAxCOUNTHIGH */
2634
2635#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
2636
2637/* Bit masks for USB_DMAxCOUNTLOW */
2638
2639#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
2640
2641/* Bit masks for HMDMAx_CONTROL */
2642
2643#define HMDMAEN 0x1 /* Handshake MDMA Enable */
2644#define REP 0x2 /* Handshake MDMA Request Polarity */
2645#define UTE 0x8 /* Urgency Threshold Enable */
2646#define OIE 0x10 /* Overflow Interrupt Enable */
2647#define BDIE 0x20 /* Block Done Interrupt Enable */
2648#define MBDI 0x40 /* Mask Block Done Interrupt */
2649#define DRQ 0x300 /* Handshake MDMA Request Type */
2650#define RBC 0x1000 /* Force Reload of BCOUNT */
2651#define PS 0x2000 /* Pin Status */
2652#define OI 0x4000 /* Overflow Interrupt Generated */
2653#define BDI 0x8000 /* Block Done Interrupt Generated */
2654
2655/* ******************************************* */
2656/* MULTI BIT MACRO ENUMERATIONS */
2657/* ******************************************* */
2658
2659/* ************************ */
2660/* MXVR Address Offsets */
2661/* ************************ */
2662
2663/* Control Message Receive Buffer (CMRB) Address Offsets */
2664
2665#define CMRB_STRIDE 0x00000016lu
2666
2667#define CMRB_DST_OFFSET 0x00000000lu
2668#define CMRB_SRC_OFFSET 0x00000002lu
2669#define CMRB_DATA_OFFSET 0x00000005lu
2670
2671/* Control Message Transmit Buffer (CMTB) Address Offsets */
2672
2673#define CMTB_PRIO_OFFSET 0x00000000lu
2674#define CMTB_DST_OFFSET 0x00000002lu
2675#define CMTB_SRC_OFFSET 0x00000004lu
2676#define CMTB_TYPE_OFFSET 0x00000006lu
2677#define CMTB_DATA_OFFSET 0x00000007lu
2678
2679#define CMTB_ANSWER_OFFSET 0x0000000Alu
2680
2681#define CMTB_STAT_N_OFFSET 0x00000018lu
2682#define CMTB_STAT_A_OFFSET 0x00000016lu
2683#define CMTB_STAT_D_OFFSET 0x0000000Elu
2684#define CMTB_STAT_R_OFFSET 0x00000014lu
2685#define CMTB_STAT_W_OFFSET 0x00000014lu
2686#define CMTB_STAT_G_OFFSET 0x00000014lu
2687
2688/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
2689
2690#define APRB_STRIDE 0x00000400lu
2691
2692#define APRB_DST_OFFSET 0x00000000lu
2693#define APRB_LEN_OFFSET 0x00000002lu
2694#define APRB_SRC_OFFSET 0x00000004lu
2695#define APRB_DATA_OFFSET 0x00000006lu
2696
2697/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
2698
2699#define APTB_PRIO_OFFSET 0x00000000lu
2700#define APTB_DST_OFFSET 0x00000002lu
2701#define APTB_LEN_OFFSET 0x00000004lu
2702#define APTB_SRC_OFFSET 0x00000006lu
2703#define APTB_DATA_OFFSET 0x00000008lu
2704
2705/* Remote Read Buffer (RRDB) Address Offsets */
2706
2707#define RRDB_WADDR_OFFSET 0x00000100lu
2708#define RRDB_WLEN_OFFSET 0x00000101lu
2709
2710/* **************** */
2711/* MXVR Macros */
2712/* **************** */
2713
2714/* MXVR_CONFIG Macros */
2715
2716#define SET_MSB(x) ( ( (x) & 0xF ) << 9)
2717
2718/* MXVR_INT_STAT_1 Macros */
2719
2720#define DONEX(x) (0x00000002 << (4 * (x)))
2721#define HDONEX(x) (0x00000001 << (4 * (x)))
2722
2723/* MXVR_INT_EN_1 Macros */
2724
2725#define DONEENX(x) (0x00000002 << (4 * (x)))
2726#define HDONEENX(x) (0x00000001 << (4 * (x)))
2727
2728/* MXVR_CDRPLL_CTL Macros */
2729
2730#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
2731
2732/* MXVR_FMPLL_CTL Macros */
2733
2734#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24)
2735#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24)
2736
2737#endif /* _DEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
deleted file mode 100644
index e022e896cb18..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ /dev/null
@@ -1,3956 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF54x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF54X_H
32#define _DEF_BF54X_H
33
34
35/* ************************************************************** */
36/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
37/* ************************************************************** */
38
39/* PLL Registers */
40
41#define PLL_CTL 0xffc00000 /* PLL Control Register */
42#define PLL_DIV 0xffc00004 /* PLL Divisor Register */
43#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
44#define PLL_STAT 0xffc0000c /* PLL Status Register */
45#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
46
47/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
48
49#define CHIPID 0xffc00014
50/* CHIPID Masks */
51#define CHIPID_VERSION 0xF0000000
52#define CHIPID_FAMILY 0x0FFFF000
53#define CHIPID_MANUFACTURE 0x00000FFE
54
55/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
56
57#define SWRST 0xffc00100 /* Software Reset Register */
58#define SYSCR 0xffc00104 /* System Configuration register */
59
60/* SIC Registers */
61
62#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
63#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
64#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
65#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
66#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
67#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
68#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
69#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
70#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
71#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
72#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
73#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
74#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
75#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
76#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
77#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
78#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
79#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
80#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
81#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
82#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
83
84/* Watchdog Timer Registers */
85
86#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */
87#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */
88#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */
89
90/* RTC Registers */
91
92#define RTC_STAT 0xffc00300 /* RTC Status Register */
93#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
94#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
95#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */
96#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */
97#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */
98
99/* UART0 Registers */
100
101#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */
102#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */
103#define UART0_GCTL 0xffc00408 /* Global Control Register */
104#define UART0_LCR 0xffc0040c /* Line Control Register */
105#define UART0_MCR 0xffc00410 /* Modem Control Register */
106#define UART0_LSR 0xffc00414 /* Line Status Register */
107#define UART0_MSR 0xffc00418 /* Modem Status Register */
108#define UART0_SCR 0xffc0041c /* Scratch Register */
109#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
110#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
111#define UART0_THR 0xffc00428 /* Transmit Hold Register */
112#define UART0_RBR 0xffc0042c /* Receive Buffer Register */
113
114/* SPI0 Registers */
115
116#define SPI0_REGBASE 0xffc00500
117#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
118#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
119#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
120#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */
121#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */
122#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */
123#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
124
125/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
126
127/* Two Wire Interface Registers (TWI0) */
128
129#define TWI0_REGBASE 0xffc00700
130#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
131#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
132#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
133#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
134#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
135#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */
136#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
137#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
138#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
139#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
140#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */
141#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
142#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
143#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
144#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
145#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
146
147/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
148
149/* SPORT1 Registers */
150
151#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
152#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
153#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
154#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
155#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */
156#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */
157#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */
158#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */
159#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
160#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
161#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */
162#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */
163#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
164#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
165#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
166#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
167#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
168#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
169#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
170#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
171#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
172#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
173
174/* Asynchronous Memory Control Registers */
175
176#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
177#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
178#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
179#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
180#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
181#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */
182#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
183
184/* DDR Memory Control Registers */
185
186#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
187#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
188#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
189#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
190#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */
191#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */
192#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */
193#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */
194
195/* DDR BankRead and Write Count Registers */
196
197#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */
198#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */
199#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */
200#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */
201#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */
202#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */
203#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */
204#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */
205#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */
206#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */
207#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */
208#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */
209#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */
210#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */
211#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */
212#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */
213#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */
214#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */
215#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
216#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */
217#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */
218#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */
219#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */
220#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */
221#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */
222
223/* DMAC0 Registers */
224
225#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
226#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
227
228/* DMA Channel 0 Registers */
229
230#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
231#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
232#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */
233#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */
234#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */
235#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */
236#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */
237#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
238#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */
239#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
240#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
241#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */
242#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */
243
244/* DMA Channel 1 Registers */
245
246#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
247#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
248#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */
249#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */
250#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */
251#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */
252#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */
253#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
254#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */
255#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
256#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
257#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */
258#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */
259
260/* DMA Channel 2 Registers */
261
262#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
263#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
264#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */
265#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */
266#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */
267#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */
268#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */
269#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
270#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */
271#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
272#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
273#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */
274#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
275
276/* DMA Channel 3 Registers */
277
278#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
279#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
280#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */
281#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */
282#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */
283#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */
284#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */
285#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
286#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */
287#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
288#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
289#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */
290#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
291
292/* DMA Channel 4 Registers */
293
294#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
295#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
296#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */
297#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */
298#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */
299#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */
300#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */
301#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
302#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */
303#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
304#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
305#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */
306#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */
307
308/* DMA Channel 5 Registers */
309
310#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
311#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
312#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */
313#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */
314#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */
315#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */
316#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */
317#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
318#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */
319#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
320#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
321#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */
322#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */
323
324/* DMA Channel 6 Registers */
325
326#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
327#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
328#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */
329#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */
330#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */
331#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */
332#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */
333#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
334#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */
335#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
336#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
337#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */
338#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */
339
340/* DMA Channel 7 Registers */
341
342#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
343#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
344#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */
345#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */
346#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */
347#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */
348#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */
349#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
350#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */
351#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
352#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
353#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */
354#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */
355
356/* DMA Channel 8 Registers */
357
358#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
359#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
360#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */
361#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */
362#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */
363#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */
364#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */
365#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
366#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */
367#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
368#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
369#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */
370#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */
371
372/* DMA Channel 9 Registers */
373
374#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
375#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
376#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */
377#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */
378#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */
379#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */
380#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */
381#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
382#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */
383#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
384#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
385#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */
386#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */
387
388/* DMA Channel 10 Registers */
389
390#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
391#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
392#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */
393#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */
394#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */
395#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */
396#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */
397#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
398#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */
399#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
400#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
401#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */
402#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
403
404/* DMA Channel 11 Registers */
405
406#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
407#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
408#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */
409#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */
410#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */
411#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */
412#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */
413#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
414#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */
415#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
416#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
417#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */
418#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
419
420/* MDMA Stream 0 Registers */
421
422#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
423#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
424#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
425#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
426#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
427#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
428#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
429#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
430#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
431#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
432#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
433#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
434#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
435#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
436#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
437#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
438#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
439#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
440#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
441#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
442#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
443#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
444#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
445#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
446#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
447#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
448
449/* MDMA Stream 1 Registers */
450
451#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
452#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
453#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
454#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
455#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
456#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
457#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
458#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
459#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
460#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
461#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
462#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
463#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
464#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
465#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
466#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
467#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
468#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
469#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
470#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
471#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
472#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
473#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
474#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
475#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
476#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
477
478/* UART3 Registers */
479
480#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
481#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
482#define UART3_GCTL 0xffc03108 /* Global Control Register */
483#define UART3_LCR 0xffc0310c /* Line Control Register */
484#define UART3_MCR 0xffc03110 /* Modem Control Register */
485#define UART3_LSR 0xffc03114 /* Line Status Register */
486#define UART3_MSR 0xffc03118 /* Modem Status Register */
487#define UART3_SCR 0xffc0311c /* Scratch Register */
488#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
489#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
490#define UART3_THR 0xffc03128 /* Transmit Hold Register */
491#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
492
493/* EPPI1 Registers */
494
495#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */
496#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
497#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */
498#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */
499#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */
500#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */
501#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
502#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
503#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */
504#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
505#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
506#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
507#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
508#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */
509
510/* Port Interrupt 0 Registers (32-bit) */
511
512#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
513#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
514#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
515#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
516#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
517#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
518#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
519#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
520#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
521#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
522
523/* Port Interrupt 1 Registers (32-bit) */
524
525#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
526#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
527#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
528#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
529#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
530#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
531#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
532#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
533#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
534#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
535
536/* Port Interrupt 2 Registers (32-bit) */
537
538#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
539#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
540#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
541#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
542#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
543#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
544#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
545#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
546#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
547#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
548
549/* Port Interrupt 3 Registers (32-bit) */
550
551#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
552#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
553#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
554#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
555#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
556#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
557#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
558#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
559#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
560#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
561
562/* Port A Registers */
563
564#define PORTA_FER 0xffc014c0 /* Function Enable Register */
565#define PORTA 0xffc014c4 /* GPIO Data Register */
566#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
567#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
568#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
569#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
570#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
571#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */
572
573/* Port B Registers */
574
575#define PORTB_FER 0xffc014e0 /* Function Enable Register */
576#define PORTB 0xffc014e4 /* GPIO Data Register */
577#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
578#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
579#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
580#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
581#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
582#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */
583
584/* Port C Registers */
585
586#define PORTC_FER 0xffc01500 /* Function Enable Register */
587#define PORTC 0xffc01504 /* GPIO Data Register */
588#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
589#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
590#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
591#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
592#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
593#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */
594
595/* Port D Registers */
596
597#define PORTD_FER 0xffc01520 /* Function Enable Register */
598#define PORTD 0xffc01524 /* GPIO Data Register */
599#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
600#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
601#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
602#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
603#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
604#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */
605
606/* Port E Registers */
607
608#define PORTE_FER 0xffc01540 /* Function Enable Register */
609#define PORTE 0xffc01544 /* GPIO Data Register */
610#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
611#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
612#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
613#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
614#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
615#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */
616
617/* Port F Registers */
618
619#define PORTF_FER 0xffc01560 /* Function Enable Register */
620#define PORTF 0xffc01564 /* GPIO Data Register */
621#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
622#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
623#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
624#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
625#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
626#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */
627
628/* Port G Registers */
629
630#define PORTG_FER 0xffc01580 /* Function Enable Register */
631#define PORTG 0xffc01584 /* GPIO Data Register */
632#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
633#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
634#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
635#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
636#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
637#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */
638
639/* Port H Registers */
640
641#define PORTH_FER 0xffc015a0 /* Function Enable Register */
642#define PORTH 0xffc015a4 /* GPIO Data Register */
643#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
644#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
645#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
646#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
647#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
648#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */
649
650/* Port I Registers */
651
652#define PORTI_FER 0xffc015c0 /* Function Enable Register */
653#define PORTI 0xffc015c4 /* GPIO Data Register */
654#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
655#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
656#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
657#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
658#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
659#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */
660
661/* Port J Registers */
662
663#define PORTJ_FER 0xffc015e0 /* Function Enable Register */
664#define PORTJ 0xffc015e4 /* GPIO Data Register */
665#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
666#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
667#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
668#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
669#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
670#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */
671
672/* PWM Timer Registers */
673
674#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */
675#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */
676#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */
677#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */
678#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */
679#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */
680#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */
681#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */
682#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */
683#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */
684#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */
685#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */
686#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */
687#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */
688#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */
689#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */
690#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */
691#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */
692#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */
693#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */
694#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */
695#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */
696#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */
697#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */
698#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */
699#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */
700#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */
701#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */
702#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */
703#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */
704#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */
705#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */
706
707/* Timer Group of 8 */
708
709#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */
710#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */
711#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */
712
713/* DMAC1 Registers */
714
715#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
716#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
717
718/* DMA Channel 12 Registers */
719
720#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
721#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
722#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */
723#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */
724#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */
725#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */
726#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */
727#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
728#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */
729#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
730#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
731#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */
732#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */
733
734/* DMA Channel 13 Registers */
735
736#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
737#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
738#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */
739#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */
740#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */
741#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */
742#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */
743#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
744#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */
745#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
746#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
747#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */
748#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */
749
750/* DMA Channel 14 Registers */
751
752#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
753#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
754#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */
755#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */
756#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */
757#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */
758#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */
759#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
760#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */
761#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
762#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
763#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */
764#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
765
766/* DMA Channel 15 Registers */
767
768#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
769#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
770#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */
771#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */
772#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */
773#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */
774#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */
775#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
776#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */
777#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
778#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
779#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */
780#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
781
782/* DMA Channel 16 Registers */
783
784#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
785#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
786#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */
787#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */
788#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */
789#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */
790#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */
791#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
792#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */
793#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
794#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
795#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */
796#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */
797
798/* DMA Channel 17 Registers */
799
800#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
801#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
802#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */
803#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */
804#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */
805#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */
806#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */
807#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
808#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */
809#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
810#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
811#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */
812#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */
813
814/* DMA Channel 18 Registers */
815
816#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
817#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
818#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */
819#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */
820#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */
821#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */
822#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */
823#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
824#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */
825#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
826#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
827#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */
828#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */
829
830/* DMA Channel 19 Registers */
831
832#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
833#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
834#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */
835#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */
836#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */
837#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */
838#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */
839#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
840#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */
841#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
842#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
843#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */
844#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */
845
846/* DMA Channel 20 Registers */
847
848#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
849#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
850#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */
851#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */
852#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */
853#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */
854#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */
855#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
856#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */
857#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
858#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
859#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */
860#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */
861
862/* DMA Channel 21 Registers */
863
864#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
865#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
866#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */
867#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */
868#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */
869#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */
870#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */
871#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
872#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */
873#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
874#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
875#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */
876#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */
877
878/* DMA Channel 22 Registers */
879
880#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
881#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
882#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */
883#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */
884#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */
885#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */
886#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */
887#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
888#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */
889#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
890#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
891#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */
892#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
893
894/* DMA Channel 23 Registers */
895
896#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
897#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
898#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */
899#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */
900#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */
901#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */
902#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */
903#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
904#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */
905#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
906#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
907#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */
908#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
909
910/* MDMA Stream 2 Registers */
911
912#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
913#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
914#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
915#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
916#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
917#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
918#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
919#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
920#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
921#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
922#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
923#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
924#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
925#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
926#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
927#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
928#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
929#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
930#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
931#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
932#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
933#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
934#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
935#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
936#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
937#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
938
939/* MDMA Stream 3 Registers */
940
941#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
942#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
943#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
944#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
945#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
946#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
947#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
948#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
949#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
950#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
951#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
952#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
953#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
954#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
955#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
956#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
957#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
958#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
959#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
960#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
961#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
962#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
963#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
964#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
965#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
966#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
967
968/* UART1 Registers */
969
970#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */
971#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */
972#define UART1_GCTL 0xffc02008 /* Global Control Register */
973#define UART1_LCR 0xffc0200c /* Line Control Register */
974#define UART1_MCR 0xffc02010 /* Modem Control Register */
975#define UART1_LSR 0xffc02014 /* Line Status Register */
976#define UART1_MSR 0xffc02018 /* Modem Status Register */
977#define UART1_SCR 0xffc0201c /* Scratch Register */
978#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
979#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
980#define UART1_THR 0xffc02028 /* Transmit Hold Register */
981#define UART1_RBR 0xffc0202c /* Receive Buffer Register */
982
983/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
984
985/* SPI1 Registers */
986
987#define SPI1_REGBASE 0xffc02300
988#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
989#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
990#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
991#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */
992#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */
993#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */
994#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
995
996/* SPORT2 Registers */
997
998#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
999#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
1000#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
1001#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
1002#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */
1003#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */
1004#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */
1005#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */
1006#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
1007#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
1008#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */
1009#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */
1010#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
1011#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
1012#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
1013#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
1014#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
1015#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
1016#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
1017#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
1018#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
1019#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
1020
1021/* SPORT3 Registers */
1022
1023#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
1024#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
1025#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
1026#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
1027#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */
1028#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */
1029#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */
1030#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */
1031#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
1032#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
1033#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */
1034#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
1035#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
1036#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
1037#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
1038#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
1039#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
1040#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
1041#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
1042#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
1043#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
1044#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
1045
1046/* EPPI2 Registers */
1047
1048#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */
1049#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
1050#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */
1051#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */
1052#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */
1053#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */
1054#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
1055#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
1056#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */
1057#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
1058#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
1059#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
1060#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
1061#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */
1062
1063/* CAN Controller 0 Config 1 Registers */
1064
1065#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
1066#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
1067#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
1068#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
1069#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
1070#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
1071#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
1072#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
1073#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
1074#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
1075#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
1076#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
1077#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
1078
1079/* CAN Controller 0 Config 2 Registers */
1080
1081#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
1082#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
1083#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
1084#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
1085#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
1086#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
1087#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
1088#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
1089#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
1090#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
1091#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
1092#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
1093#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
1094
1095/* CAN Controller 0 Clock/Interrupt/Counter Registers */
1096
1097#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
1098#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
1099#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
1100#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
1101#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
1102#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
1103#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
1104#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
1105#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */
1106#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
1107#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
1108#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
1109#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
1110#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
1111#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
1112#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
1113
1114/* CAN Controller 0 Acceptance Registers */
1115
1116#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
1117#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
1118#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
1119#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
1120#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
1121#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
1122#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
1123#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
1124#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
1125#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
1126#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
1127#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
1128#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
1129#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
1130#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
1131#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
1132#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
1133#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
1134#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
1135#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
1136#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
1137#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
1138#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
1139#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
1140#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
1141#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
1142#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
1143#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
1144#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
1145#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
1146#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
1147#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
1148
1149/* CAN Controller 0 Acceptance Registers */
1150
1151#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
1152#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
1153#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
1154#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
1155#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
1156#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
1157#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
1158#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
1159#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
1160#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
1161#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
1162#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
1163#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
1164#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
1165#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
1166#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
1167#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
1168#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
1169#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
1170#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
1171#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
1172#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
1173#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
1174#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
1175#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
1176#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
1177#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
1178#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
1179#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
1180#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
1181#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
1182#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
1183
1184/* CAN Controller 0 Mailbox Data Registers */
1185
1186#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
1187#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
1188#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
1189#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
1190#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
1191#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
1192#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
1193#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
1194#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
1195#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
1196#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
1197#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
1198#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
1199#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
1200#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
1201#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
1202#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
1203#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
1204#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
1205#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
1206#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
1207#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
1208#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
1209#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
1210#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
1211#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
1212#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
1213#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
1214#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
1215#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
1216#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
1217#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
1218#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
1219#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
1220#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
1221#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
1222#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
1223#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
1224#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
1225#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
1226#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
1227#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
1228#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
1229#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
1230#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
1231#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
1232#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
1233#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
1234#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
1235#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
1236#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
1237#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
1238#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
1239#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
1240#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
1241#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
1242#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
1243#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
1244#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
1245#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
1246#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
1247#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
1248#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
1249#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
1250#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
1251#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
1252#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
1253#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
1254#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
1255#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
1256#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
1257#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
1258#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
1259#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
1260#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
1261#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
1262#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
1263#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
1264#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
1265#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
1266#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
1267#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
1268#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
1269#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
1270#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
1271#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
1272#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
1273#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
1274#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
1275#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
1276#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
1277#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
1278#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
1279#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
1280#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
1281#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
1282#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
1283#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
1284#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
1285#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
1286#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
1287#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
1288#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
1289#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
1290#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
1291#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
1292#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
1293#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
1294#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
1295#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
1296#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
1297#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
1298#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
1299#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
1300#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
1301#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
1302#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
1303#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
1304#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
1305#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
1306#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
1307#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
1308#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
1309#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
1310#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
1311#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
1312#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
1313#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
1314
1315/* CAN Controller 0 Mailbox Data Registers */
1316
1317#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
1318#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
1319#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
1320#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
1321#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
1322#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
1323#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
1324#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
1325#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
1326#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
1327#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
1328#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
1329#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
1330#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
1331#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
1332#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
1333#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
1334#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
1335#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
1336#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
1337#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
1338#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
1339#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
1340#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
1341#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
1342#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
1343#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
1344#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
1345#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
1346#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
1347#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
1348#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
1349#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
1350#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
1351#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
1352#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
1353#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
1354#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
1355#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
1356#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
1357#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
1358#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
1359#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
1360#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
1361#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
1362#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
1363#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
1364#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
1365#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
1366#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
1367#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
1368#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
1369#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
1370#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
1371#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
1372#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
1373#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
1374#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
1375#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
1376#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
1377#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
1378#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
1379#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
1380#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
1381#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
1382#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
1383#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
1384#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
1385#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
1386#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
1387#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
1388#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
1389#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
1390#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
1391#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
1392#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
1393#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
1394#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
1395#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
1396#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
1397#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
1398#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
1399#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
1400#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
1401#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
1402#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
1403#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
1404#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
1405#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
1406#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
1407#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
1408#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
1409#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
1410#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
1411#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
1412#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
1413#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
1414#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
1415#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
1416#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
1417#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
1418#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
1419#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
1420#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
1421#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
1422#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
1423#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
1424#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
1425#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
1426#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
1427#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
1428#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
1429#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
1430#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
1431#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
1432#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
1433#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
1434#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
1435#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
1436#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
1437#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
1438#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
1439#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
1440#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
1441#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
1442#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
1443#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
1444#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
1445
1446/* UART3 Registers */
1447
1448#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
1449#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
1450#define UART3_GCTL 0xffc03108 /* Global Control Register */
1451#define UART3_LCR 0xffc0310c /* Line Control Register */
1452#define UART3_MCR 0xffc03110 /* Modem Control Register */
1453#define UART3_LSR 0xffc03114 /* Line Status Register */
1454#define UART3_MSR 0xffc03118 /* Modem Status Register */
1455#define UART3_SCR 0xffc0311c /* Scratch Register */
1456#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
1457#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
1458#define UART3_THR 0xffc03128 /* Transmit Hold Register */
1459#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
1460
1461/* NFC Registers */
1462
1463#define NFC_CTL 0xffc03b00 /* NAND Control Register */
1464#define NFC_STAT 0xffc03b04 /* NAND Status Register */
1465#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
1466#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
1467#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */
1468#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */
1469#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */
1470#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */
1471#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */
1472#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */
1473#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */
1474#define NFC_READ 0xffc03b2c /* NAND Read Data Register */
1475#define NFC_ADDR 0xffc03b40 /* NAND Address Register */
1476#define NFC_CMD 0xffc03b44 /* NAND Command Register */
1477#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */
1478#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */
1479
1480/* Counter Registers */
1481
1482#define CNT_CONFIG 0xffc04200 /* Configuration Register */
1483#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
1484#define CNT_STATUS 0xffc04208 /* Status Register */
1485#define CNT_COMMAND 0xffc0420c /* Command Register */
1486#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */
1487#define CNT_COUNTER 0xffc04214 /* Counter Register */
1488#define CNT_MAX 0xffc04218 /* Maximal Count Register */
1489#define CNT_MIN 0xffc0421c /* Minimal Count Register */
1490
1491/* OTP/FUSE Registers */
1492
1493#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */
1494#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */
1495#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */
1496#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */
1497
1498/* Security Registers */
1499
1500#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */
1501#define SECURE_CONTROL 0xffc04324 /* Secure Control */
1502#define SECURE_STATUS 0xffc04328 /* Secure Status */
1503
1504/* DMA Peripheral Mux Register */
1505
1506#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
1507
1508/* OTP Read/Write Data Buffer Registers */
1509
1510#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1511#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1512#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1513#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1514
1515/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
1516
1517/* ********************************************************** */
1518/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1519/* and MULTI BIT READ MACROS */
1520/* ********************************************************** */
1521
1522/* SIC_IMASK Masks */
1523#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1524#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1525#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
1526#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
1527
1528/* SIC_IWR Masks */
1529#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1530#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1531#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
1532#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
1533
1534/* Bit masks for SIC_IAR0 */
1535
1536#define PLL_WAKEUP 0x1 /* PLL Wakeup */
1537
1538/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
1539
1540#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
1541#define EPPI0_ERR 0x4 /* EPPI0 Error */
1542#define SPORT0_ERR 0x8 /* SPORT0 Error */
1543#define SPORT1_ERR 0x10 /* SPORT1 Error */
1544#define SPI0_ERR 0x20 /* SPI0 Error */
1545#define UART0_ERR 0x40 /* UART0 Error */
1546#define RTC 0x80 /* Real-Time Clock */
1547#define DMA12 0x100 /* DMA Channel 12 */
1548#define DMA0 0x200 /* DMA Channel 0 */
1549#define DMA1 0x400 /* DMA Channel 1 */
1550#define DMA2 0x800 /* DMA Channel 2 */
1551#define DMA3 0x1000 /* DMA Channel 3 */
1552#define DMA4 0x2000 /* DMA Channel 4 */
1553#define DMA6 0x4000 /* DMA Channel 6 */
1554#define DMA7 0x8000 /* DMA Channel 7 */
1555#define PINT0 0x80000 /* Pin Interrupt 0 */
1556#define PINT1 0x100000 /* Pin Interrupt 1 */
1557#define MDMA0 0x200000 /* Memory DMA Stream 0 */
1558#define MDMA1 0x400000 /* Memory DMA Stream 1 */
1559#define WDOG 0x800000 /* Watchdog Timer */
1560#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
1561#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
1562#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
1563#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
1564#define SPI1_ERR 0x10000000 /* SPI1 Error */
1565#define SPI2_ERR 0x20000000 /* SPI2 Error */
1566#define UART1_ERR 0x40000000 /* UART1 Error */
1567#define UART2_ERR 0x80000000 /* UART2 Error */
1568
1569/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
1570
1571#define CAN0_ERR 0x1 /* CAN0 Error */
1572#define DMA18 0x2 /* DMA Channel 18 */
1573#define DMA19 0x4 /* DMA Channel 19 */
1574#define DMA20 0x8 /* DMA Channel 20 */
1575#define DMA21 0x10 /* DMA Channel 21 */
1576#define DMA13 0x20 /* DMA Channel 13 */
1577#define DMA14 0x40 /* DMA Channel 14 */
1578#define DMA5 0x80 /* DMA Channel 5 */
1579#define DMA23 0x100 /* DMA Channel 23 */
1580#define DMA8 0x200 /* DMA Channel 8 */
1581#define DMA9 0x400 /* DMA Channel 9 */
1582#define DMA10 0x800 /* DMA Channel 10 */
1583#define DMA11 0x1000 /* DMA Channel 11 */
1584#define TWI0 0x2000 /* TWI0 */
1585#define TWI1 0x4000 /* TWI1 */
1586#define CAN0_RX 0x8000 /* CAN0 Receive */
1587#define CAN0_TX 0x10000 /* CAN0 Transmit */
1588#define MDMA2 0x20000 /* Memory DMA Stream 0 */
1589#define MDMA3 0x40000 /* Memory DMA Stream 1 */
1590#define MXVR_STAT 0x80000 /* MXVR Status */
1591#define MXVR_CM 0x100000 /* MXVR Control Message */
1592#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
1593#define EPPI1_ERR 0x400000 /* EPPI1 Error */
1594#define EPPI2_ERR 0x800000 /* EPPI2 Error */
1595#define UART3_ERR 0x1000000 /* UART3 Error */
1596#define HOST_ERR 0x2000000 /* Host DMA Port Error */
1597#define USB_ERR 0x4000000 /* USB Error */
1598#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
1599#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
1600#define ATAPI_ERR 0x20000000 /* ATAPI Error */
1601#define CAN1_ERR 0x40000000 /* CAN1 Error */
1602#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
1603#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
1604#define DMAR0 0x80000000 /* DMAR0 Block */
1605#define DMAR1 0x80000000 /* DMAR1 Block */
1606
1607/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
1608
1609#define DMA15 0x1 /* DMA Channel 15 */
1610#define DMA16 0x2 /* DMA Channel 16 */
1611#define DMA17 0x4 /* DMA Channel 17 */
1612#define DMA22 0x8 /* DMA Channel 22 */
1613#define CNT 0x10 /* Counter */
1614#define KEY 0x20 /* Keypad */
1615#define CAN1_RX 0x40 /* CAN1 Receive */
1616#define CAN1_TX 0x80 /* CAN1 Transmit */
1617#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
1618#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
1619#define USB_EINT 0x400 /* USB Exception */
1620#define USB_INT0 0x800 /* USB Interrupt 0 */
1621#define USB_INT1 0x1000 /* USB Interrupt 1 */
1622#define USB_INT2 0x2000 /* USB Interrupt 2 */
1623#define USB_DMAINT 0x4000 /* USB DMA */
1624#define OTPSEC 0x8000 /* OTP Access Complete */
1625#define TIMER0 0x400000 /* Timer 0 */
1626#define TIMER1 0x800000 /* Timer 1 */
1627#define TIMER2 0x1000000 /* Timer 2 */
1628#define TIMER3 0x2000000 /* Timer 3 */
1629#define TIMER4 0x4000000 /* Timer 4 */
1630#define TIMER5 0x8000000 /* Timer 5 */
1631#define TIMER6 0x10000000 /* Timer 6 */
1632#define TIMER7 0x20000000 /* Timer 7 */
1633#define PINT2 0x40000000 /* Pin Interrupt 2 */
1634#define PINT3 0x80000000 /* Pin Interrupt 3 */
1635
1636/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
1637
1638#define DMAEN 0x1 /* DMA Channel Enable */
1639#define WNR 0x2 /* DMA Direction */
1640#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */
1641#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */
1642#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */
1643#define DMA2D 0x10 /* DMA Mode */
1644#define RESTART 0x20 /* Work Unit Transitions */
1645#define DI_SEL 0x40 /* Data Interrupt Timing Select */
1646#define DI_EN 0x80 /* Data Interrupt Enable */
1647
1648#define NDSIZE 0xf00 /* Flex Descriptor Size */
1649#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1650#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1651#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1652#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1653#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1654#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1655#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1656#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1657#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1658#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1659
1660#define DMAFLOW 0xf000 /* Next Operation */
1661#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1662#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1663#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1664#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1665#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1666
1667/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1668
1669#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
1670#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
1671#define DFETCH 0x4 /* DMA Descriptor Fetch */
1672#define DMA_RUN 0x8 /* DMA Channel Running */
1673
1674/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1675
1676#define CTYPE 0x40 /* DMA Channel Type */
1677#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
1678
1679/* Bit masks for DMACx_TCPER */
1680
1681#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
1682#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
1683#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
1684#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
1685
1686/* Bit masks for DMACx_TCCNT */
1687
1688#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
1689#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
1690#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
1691#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
1692
1693/* Bit masks for DMAC1_PERIMUX */
1694
1695#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
1696
1697/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1698/* EBIU_AMGCTL Masks */
1699#define AMCKEN 0x0001 /* Enable CLKOUT */
1700#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1701#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1702#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1703#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1704#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1705
1706
1707/* Bit masks for EBIU_AMBCTL0 */
1708
1709#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
1710#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
1711#define B0TT 0xc /* Bank 0 transition time */
1712#define B0ST 0x30 /* Bank 0 Setup time */
1713#define B0HT 0xc0 /* Bank 0 Hold time */
1714#define B0RAT 0xf00 /* Bank 0 Read access time */
1715#define B0WAT 0xf000 /* Bank 0 write access time */
1716#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
1717#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
1718#define B1TT 0xc0000 /* Bank 1 transition time */
1719#define B1ST 0x300000 /* Bank 1 Setup time */
1720#define B1HT 0xc00000 /* Bank 1 Hold time */
1721#define B1RAT 0xf000000 /* Bank 1 Read access time */
1722#define B1WAT 0xf0000000 /* Bank 1 write access time */
1723
1724/* Bit masks for EBIU_AMBCTL1 */
1725
1726#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
1727#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
1728#define B2TT 0xc /* Bank 2 transition time */
1729#define B2ST 0x30 /* Bank 2 Setup time */
1730#define B2HT 0xc0 /* Bank 2 Hold time */
1731#define B2RAT 0xf00 /* Bank 2 Read access time */
1732#define B2WAT 0xf000 /* Bank 2 write access time */
1733#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
1734#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
1735#define B3TT 0xc0000 /* Bank 3 transition time */
1736#define B3ST 0x300000 /* Bank 3 Setup time */
1737#define B3HT 0xc00000 /* Bank 3 Hold time */
1738#define B3RAT 0xf000000 /* Bank 3 Read access time */
1739#define B3WAT 0xf0000000 /* Bank 3 write access time */
1740
1741/* Bit masks for EBIU_MBSCTL */
1742
1743#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
1744#define AMSB1CTL 0xc /* Async Memory Bank 1 select */
1745#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
1746#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
1747
1748/* Bit masks for EBIU_MODE */
1749
1750#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
1751#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
1752#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
1753#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
1754
1755/* Bit masks for EBIU_FCTL */
1756
1757#define TESTSETLOCK 0x1 /* Test set lock */
1758#define BCLK 0x6 /* Burst clock frequency */
1759#define PGWS 0x38 /* Page wait states */
1760#define PGSZ 0x40 /* Page size */
1761#define RDDL 0x380 /* Read data delay */
1762
1763/* Bit masks for EBIU_ARBSTAT */
1764
1765#define ARBSTAT 0x1 /* Arbitration status */
1766#define BGSTAT 0x2 /* Bus grant status */
1767
1768/* Bit masks for EBIU_DDRCTL0 */
1769
1770#define TREFI 0x3fff /* Refresh Interval */
1771#define TRFC 0x3c000 /* Auto-refresh command period */
1772#define TRP 0x3c0000 /* Pre charge-to-active command period */
1773#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1774#define TRC 0x3c000000 /* Active-to-active time */
1775#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
1776#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
1777#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
1778#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
1779#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
1780
1781/* Bit masks for EBIU_DDRCTL1 */
1782
1783#define TRCD 0xf /* Active-to-Read/write delay */
1784#define TMRD 0xf0 /* Mode register set to active */
1785#define TWR 0x300 /* Write Recovery time */
1786#define DDRDATWIDTH 0x3000 /* DDR data width */
1787#define EXTBANKS 0xc000 /* External banks */
1788#define DDRDEVWIDTH 0x30000 /* DDR device width */
1789#define DDRDEVSIZE 0xc0000 /* DDR device size */
1790#define TWTR 0xf0000000 /* Write-to-read delay */
1791#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
1792#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
1793#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
1794#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
1795#define DDR_DATWIDTH 0x2000 /* DDR data width */
1796#define EXTBANK_1 0 /* 1 external bank */
1797#define EXTBANK_2 0x4000 /* 2 external banks */
1798#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
1799#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
1800#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
1801#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
1802#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
1803#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
1804#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
1805
1806/* Bit masks for EBIU_DDRCTL2 */
1807
1808#define BURSTLENGTH 0x7 /* Burst length */
1809#define CASLATENCY 0x70 /* CAS latency */
1810#define DLLRESET 0x100 /* DLL Reset */
1811#define REGE 0x1000 /* Register mode enable */
1812#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
1813#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
1814#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
1815#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
1816
1817/* Bit masks for EBIU_DDRCTL3 */
1818
1819#define PASR 0x7 /* Partial array self-refresh */
1820
1821/* Bit masks for EBIU_DDRQUE */
1822
1823#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
1824#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
1825#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
1826#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
1827#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
1828#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
1829#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
1830
1831/* Bit masks for EBIU_ERRMST */
1832
1833#define DEB1_ERROR 0x1 /* DEB1 Error */
1834#define DEB2_ERROR 0x2 /* DEB2 Error */
1835#define DEB3_ERROR 0x4 /* DEB3 Error */
1836#define CORE_ERROR 0x8 /* Core error */
1837#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
1838#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
1839#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
1840#define CORE_MERROR 0x80 /* Core Error (2nd) */
1841
1842/* Bit masks for EBIU_ERRADD */
1843
1844#define ERROR_ADDRESS 0xffffffff /* Error Address */
1845
1846/* Bit masks for EBIU_RSTCTL */
1847
1848#define DDRSRESET 0x1 /* DDR soft reset */
1849#define PFTCHSRESET 0x4 /* DDR prefetch reset */
1850#define SRREQ 0x8 /* Self-refresh request */
1851#define SRACK 0x10 /* Self-refresh acknowledge */
1852#define MDDRENABLE 0x20 /* Mobile DDR enable */
1853
1854/* Bit masks for EBIU_DDRBRC0 */
1855
1856#define BRC0 0xffffffff /* Count */
1857
1858/* Bit masks for EBIU_DDRBRC1 */
1859
1860#define BRC1 0xffffffff /* Count */
1861
1862/* Bit masks for EBIU_DDRBRC2 */
1863
1864#define BRC2 0xffffffff /* Count */
1865
1866/* Bit masks for EBIU_DDRBRC3 */
1867
1868#define BRC3 0xffffffff /* Count */
1869
1870/* Bit masks for EBIU_DDRBRC4 */
1871
1872#define BRC4 0xffffffff /* Count */
1873
1874/* Bit masks for EBIU_DDRBRC5 */
1875
1876#define BRC5 0xffffffff /* Count */
1877
1878/* Bit masks for EBIU_DDRBRC6 */
1879
1880#define BRC6 0xffffffff /* Count */
1881
1882/* Bit masks for EBIU_DDRBRC7 */
1883
1884#define BRC7 0xffffffff /* Count */
1885
1886/* Bit masks for EBIU_DDRBWC0 */
1887
1888#define BWC0 0xffffffff /* Count */
1889
1890/* Bit masks for EBIU_DDRBWC1 */
1891
1892#define BWC1 0xffffffff /* Count */
1893
1894/* Bit masks for EBIU_DDRBWC2 */
1895
1896#define BWC2 0xffffffff /* Count */
1897
1898/* Bit masks for EBIU_DDRBWC3 */
1899
1900#define BWC3 0xffffffff /* Count */
1901
1902/* Bit masks for EBIU_DDRBWC4 */
1903
1904#define BWC4 0xffffffff /* Count */
1905
1906/* Bit masks for EBIU_DDRBWC5 */
1907
1908#define BWC5 0xffffffff /* Count */
1909
1910/* Bit masks for EBIU_DDRBWC6 */
1911
1912#define BWC6 0xffffffff /* Count */
1913
1914/* Bit masks for EBIU_DDRBWC7 */
1915
1916#define BWC7 0xffffffff /* Count */
1917
1918/* Bit masks for EBIU_DDRACCT */
1919
1920#define ACCT 0xffffffff /* Count */
1921
1922/* Bit masks for EBIU_DDRTACT */
1923
1924#define TECT 0xffffffff /* Count */
1925
1926/* Bit masks for EBIU_DDRARCT */
1927
1928#define ARCT 0xffffffff /* Count */
1929
1930/* Bit masks for EBIU_DDRGC0 */
1931
1932#define GC0 0xffffffff /* Count */
1933
1934/* Bit masks for EBIU_DDRGC1 */
1935
1936#define GC1 0xffffffff /* Count */
1937
1938/* Bit masks for EBIU_DDRGC2 */
1939
1940#define GC2 0xffffffff /* Count */
1941
1942/* Bit masks for EBIU_DDRGC3 */
1943
1944#define GC3 0xffffffff /* Count */
1945
1946/* Bit masks for EBIU_DDRMCEN */
1947
1948#define B0WCENABLE 0x1 /* Bank 0 write count enable */
1949#define B1WCENABLE 0x2 /* Bank 1 write count enable */
1950#define B2WCENABLE 0x4 /* Bank 2 write count enable */
1951#define B3WCENABLE 0x8 /* Bank 3 write count enable */
1952#define B4WCENABLE 0x10 /* Bank 4 write count enable */
1953#define B5WCENABLE 0x20 /* Bank 5 write count enable */
1954#define B6WCENABLE 0x40 /* Bank 6 write count enable */
1955#define B7WCENABLE 0x80 /* Bank 7 write count enable */
1956#define B0RCENABLE 0x100 /* Bank 0 read count enable */
1957#define B1RCENABLE 0x200 /* Bank 1 read count enable */
1958#define B2RCENABLE 0x400 /* Bank 2 read count enable */
1959#define B3RCENABLE 0x800 /* Bank 3 read count enable */
1960#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
1961#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
1962#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
1963#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
1964#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
1965#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
1966#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
1967#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
1968#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
1969#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
1970#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
1971#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
1972
1973/* Bit masks for EBIU_DDRMCCL */
1974
1975#define CB0WCOUNT 0x1 /* Clear write count 0 */
1976#define CB1WCOUNT 0x2 /* Clear write count 1 */
1977#define CB2WCOUNT 0x4 /* Clear write count 2 */
1978#define CB3WCOUNT 0x8 /* Clear write count 3 */
1979#define CB4WCOUNT 0x10 /* Clear write count 4 */
1980#define CB5WCOUNT 0x20 /* Clear write count 5 */
1981#define CB6WCOUNT 0x40 /* Clear write count 6 */
1982#define CB7WCOUNT 0x80 /* Clear write count 7 */
1983#define CBRCOUNT 0x100 /* Clear read count 0 */
1984#define CB1RCOUNT 0x200 /* Clear read count 1 */
1985#define CB2RCOUNT 0x400 /* Clear read count 2 */
1986#define CB3RCOUNT 0x800 /* Clear read count 3 */
1987#define CB4RCOUNT 0x1000 /* Clear read count 4 */
1988#define CB5RCOUNT 0x2000 /* Clear read count 5 */
1989#define CB6RCOUNT 0x4000 /* Clear read count 6 */
1990#define CB7RCOUNT 0x8000 /* Clear read count 7 */
1991#define CRACOUNT 0x10000 /* Clear row activation count */
1992#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
1993#define CARCOUNT 0x40000 /* Clear auto-refresh count */
1994#define CG0COUNT 0x100000 /* Clear grant count 0 */
1995#define CG1COUNT 0x200000 /* Clear grant count 1 */
1996#define CG2COUNT 0x400000 /* Clear grant count 2 */
1997#define CG3COUNT 0x800000 /* Clear grant count 3 */
1998
1999/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
2000
2001#define Px0 0x1 /* GPIO 0 */
2002#define Px1 0x2 /* GPIO 1 */
2003#define Px2 0x4 /* GPIO 2 */
2004#define Px3 0x8 /* GPIO 3 */
2005#define Px4 0x10 /* GPIO 4 */
2006#define Px5 0x20 /* GPIO 5 */
2007#define Px6 0x40 /* GPIO 6 */
2008#define Px7 0x80 /* GPIO 7 */
2009#define Px8 0x100 /* GPIO 8 */
2010#define Px9 0x200 /* GPIO 9 */
2011#define Px10 0x400 /* GPIO 10 */
2012#define Px11 0x800 /* GPIO 11 */
2013#define Px12 0x1000 /* GPIO 12 */
2014#define Px13 0x2000 /* GPIO 13 */
2015#define Px14 0x4000 /* GPIO 14 */
2016#define Px15 0x8000 /* GPIO 15 */
2017
2018/* Bit masks for PORTA_MUX - PORTJ_MUX */
2019
2020#define PxM0 0x3 /* GPIO Mux 0 */
2021#define PxM1 0xc /* GPIO Mux 1 */
2022#define PxM2 0x30 /* GPIO Mux 2 */
2023#define PxM3 0xc0 /* GPIO Mux 3 */
2024#define PxM4 0x300 /* GPIO Mux 4 */
2025#define PxM5 0xc00 /* GPIO Mux 5 */
2026#define PxM6 0x3000 /* GPIO Mux 6 */
2027#define PxM7 0xc000 /* GPIO Mux 7 */
2028#define PxM8 0x30000 /* GPIO Mux 8 */
2029#define PxM9 0xc0000 /* GPIO Mux 9 */
2030#define PxM10 0x300000 /* GPIO Mux 10 */
2031#define PxM11 0xc00000 /* GPIO Mux 11 */
2032#define PxM12 0x3000000 /* GPIO Mux 12 */
2033#define PxM13 0xc000000 /* GPIO Mux 13 */
2034#define PxM14 0x30000000 /* GPIO Mux 14 */
2035#define PxM15 0xc0000000 /* GPIO Mux 15 */
2036
2037
2038/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
2039
2040#define IB0 0x1 /* Interrupt Bit 0 */
2041#define IB1 0x2 /* Interrupt Bit 1 */
2042#define IB2 0x4 /* Interrupt Bit 2 */
2043#define IB3 0x8 /* Interrupt Bit 3 */
2044#define IB4 0x10 /* Interrupt Bit 4 */
2045#define IB5 0x20 /* Interrupt Bit 5 */
2046#define IB6 0x40 /* Interrupt Bit 6 */
2047#define IB7 0x80 /* Interrupt Bit 7 */
2048#define IB8 0x100 /* Interrupt Bit 8 */
2049#define IB9 0x200 /* Interrupt Bit 9 */
2050#define IB10 0x400 /* Interrupt Bit 10 */
2051#define IB11 0x800 /* Interrupt Bit 11 */
2052#define IB12 0x1000 /* Interrupt Bit 12 */
2053#define IB13 0x2000 /* Interrupt Bit 13 */
2054#define IB14 0x4000 /* Interrupt Bit 14 */
2055#define IB15 0x8000 /* Interrupt Bit 15 */
2056
2057/* Bit masks for TIMERx_CONFIG */
2058
2059#define TMODE 0x3 /* Timer Mode */
2060#define PULSE_HI 0x4 /* Pulse Polarity */
2061#define PERIOD_CNT 0x8 /* Period Count */
2062#define IRQ_ENA 0x10 /* Interrupt Request Enable */
2063#define TIN_SEL 0x20 /* Timer Input Select */
2064#define OUT_DIS 0x40 /* Output Pad Disable */
2065#define CLK_SEL 0x80 /* Timer Clock Select */
2066#define TOGGLE_HI 0x100 /* Toggle Mode */
2067#define EMU_RUN 0x200 /* Emulation Behavior Select */
2068#define ERR_TYP 0xc000 /* Error Type */
2069
2070/* Bit masks for TIMER_ENABLE0 */
2071
2072#define TIMEN0 0x1 /* Timer 0 Enable */
2073#define TIMEN1 0x2 /* Timer 1 Enable */
2074#define TIMEN2 0x4 /* Timer 2 Enable */
2075#define TIMEN3 0x8 /* Timer 3 Enable */
2076#define TIMEN4 0x10 /* Timer 4 Enable */
2077#define TIMEN5 0x20 /* Timer 5 Enable */
2078#define TIMEN6 0x40 /* Timer 6 Enable */
2079#define TIMEN7 0x80 /* Timer 7 Enable */
2080
2081/* Bit masks for TIMER_DISABLE0 */
2082
2083#define TIMDIS0 0x1 /* Timer 0 Disable */
2084#define TIMDIS1 0x2 /* Timer 1 Disable */
2085#define TIMDIS2 0x4 /* Timer 2 Disable */
2086#define TIMDIS3 0x8 /* Timer 3 Disable */
2087#define TIMDIS4 0x10 /* Timer 4 Disable */
2088#define TIMDIS5 0x20 /* Timer 5 Disable */
2089#define TIMDIS6 0x40 /* Timer 6 Disable */
2090#define TIMDIS7 0x80 /* Timer 7 Disable */
2091
2092/* Bit masks for TIMER_STATUS0 */
2093
2094#define TIMIL0 0x1 /* Timer 0 Interrupt */
2095#define TIMIL1 0x2 /* Timer 1 Interrupt */
2096#define TIMIL2 0x4 /* Timer 2 Interrupt */
2097#define TIMIL3 0x8 /* Timer 3 Interrupt */
2098#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
2099#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
2100#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
2101#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
2102#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
2103#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
2104#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
2105#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
2106#define TIMIL4 0x10000 /* Timer 4 Interrupt */
2107#define TIMIL5 0x20000 /* Timer 5 Interrupt */
2108#define TIMIL6 0x40000 /* Timer 6 Interrupt */
2109#define TIMIL7 0x80000 /* Timer 7 Interrupt */
2110#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
2111#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
2112#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
2113#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
2114#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
2115#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
2116#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
2117#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
2118
2119/* Bit masks for WDOG_CTL */
2120
2121#define WDEV 0x6 /* Watchdog Event */
2122#define WDEN 0xff0 /* Watchdog Enable */
2123#define WDRO 0x8000 /* Watchdog Rolled Over */
2124
2125/* Bit masks for CNT_CONFIG */
2126
2127#define CNTE 0x1 /* Counter Enable */
2128#define DEBE 0x2 /* Debounce Enable */
2129#define CDGINV 0x10 /* CDG Pin Polarity Invert */
2130#define CUDINV 0x20 /* CUD Pin Polarity Invert */
2131#define CZMINV 0x40 /* CZM Pin Polarity Invert */
2132#define CNTMODE 0x700 /* Counter Operating Mode */
2133#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
2134#define BNDMODE 0x3000 /* Boundary register Mode */
2135#define INPDIS 0x8000 /* CUG and CDG Input Disable */
2136
2137/* Bit masks for CNT_IMASK */
2138
2139#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
2140#define UCIE 0x2 /* Up count Interrupt Enable */
2141#define DCIE 0x4 /* Down count Interrupt Enable */
2142#define MINCIE 0x8 /* Min Count Interrupt Enable */
2143#define MAXCIE 0x10 /* Max Count Interrupt Enable */
2144#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
2145#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
2146#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
2147#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
2148#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
2149#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
2150
2151/* Bit masks for CNT_STATUS */
2152
2153#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
2154#define UCII 0x2 /* Up count Interrupt Identifier */
2155#define DCII 0x4 /* Down count Interrupt Identifier */
2156#define MINCII 0x8 /* Min Count Interrupt Identifier */
2157#define MAXCII 0x10 /* Max Count Interrupt Identifier */
2158#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
2159#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
2160#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
2161#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
2162#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
2163#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
2164
2165/* Bit masks for CNT_COMMAND */
2166
2167#define W1LCNT 0xf /* Load Counter Register */
2168#define W1LMIN 0xf0 /* Load Min Register */
2169#define W1LMAX 0xf00 /* Load Max Register */
2170#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
2171
2172/* Bit masks for CNT_DEBOUNCE */
2173
2174#define DPRESCALE 0xf /* Load Counter Register */
2175
2176/* Bit masks for RTC_STAT */
2177
2178#define SECONDS 0x3f /* Seconds */
2179#define MINUTES 0xfc0 /* Minutes */
2180#define HOURS 0x1f000 /* Hours */
2181#define DAY_COUNTER 0xfffe0000 /* Day Counter */
2182
2183/* Bit masks for RTC_ICTL */
2184
2185#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */
2186#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */
2187#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
2188#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */
2189#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */
2190#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */
2191#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */
2192#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */
2193
2194/* Bit masks for RTC_ISTAT */
2195
2196#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */
2197#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */
2198#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
2199#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */
2200#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */
2201#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */
2202#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */
2203#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */
2204#define WRITE_COMPLETE 0x8000 /* Write Complete */
2205
2206/* Bit masks for RTC_SWCNT */
2207
2208#define STOPWATCH_COUNT 0xffff /* Stopwatch Count */
2209
2210/* Bit masks for RTC_ALARM */
2211
2212#define SECONDS 0x3f /* Seconds */
2213#define MINUTES 0xfc0 /* Minutes */
2214#define HOURS 0x1f000 /* Hours */
2215#define DAY 0xfffe0000 /* Day */
2216
2217/* Bit masks for RTC_PREN */
2218
2219#define PREN 0x1 /* Prescaler Enable */
2220
2221/* Bit masks for OTP_CONTROL */
2222
2223#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
2224#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
2225#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
2226#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
2227#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
2228#define FWREN 0x8000 /* OTP/Fuse Write Enable */
2229
2230/* Bit masks for OTP_BEN */
2231
2232#define FBEN 0xffff /* OTP/Fuse Byte Enable */
2233
2234/* Bit masks for OTP_STATUS */
2235
2236#define FCOMP 0x1 /* OTP/Fuse Access Complete */
2237#define FERROR 0x2 /* OTP/Fuse Access Error */
2238#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
2239#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
2240#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
2241
2242/* Bit masks for OTP_TIMING */
2243
2244#define USECDIV 0xff /* Micro Second Divider */
2245#define READACC 0x7f00 /* Read Access Time */
2246#define CPUMPRL 0x38000 /* Charge Pump Release Time */
2247#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
2248#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
2249#define PGMTIME 0xff000000 /* Program Time */
2250
2251/* Bit masks for SECURE_SYSSWT */
2252
2253#define EMUDABL 0x1 /* Emulation Disable. */
2254#define RSTDABL 0x2 /* Reset Disable */
2255#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
2256#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
2257#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
2258#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
2259#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
2260#define EMUOVR 0x4000 /* Emulation Override */
2261#define OTPSEN 0x8000 /* OTP Secrets Enable. */
2262#define L2DABL 0x70000 /* L2 Memory Disable. */
2263
2264/* Bit masks for SECURE_CONTROL */
2265
2266#define SECURE0 0x1 /* SECURE 0 */
2267#define SECURE1 0x2 /* SECURE 1 */
2268#define SECURE2 0x4 /* SECURE 2 */
2269#define SECURE3 0x8 /* SECURE 3 */
2270
2271/* Bit masks for SECURE_STATUS */
2272
2273#define SECMODE 0x3 /* Secured Mode Control State */
2274#define NMI 0x4 /* Non Maskable Interrupt */
2275#define AFVALID 0x8 /* Authentication Firmware Valid */
2276#define AFEXIT 0x10 /* Authentication Firmware Exit */
2277#define SECSTAT 0xe0 /* Secure Status */
2278
2279/* Bit masks for PLL_DIV */
2280
2281#define CSEL 0x30 /* Core Select */
2282#define SSEL 0xf /* System Select */
2283#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
2284#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
2285#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
2286#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
2287
2288/* Bit masks for PLL_CTL */
2289
2290#define MSEL 0x7e00 /* Multiplier Select */
2291#define BYPASS 0x100 /* PLL Bypass Enable */
2292#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
2293#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
2294#define PDWN 0x20 /* Power Down */
2295#define STOPCK 0x8 /* Stop Clock */
2296#define PLL_OFF 0x2 /* Disable PLL */
2297#define DF 0x1 /* Divide Frequency */
2298
2299/* SWRST Masks */
2300#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
2301#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
2302#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
2303#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
2304#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
2305
2306/* Bit masks for PLL_STAT */
2307
2308#define PLL_LOCKED 0x20 /* PLL Locked Status */
2309#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
2310#define FULL_ON 0x2 /* Full-On Mode */
2311#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
2312#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
2313#define CANWS 0x800 /* CAN Wake-Up Status */
2314#define USBWS 0x2000 /* USB Wake-Up Status */
2315#define KPADWS 0x4000 /* Keypad Wake-Up Status */
2316#define ROTWS 0x8000 /* Rotary Wake-Up Status */
2317#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
2318
2319/* Bit masks for VR_CTL */
2320
2321#define FREQ 0x3 /* Regulator Switching Frequency */
2322#define GAIN 0xc /* Voltage Output Level Gain */
2323#define VLEV 0xf0 /* Internal Voltage Level */
2324#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
2325#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
2326#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
2327#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
2328#define USBWE 0x800 /* USB Wake-Up Enable */
2329#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
2330#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
2331
2332#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
2333#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
2334#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
2335
2336#define GAIN_5 0x0000 /* GAIN = 5*/
2337#define GAIN_10 0x0004 /* GAIN = 1*/
2338#define GAIN_20 0x0008 /* GAIN = 2*/
2339#define GAIN_50 0x000C /* GAIN = 5*/
2340
2341#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
2342#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
2343#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
2344#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
2345#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
2346#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
2347#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
2348#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
2349#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
2350#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
2351
2352/* Bit masks for NFC_CTL */
2353
2354#define WR_DLY 0xf /* Write Strobe Delay */
2355#define RD_DLY 0xf0 /* Read Strobe Delay */
2356#define NWIDTH 0x100 /* NAND Data Width */
2357#define PG_SIZE 0x200 /* Page Size */
2358
2359/* Bit masks for NFC_STAT */
2360
2361#define NBUSY 0x1 /* Not Busy */
2362#define WB_FULL 0x2 /* Write Buffer Full */
2363#define PG_WR_STAT 0x4 /* Page Write Pending */
2364#define PG_RD_STAT 0x8 /* Page Read Pending */
2365#define WB_EMPTY 0x10 /* Write Buffer Empty */
2366
2367/* Bit masks for NFC_IRQSTAT */
2368
2369#define NBUSYIRQ 0x1 /* Not Busy IRQ */
2370#define WB_OVF 0x2 /* Write Buffer Overflow */
2371#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
2372#define RD_RDY 0x8 /* Read Data Ready */
2373#define WR_DONE 0x10 /* Page Write Done */
2374
2375/* Bit masks for NFC_IRQMASK */
2376
2377#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
2378#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
2379#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
2380#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
2381#define MASK_WRDONE 0x10 /* Mask Write Done */
2382
2383/* Bit masks for NFC_RST */
2384
2385#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
2386
2387/* Bit masks for NFC_PGCTL */
2388
2389#define PG_RD_START 0x1 /* Page Read Start */
2390#define PG_WR_START 0x2 /* Page Write Start */
2391
2392/* Bit masks for NFC_ECC0 */
2393
2394#define ECC0 0x7ff /* Parity Calculation Result0 */
2395
2396/* Bit masks for NFC_ECC1 */
2397
2398#define ECC1 0x7ff /* Parity Calculation Result1 */
2399
2400/* Bit masks for NFC_ECC2 */
2401
2402#define ECC2 0x7ff /* Parity Calculation Result2 */
2403
2404/* Bit masks for NFC_ECC3 */
2405
2406#define ECC3 0x7ff /* Parity Calculation Result3 */
2407
2408/* Bit masks for NFC_COUNT */
2409
2410#define ECCCNT 0x3ff /* Transfer Count */
2411
2412/* Bit masks for CAN0_CONTROL */
2413
2414#define SRS 0x1 /* Software Reset */
2415#define DNM 0x2 /* DeviceNet Mode */
2416#define ABO 0x4 /* Auto Bus On */
2417#define WBA 0x10 /* Wakeup On CAN Bus Activity */
2418#define SMR 0x20 /* Sleep Mode Request */
2419#define CSR 0x40 /* CAN Suspend Mode Request */
2420#define CCR 0x80 /* CAN Configuration Mode Request */
2421
2422/* Bit masks for CAN0_STATUS */
2423
2424#define WT 0x1 /* CAN Transmit Warning Flag */
2425#define WR 0x2 /* CAN Receive Warning Flag */
2426#define EP 0x4 /* CAN Error Passive Mode */
2427#define EBO 0x8 /* CAN Error Bus Off Mode */
2428#define CSA 0x40 /* CAN Suspend Mode Acknowledge */
2429#define CCA 0x80 /* CAN Configuration Mode Acknowledge */
2430#define MBPTR 0x1f00 /* Mailbox Pointer */
2431#define TRM 0x4000 /* Transmit Mode Status */
2432#define REC 0x8000 /* Receive Mode Status */
2433
2434/* Bit masks for CAN0_DEBUG */
2435
2436#define DEC 0x1 /* Disable Transmit/Receive Error Counters */
2437#define DRI 0x2 /* Disable CANRX Input Pin */
2438#define DTO 0x4 /* Disable CANTX Output Pin */
2439#define DIL 0x8 /* Disable Internal Loop */
2440#define MAA 0x10 /* Mode Auto-Acknowledge */
2441#define MRB 0x20 /* Mode Read Back */
2442#define CDE 0x8000 /* CAN Debug Mode Enable */
2443
2444/* Bit masks for CAN0_CLOCK */
2445
2446#define BRP 0x3ff /* CAN Bit Rate Prescaler */
2447
2448/* Bit masks for CAN0_TIMING */
2449
2450#define SJW 0x300 /* Synchronization Jump Width */
2451#define SAM 0x80 /* Sampling */
2452#define TSEG2 0x70 /* Time Segment 2 */
2453#define TSEG1 0xf /* Time Segment 1 */
2454
2455/* Bit masks for CAN0_INTR */
2456
2457#define CANRX 0x80 /* Serial Input From Transceiver */
2458#define CANTX 0x40 /* Serial Output To Transceiver */
2459#define SMACK 0x8 /* Sleep Mode Acknowledge */
2460#define GIRQ 0x4 /* Global Interrupt Request Status */
2461#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
2462#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
2463
2464/* Bit masks for CAN0_GIM */
2465
2466#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
2467#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
2468#define EPIM 0x4 /* Error Passive Interrupt Mask */
2469#define BOIM 0x8 /* Bus Off Interrupt Mask */
2470#define WUIM 0x10 /* Wakeup Interrupt Mask */
2471#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
2472#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
2473#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
2474#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
2475#define ADIM 0x400 /* Access Denied Interrupt Mask */
2476
2477/* Bit masks for CAN0_GIS */
2478
2479#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
2480#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
2481#define EPIS 0x4 /* Error Passive Interrupt Status */
2482#define BOIS 0x8 /* Bus Off Interrupt Status */
2483#define WUIS 0x10 /* Wakeup Interrupt Status */
2484#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
2485#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
2486#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
2487#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
2488#define ADIS 0x400 /* Access Denied Interrupt Status */
2489
2490/* Bit masks for CAN0_GIF */
2491
2492#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
2493#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
2494#define EPIF 0x4 /* Error Passive Interrupt Flag */
2495#define BOIF 0x8 /* Bus Off Interrupt Flag */
2496#define WUIF 0x10 /* Wakeup Interrupt Flag */
2497#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
2498#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
2499#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
2500#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
2501#define ADIF 0x400 /* Access Denied Interrupt Flag */
2502
2503/* Bit masks for CAN0_MBTD */
2504
2505#define TDR 0x80 /* Temporary Disable Request */
2506#define TDA 0x40 /* Temporary Disable Acknowledge */
2507#define TDPTR 0x1f /* Temporary Disable Pointer */
2508
2509/* Bit masks for CAN0_UCCNF */
2510
2511#define UCCNF 0xf /* Universal Counter Configuration */
2512#define UCRC 0x20 /* Universal Counter Reload/Clear */
2513#define UCCT 0x40 /* Universal Counter CAN Trigger */
2514#define UCE 0x80 /* Universal Counter Enable */
2515
2516/* Bit masks for CAN0_UCCNT */
2517
2518#define UCCNT 0xffff /* Universal Counter Count Value */
2519
2520/* Bit masks for CAN0_UCRC */
2521
2522#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */
2523
2524/* Bit masks for CAN0_CEC */
2525
2526#define RXECNT 0xff /* Receive Error Counter */
2527#define TXECNT 0xff00 /* Transmit Error Counter */
2528
2529/* Bit masks for CAN0_ESR */
2530
2531#define FER 0x80 /* Form Error */
2532#define BEF 0x40 /* Bit Error Flag */
2533#define SA0 0x20 /* Stuck At Dominant */
2534#define CRCE 0x10 /* CRC Error */
2535#define SER 0x8 /* Stuff Bit Error */
2536#define ACKE 0x4 /* Acknowledge Error */
2537
2538/* Bit masks for CAN0_EWR */
2539
2540#define EWLTEC 0xff00 /* Transmit Error Warning Limit */
2541#define EWLREC 0xff /* Receive Error Warning Limit */
2542
2543/* Bit masks for CAN0_AMxx_H */
2544
2545#define FDF 0x8000 /* Filter On Data Field */
2546#define FMD 0x4000 /* Full Mask Data */
2547#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
2548#define BASEID 0x1ffc /* Base Identifier */
2549#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2550
2551/* Bit masks for CAN0_AMxx_L */
2552
2553#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
2554#define DFM 0xffff /* Data Field Mask */
2555
2556/* Bit masks for CAN0_MBxx_ID1 */
2557
2558#define AME 0x8000 /* Acceptance Mask Enable */
2559#define RTR 0x4000 /* Remote Transmission Request */
2560#define IDE 0x2000 /* Identifier Extension */
2561#define BASEID 0x1ffc /* Base Identifier */
2562#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2563
2564/* Bit masks for CAN0_MBxx_ID0 */
2565
2566#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
2567#define DFM 0xffff /* Data Field Mask */
2568
2569/* Bit masks for CAN0_MBxx_TIMESTAMP */
2570
2571#define TSV 0xffff /* Time Stamp Value */
2572
2573/* Bit masks for CAN0_MBxx_LENGTH */
2574
2575#define DLC 0xf /* Data Length Code */
2576
2577/* Bit masks for CAN0_MBxx_DATA3 */
2578
2579#define CAN_BYTE0 0xff00 /* Data Field Byte 0 */
2580#define CAN_BYTE1 0xff /* Data Field Byte 1 */
2581
2582/* Bit masks for CAN0_MBxx_DATA2 */
2583
2584#define CAN_BYTE2 0xff00 /* Data Field Byte 2 */
2585#define CAN_BYTE3 0xff /* Data Field Byte 3 */
2586
2587/* Bit masks for CAN0_MBxx_DATA1 */
2588
2589#define CAN_BYTE4 0xff00 /* Data Field Byte 4 */
2590#define CAN_BYTE5 0xff /* Data Field Byte 5 */
2591
2592/* Bit masks for CAN0_MBxx_DATA0 */
2593
2594#define CAN_BYTE6 0xff00 /* Data Field Byte 6 */
2595#define CAN_BYTE7 0xff /* Data Field Byte 7 */
2596
2597/* Bit masks for CAN0_MC1 */
2598
2599#define MC0 0x1 /* Mailbox 0 Enable */
2600#define MC1 0x2 /* Mailbox 1 Enable */
2601#define MC2 0x4 /* Mailbox 2 Enable */
2602#define MC3 0x8 /* Mailbox 3 Enable */
2603#define MC4 0x10 /* Mailbox 4 Enable */
2604#define MC5 0x20 /* Mailbox 5 Enable */
2605#define MC6 0x40 /* Mailbox 6 Enable */
2606#define MC7 0x80 /* Mailbox 7 Enable */
2607#define MC8 0x100 /* Mailbox 8 Enable */
2608#define MC9 0x200 /* Mailbox 9 Enable */
2609#define MC10 0x400 /* Mailbox 10 Enable */
2610#define MC11 0x800 /* Mailbox 11 Enable */
2611#define MC12 0x1000 /* Mailbox 12 Enable */
2612#define MC13 0x2000 /* Mailbox 13 Enable */
2613#define MC14 0x4000 /* Mailbox 14 Enable */
2614#define MC15 0x8000 /* Mailbox 15 Enable */
2615
2616/* Bit masks for CAN0_MC2 */
2617
2618#define MC16 0x1 /* Mailbox 16 Enable */
2619#define MC17 0x2 /* Mailbox 17 Enable */
2620#define MC18 0x4 /* Mailbox 18 Enable */
2621#define MC19 0x8 /* Mailbox 19 Enable */
2622#define MC20 0x10 /* Mailbox 20 Enable */
2623#define MC21 0x20 /* Mailbox 21 Enable */
2624#define MC22 0x40 /* Mailbox 22 Enable */
2625#define MC23 0x80 /* Mailbox 23 Enable */
2626#define MC24 0x100 /* Mailbox 24 Enable */
2627#define MC25 0x200 /* Mailbox 25 Enable */
2628#define MC26 0x400 /* Mailbox 26 Enable */
2629#define MC27 0x800 /* Mailbox 27 Enable */
2630#define MC28 0x1000 /* Mailbox 28 Enable */
2631#define MC29 0x2000 /* Mailbox 29 Enable */
2632#define MC30 0x4000 /* Mailbox 30 Enable */
2633#define MC31 0x8000 /* Mailbox 31 Enable */
2634
2635/* Bit masks for CAN0_MD1 */
2636
2637#define MD0 0x1 /* Mailbox 0 Receive Enable */
2638#define MD1 0x2 /* Mailbox 1 Receive Enable */
2639#define MD2 0x4 /* Mailbox 2 Receive Enable */
2640#define MD3 0x8 /* Mailbox 3 Receive Enable */
2641#define MD4 0x10 /* Mailbox 4 Receive Enable */
2642#define MD5 0x20 /* Mailbox 5 Receive Enable */
2643#define MD6 0x40 /* Mailbox 6 Receive Enable */
2644#define MD7 0x80 /* Mailbox 7 Receive Enable */
2645#define MD8 0x100 /* Mailbox 8 Receive Enable */
2646#define MD9 0x200 /* Mailbox 9 Receive Enable */
2647#define MD10 0x400 /* Mailbox 10 Receive Enable */
2648#define MD11 0x800 /* Mailbox 11 Receive Enable */
2649#define MD12 0x1000 /* Mailbox 12 Receive Enable */
2650#define MD13 0x2000 /* Mailbox 13 Receive Enable */
2651#define MD14 0x4000 /* Mailbox 14 Receive Enable */
2652#define MD15 0x8000 /* Mailbox 15 Receive Enable */
2653
2654/* Bit masks for CAN0_MD2 */
2655
2656#define MD16 0x1 /* Mailbox 16 Receive Enable */
2657#define MD17 0x2 /* Mailbox 17 Receive Enable */
2658#define MD18 0x4 /* Mailbox 18 Receive Enable */
2659#define MD19 0x8 /* Mailbox 19 Receive Enable */
2660#define MD20 0x10 /* Mailbox 20 Receive Enable */
2661#define MD21 0x20 /* Mailbox 21 Receive Enable */
2662#define MD22 0x40 /* Mailbox 22 Receive Enable */
2663#define MD23 0x80 /* Mailbox 23 Receive Enable */
2664#define MD24 0x100 /* Mailbox 24 Receive Enable */
2665#define MD25 0x200 /* Mailbox 25 Receive Enable */
2666#define MD26 0x400 /* Mailbox 26 Receive Enable */
2667#define MD27 0x800 /* Mailbox 27 Receive Enable */
2668#define MD28 0x1000 /* Mailbox 28 Receive Enable */
2669#define MD29 0x2000 /* Mailbox 29 Receive Enable */
2670#define MD30 0x4000 /* Mailbox 30 Receive Enable */
2671#define MD31 0x8000 /* Mailbox 31 Receive Enable */
2672
2673/* Bit masks for CAN0_RMP1 */
2674
2675#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
2676#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
2677#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
2678#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
2679#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
2680#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
2681#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
2682#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
2683#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
2684#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
2685#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
2686#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
2687#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
2688#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
2689#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
2690#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
2691
2692/* Bit masks for CAN0_RMP2 */
2693
2694#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
2695#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
2696#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
2697#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
2698#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
2699#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
2700#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
2701#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
2702#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
2703#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
2704#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
2705#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
2706#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
2707#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
2708#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
2709#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
2710
2711/* Bit masks for CAN0_RML1 */
2712
2713#define RML0 0x1 /* Mailbox 0 Receive Message Lost */
2714#define RML1 0x2 /* Mailbox 1 Receive Message Lost */
2715#define RML2 0x4 /* Mailbox 2 Receive Message Lost */
2716#define RML3 0x8 /* Mailbox 3 Receive Message Lost */
2717#define RML4 0x10 /* Mailbox 4 Receive Message Lost */
2718#define RML5 0x20 /* Mailbox 5 Receive Message Lost */
2719#define RML6 0x40 /* Mailbox 6 Receive Message Lost */
2720#define RML7 0x80 /* Mailbox 7 Receive Message Lost */
2721#define RML8 0x100 /* Mailbox 8 Receive Message Lost */
2722#define RML9 0x200 /* Mailbox 9 Receive Message Lost */
2723#define RML10 0x400 /* Mailbox 10 Receive Message Lost */
2724#define RML11 0x800 /* Mailbox 11 Receive Message Lost */
2725#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
2726#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
2727#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
2728#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
2729
2730/* Bit masks for CAN0_RML2 */
2731
2732#define RML16 0x1 /* Mailbox 16 Receive Message Lost */
2733#define RML17 0x2 /* Mailbox 17 Receive Message Lost */
2734#define RML18 0x4 /* Mailbox 18 Receive Message Lost */
2735#define RML19 0x8 /* Mailbox 19 Receive Message Lost */
2736#define RML20 0x10 /* Mailbox 20 Receive Message Lost */
2737#define RML21 0x20 /* Mailbox 21 Receive Message Lost */
2738#define RML22 0x40 /* Mailbox 22 Receive Message Lost */
2739#define RML23 0x80 /* Mailbox 23 Receive Message Lost */
2740#define RML24 0x100 /* Mailbox 24 Receive Message Lost */
2741#define RML25 0x200 /* Mailbox 25 Receive Message Lost */
2742#define RML26 0x400 /* Mailbox 26 Receive Message Lost */
2743#define RML27 0x800 /* Mailbox 27 Receive Message Lost */
2744#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
2745#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
2746#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
2747#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
2748
2749/* Bit masks for CAN0_OPSS1 */
2750
2751#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
2752#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
2753#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
2754#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
2755#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
2756#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
2757#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
2758#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
2759#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
2760#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
2761#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
2762#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
2763#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
2764#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
2765#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
2766#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
2767
2768/* Bit masks for CAN0_OPSS2 */
2769
2770#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
2771#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
2772#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
2773#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
2774#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
2775#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
2776#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
2777#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
2778#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
2779#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
2780#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
2781#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
2782#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
2783#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
2784#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
2785#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
2786
2787/* Bit masks for CAN0_TRS1 */
2788
2789#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
2790#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
2791#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
2792#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
2793#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
2794#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
2795#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
2796#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
2797#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
2798#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
2799#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
2800#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
2801#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
2802#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
2803#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
2804#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
2805
2806/* Bit masks for CAN0_TRS2 */
2807
2808#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
2809#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
2810#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
2811#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
2812#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
2813#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
2814#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
2815#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
2816#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
2817#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
2818#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
2819#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
2820#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
2821#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
2822#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
2823#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
2824
2825/* Bit masks for CAN0_TRR1 */
2826
2827#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
2828#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
2829#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
2830#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
2831#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
2832#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
2833#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
2834#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
2835#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
2836#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
2837#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
2838#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
2839#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
2840#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
2841#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
2842#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
2843
2844/* Bit masks for CAN0_TRR2 */
2845
2846#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
2847#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
2848#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
2849#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
2850#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
2851#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
2852#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
2853#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
2854#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
2855#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
2856#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
2857#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
2858#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
2859#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
2860#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
2861#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
2862
2863/* Bit masks for CAN0_AA1 */
2864
2865#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
2866#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
2867#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
2868#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
2869#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
2870#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
2871#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
2872#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
2873#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
2874#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
2875#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
2876#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
2877#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
2878#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
2879#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
2880#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
2881
2882/* Bit masks for CAN0_AA2 */
2883
2884#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
2885#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
2886#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
2887#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
2888#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
2889#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
2890#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
2891#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
2892#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
2893#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
2894#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
2895#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
2896#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
2897#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
2898#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
2899#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
2900
2901/* Bit masks for CAN0_TA1 */
2902
2903#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
2904#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
2905#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
2906#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
2907#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
2908#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
2909#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
2910#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
2911#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
2912#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
2913#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
2914#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
2915#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
2916#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
2917#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
2918#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
2919
2920/* Bit masks for CAN0_TA2 */
2921
2922#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
2923#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
2924#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
2925#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
2926#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
2927#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
2928#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
2929#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
2930#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
2931#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
2932#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
2933#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
2934#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
2935#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
2936#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
2937#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
2938
2939/* Bit masks for CAN0_RFH1 */
2940
2941#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
2942#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
2943#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
2944#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
2945#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
2946#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
2947#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
2948#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
2949#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
2950#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
2951#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
2952#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
2953#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
2954#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
2955#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
2956#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
2957
2958/* Bit masks for CAN0_RFH2 */
2959
2960#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
2961#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
2962#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
2963#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
2964#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
2965#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
2966#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
2967#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
2968#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
2969#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
2970#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
2971#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
2972#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
2973#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
2974#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
2975#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
2976
2977/* Bit masks for CAN0_MBIM1 */
2978
2979#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
2980#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
2981#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
2982#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
2983#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
2984#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
2985#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
2986#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
2987#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
2988#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
2989#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
2990#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
2991#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
2992#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
2993#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
2994#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
2995
2996/* Bit masks for CAN0_MBIM2 */
2997
2998#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
2999#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
3000#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
3001#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
3002#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
3003#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
3004#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
3005#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
3006#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
3007#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
3008#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
3009#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
3010#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
3011#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
3012#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
3013#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
3014
3015/* Bit masks for CAN0_MBTIF1 */
3016
3017#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
3018#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
3019#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
3020#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
3021#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
3022#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
3023#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
3024#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
3025#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
3026#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
3027#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
3028#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
3029#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
3030#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
3031#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
3032#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
3033
3034/* Bit masks for CAN0_MBTIF2 */
3035
3036#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
3037#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
3038#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
3039#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
3040#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
3041#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
3042#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
3043#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
3044#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
3045#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
3046#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
3047#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
3048#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
3049#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
3050#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
3051#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
3052
3053/* Bit masks for CAN0_MBRIF1 */
3054
3055#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
3056#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
3057#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
3058#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
3059#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
3060#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
3061#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
3062#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
3063#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
3064#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
3065#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
3066#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
3067#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
3068#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
3069#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
3070#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
3071
3072/* Bit masks for CAN0_MBRIF2 */
3073
3074#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
3075#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
3076#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
3077#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
3078#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
3079#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
3080#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
3081#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
3082#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
3083#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
3084#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
3085#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
3086#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
3087#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
3088#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
3089#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
3090
3091/* Bit masks for EPPIx_STATUS */
3092
3093#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
3094#define YFIFO_ERR 0x2 /* Luma FIFO Error */
3095#define LTERR_OVR 0x4 /* Line Track Overflow */
3096#define LTERR_UNDR 0x8 /* Line Track Underflow */
3097#define FTERR_OVR 0x10 /* Frame Track Overflow */
3098#define FTERR_UNDR 0x20 /* Frame Track Underflow */
3099#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
3100#define DMA1URQ 0x80 /* DMA1 Urgent Request */
3101#define DMA0URQ 0x100 /* DMA0 Urgent Request */
3102#define ERR_DET 0x4000 /* Preamble Error Detected */
3103#define FLD 0x8000 /* Field */
3104
3105/* Bit masks for EPPIx_CONTROL */
3106
3107#define EPPI_EN 0x1 /* Enable */
3108#define EPPI_DIR 0x2 /* Direction */
3109#define XFR_TYPE 0xc /* Operating Mode */
3110#define FS_CFG 0x30 /* Frame Sync Configuration */
3111#define FLD_SEL 0x40 /* Field Select/Trigger */
3112#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
3113#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
3114#define ICLKGEN 0x200 /* Internal Clock Generation */
3115#define IFSGEN 0x400 /* Internal Frame Sync Generation */
3116#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
3117#define POLS 0x6000 /* Frame Sync Polarity */
3118#define DLENGTH 0x38000 /* Data Length */
3119#define SKIP_EN 0x40000 /* Skip Enable */
3120#define SKIP_EO 0x80000 /* Skip Even or Odd */
3121#define PACKEN 0x100000 /* Packing/Unpacking Enable */
3122#define SWAPEN 0x200000 /* Swap Enable */
3123#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
3124#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
3125#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
3126#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
3127#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
3128#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
3129#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
3130
3131#define DLEN_8 (0 << 15) /* 000 - 8 bits */
3132#define DLEN_10 (1 << 15) /* 001 - 10 bits */
3133#define DLEN_12 (2 << 15) /* 010 - 12 bits */
3134#define DLEN_14 (3 << 15) /* 011 - 14 bits */
3135#define DLEN_16 (4 << 15) /* 100 - 16 bits */
3136#define DLEN_18 (5 << 15) /* 101 - 18 bits */
3137#define DLEN_24 (6 << 15) /* 110 - 24 bits */
3138
3139
3140/* Bit masks for EPPIx_FS2W_LVB */
3141
3142#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
3143#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */
3144#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */
3145#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
3146
3147/* Bit masks for EPPIx_FS2W_LAVF */
3148
3149#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */
3150#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
3151
3152/* Bit masks for EPPIx_CLIP */
3153
3154#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */
3155#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */
3156#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
3157#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
3158
3159/* Bit masks for SPIx_BAUD */
3160
3161#define SPI_BAUD 0xffff /* Baud Rate */
3162
3163/* Bit masks for SPIx_CTL */
3164
3165#define SPE 0x4000 /* SPI Enable */
3166#define WOM 0x2000 /* Write Open Drain Master */
3167#define MSTR 0x1000 /* Master Mode */
3168#define CPOL 0x800 /* Clock Polarity */
3169#define CPHA 0x400 /* Clock Phase */
3170#define LSBF 0x200 /* LSB First */
3171#define SIZE 0x100 /* Size of Words */
3172#define EMISO 0x20 /* Enable MISO Output */
3173#define PSSE 0x10 /* Slave-Select Enable */
3174#define GM 0x8 /* Get More Data */
3175#define SZ 0x4 /* Send Zero */
3176#define TIMOD 0x3 /* Transfer Initiation Mode */
3177
3178/* Bit masks for SPIx_FLG */
3179
3180#define FLS1 0x2 /* Slave Select Enable 1 */
3181#define FLS2 0x4 /* Slave Select Enable 2 */
3182#define FLS3 0x8 /* Slave Select Enable 3 */
3183#define FLG1 0x200 /* Slave Select Value 1 */
3184#define FLG2 0x400 /* Slave Select Value 2 */
3185#define FLG3 0x800 /* Slave Select Value 3 */
3186
3187/* Bit masks for SPIx_STAT */
3188
3189#define TXCOL 0x40 /* Transmit Collision Error */
3190#define RXS 0x20 /* RDBR Data Buffer Status */
3191#define RBSY 0x10 /* Receive Error */
3192#define TXS 0x8 /* TDBR Data Buffer Status */
3193#define TXE 0x4 /* Transmission Error */
3194#define MODF 0x2 /* Mode Fault Error */
3195#define SPIF 0x1 /* SPI Finished */
3196
3197/* Bit masks for SPIx_TDBR */
3198
3199#define TDBR 0xffff /* Transmit Data Buffer */
3200
3201/* Bit masks for SPIx_RDBR */
3202
3203#define RDBR 0xffff /* Receive Data Buffer */
3204
3205/* Bit masks for SPIx_SHADOW */
3206
3207#define SHADOW 0xffff /* RDBR Shadow */
3208
3209/* ************************************************ */
3210/* The TWI bit masks fields are from the ADSP-BF538 */
3211/* and they have not been verified as the final */
3212/* ones for the Moab processors ... bz 1/19/2007 */
3213/* ************************************************ */
3214
3215/* Bit masks for TWIx_CONTROL */
3216
3217#define PRESCALE 0x7f /* Prescale Value */
3218#define TWI_ENA 0x80 /* TWI Enable */
3219#define SCCB 0x200 /* Serial Camera Control Bus */
3220
3221/* Bit maskes for TWIx_CLKDIV */
3222
3223#define CLKLOW 0xff /* Clock Low */
3224#define CLKHI 0xff00 /* Clock High */
3225
3226/* Bit maskes for TWIx_SLAVE_CTL */
3227
3228#define SEN 0x1 /* Slave Enable */
3229#define STDVAL 0x4 /* Slave Transmit Data Valid */
3230#define NAK 0x8 /* Not Acknowledge */
3231#define GEN 0x10 /* General Call Enable */
3232
3233/* Bit maskes for TWIx_SLAVE_ADDR */
3234
3235#define SADDR 0x7f /* Slave Mode Address */
3236
3237/* Bit maskes for TWIx_SLAVE_STAT */
3238
3239#define SDIR 0x1 /* Slave Transfer Direction */
3240#define GCALL 0x2 /* General Call */
3241
3242/* Bit maskes for TWIx_MASTER_CTL */
3243
3244#define MEN 0x1 /* Master Mode Enable */
3245#define MDIR 0x4 /* Master Transfer Direction */
3246#define FAST 0x8 /* Fast Mode */
3247#define STOP 0x10 /* Issue Stop Condition */
3248#define RSTART 0x20 /* Repeat Start */
3249#define DCNT 0x3fc0 /* Data Transfer Count */
3250#define SDAOVR 0x4000 /* Serial Data Override */
3251#define SCLOVR 0x8000 /* Serial Clock Override */
3252
3253/* Bit maskes for TWIx_MASTER_ADDR */
3254
3255#define MADDR 0x7f /* Master Mode Address */
3256
3257/* Bit maskes for TWIx_MASTER_STAT */
3258
3259#define MPROG 0x1 /* Master Transfer in Progress */
3260#define LOSTARB 0x2 /* Lost Arbitration */
3261#define ANAK 0x4 /* Address Not Acknowledged */
3262#define DNAK 0x8 /* Data Not Acknowledged */
3263#define BUFRDERR 0x10 /* Buffer Read Error */
3264#define BUFWRERR 0x20 /* Buffer Write Error */
3265#define SDASEN 0x40 /* Serial Data Sense */
3266#define SCLSEN 0x80 /* Serial Clock Sense */
3267#define BUSBUSY 0x100 /* Bus Busy */
3268
3269/* Bit maskes for TWIx_FIFO_CTL */
3270
3271#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
3272#define RCVFLUSH 0x2 /* Receive Buffer Flush */
3273#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
3274#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
3275
3276/* Bit maskes for TWIx_FIFO_STAT */
3277
3278#define XMTSTAT 0x3 /* Transmit FIFO Status */
3279#define RCVSTAT 0xc /* Receive FIFO Status */
3280
3281/* Bit maskes for TWIx_INT_MASK */
3282
3283#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
3284#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
3285#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
3286#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
3287#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
3288#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
3289#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
3290#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
3291
3292/* Bit maskes for TWIx_INT_STAT */
3293
3294#define SINIT 0x1 /* Slave Transfer Initiated */
3295#define SCOMP 0x2 /* Slave Transfer Complete */
3296#define SERR 0x4 /* Slave Transfer Error */
3297#define SOVF 0x8 /* Slave Overflow */
3298#define MCOMP 0x10 /* Master Transfer Complete */
3299#define MERR 0x20 /* Master Transfer Error */
3300#define XMTSERV 0x40 /* Transmit FIFO Service */
3301#define RCVSERV 0x80 /* Receive FIFO Service */
3302
3303/* Bit maskes for TWIx_XMT_DATA8 */
3304
3305#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
3306
3307/* Bit maskes for TWIx_XMT_DATA16 */
3308
3309#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
3310
3311/* Bit maskes for TWIx_RCV_DATA8 */
3312
3313#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
3314
3315/* Bit maskes for TWIx_RCV_DATA16 */
3316
3317#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
3318
3319/* Bit masks for SPORTx_TCR1 */
3320
3321#define TCKFE 0x4000 /* Clock Falling Edge Select */
3322#define LATFS 0x2000 /* Late Transmit Frame Sync */
3323#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
3324#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
3325#define TFSR 0x400 /* Transmit Frame Sync Required Select */
3326#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
3327#define TLSBIT 0x10 /* Transmit Bit Order */
3328#define TDTYPE 0xc /* Data Formatting Type Select */
3329#define ITCLK 0x2 /* Internal Transmit Clock Select */
3330#define TSPEN 0x1 /* Transmit Enable */
3331
3332/* Bit masks for SPORTx_TCR2 */
3333
3334#define TRFST 0x400 /* Left/Right Order */
3335#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
3336#define TXSE 0x100 /* TxSEC Enable */
3337#define SLEN_T 0x1f /* SPORT Word Length */
3338
3339/* Bit masks for SPORTx_RCR1 */
3340
3341#define RCKFE 0x4000 /* Clock Falling Edge Select */
3342#define LARFS 0x2000 /* Late Receive Frame Sync */
3343#define LRFS 0x1000 /* Low Receive Frame Sync Select */
3344#define RFSR 0x400 /* Receive Frame Sync Required Select */
3345#define IRFS 0x200 /* Internal Receive Frame Sync Select */
3346#define RLSBIT 0x10 /* Receive Bit Order */
3347#define RDTYPE 0xc /* Data Formatting Type Select */
3348#define IRCLK 0x2 /* Internal Receive Clock Select */
3349#define RSPEN 0x1 /* Receive Enable */
3350
3351/* Bit masks for SPORTx_RCR2 */
3352
3353#define RRFST 0x400 /* Left/Right Order */
3354#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
3355#define RXSE 0x100 /* RxSEC Enable */
3356#define SLEN_R 0x1f /* SPORT Word Length */
3357
3358/* Bit masks for SPORTx_STAT */
3359
3360#define TXHRE 0x40 /* Transmit Hold Register Empty */
3361#define TOVF 0x20 /* Sticky Transmit Overflow Status */
3362#define TUVF 0x10 /* Sticky Transmit Underflow Status */
3363#define TXF 0x8 /* Transmit FIFO Full Status */
3364#define ROVF 0x4 /* Sticky Receive Overflow Status */
3365#define RUVF 0x2 /* Sticky Receive Underflow Status */
3366#define RXNE 0x1 /* Receive FIFO Not Empty Status */
3367
3368/* Bit masks for SPORTx_MCMC1 */
3369
3370#define SP_WSIZE 0xf000 /* Window Size */
3371#define SP_WOFF 0x3ff /* Windows Offset */
3372
3373/* Bit masks for SPORTx_MCMC2 */
3374
3375#define MFD 0xf000 /* Multi channel Frame Delay */
3376#define FSDR 0x80 /* Frame Sync to Data Relationship */
3377#define MCMEN 0x10 /* Multi channel Frame Mode Enable */
3378#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
3379#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
3380#define MCCRM 0x3 /* 2X Clock Recovery Mode */
3381
3382/* Bit masks for SPORTx_CHNL */
3383
3384#define CUR_CHNL 0x3ff /* Current Channel Indicator */
3385
3386/* Bit masks for UARTx_LCR */
3387
3388#if 0
3389/* conflicts with legacy one in last section */
3390#define WLS 0x3 /* Word Length Select */
3391#endif
3392#define STB 0x4 /* Stop Bits */
3393#define PEN 0x8 /* Parity Enable */
3394#define EPS 0x10 /* Even Parity Select */
3395#define STP 0x20 /* Sticky Parity */
3396#define SB 0x40 /* Set Break */
3397
3398/* Bit masks for UARTx_MCR */
3399
3400#define XOFF 0x1 /* Transmitter Off */
3401#define MRTS 0x2 /* Manual Request To Send */
3402#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
3403#define RFRT 0x8 /* Receive FIFO RTS Threshold */
3404#define LOOP_ENA 0x10 /* Loopback Mode Enable */
3405#define FCPOL 0x20 /* Flow Control Pin Polarity */
3406#define ARTS 0x40 /* Automatic Request To Send */
3407#define ACTS 0x80 /* Automatic Clear To Send */
3408
3409/* Bit masks for UARTx_LSR */
3410
3411#define DR 0x1 /* Data Ready */
3412#define OE 0x2 /* Overrun Error */
3413#define PE 0x4 /* Parity Error */
3414#define FE 0x8 /* Framing Error */
3415#define BI 0x10 /* Break Interrupt */
3416#define THRE 0x20 /* THR Empty */
3417#define TEMT 0x40 /* Transmitter Empty */
3418#define TFI 0x80 /* Transmission Finished Indicator */
3419
3420/* Bit masks for UARTx_MSR */
3421
3422#define SCTS 0x1 /* Sticky CTS */
3423#define CTS 0x10 /* Clear To Send */
3424#define RFCS 0x20 /* Receive FIFO Count Status */
3425
3426/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
3427
3428#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
3429#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
3430#define ELSI 0x4 /* Enable Receive Status Interrupt */
3431#define EDSSI 0x8 /* Enable Modem Status Interrupt */
3432#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
3433#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
3434#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
3435
3436/* Bit masks for UARTx_GCTL */
3437
3438#define UCEN 0x1 /* UART Enable */
3439#define IREN 0x2 /* IrDA Mode Enable */
3440#define TPOLC 0x4 /* IrDA TX Polarity Change */
3441#define RPOLC 0x8 /* IrDA RX Polarity Change */
3442#define FPE 0x10 /* Force Parity Error */
3443#define FFE 0x20 /* Force Framing Error */
3444#define EDBO 0x40 /* Enable Divide-by-One */
3445#define EGLSI 0x80 /* Enable Global LS Interrupt */
3446
3447
3448/* ******************************************* */
3449/* MULTI BIT MACRO ENUMERATIONS */
3450/* ******************************************* */
3451
3452/* BCODE bit field options (SYSCFG register) */
3453
3454#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
3455#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
3456#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
3457#define BCODE_NOBOOT 0x0030 /* always perform full boot */
3458
3459/* CNT_COMMAND bit field options */
3460
3461#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
3462#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
3463#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
3464
3465#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
3466#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
3467#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
3468
3469#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
3470#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
3471#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
3472
3473/* CNT_CONFIG bit field options */
3474
3475#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
3476#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
3477#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
3478#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
3479#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
3480
3481#define BNDMODE_COMP 0x0000 /* boundary compare mode */
3482#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
3483#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
3484#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
3485
3486/* TMODE in TIMERx_CONFIG bit field options */
3487
3488#define PWM_OUT 0x0001
3489#define WDTH_CAP 0x0002
3490#define EXT_CLK 0x0003
3491
3492/* UARTx_LCR bit field options */
3493
3494#define WLS_5 0x0000 /* 5 data bits */
3495#define WLS_6 0x0001 /* 6 data bits */
3496#define WLS_7 0x0002 /* 7 data bits */
3497#define WLS_8 0x0003 /* 8 data bits */
3498
3499/* PINTx Register Bit Definitions */
3500
3501#define PIQ0 0x00000001
3502#define PIQ1 0x00000002
3503#define PIQ2 0x00000004
3504#define PIQ3 0x00000008
3505
3506#define PIQ4 0x00000010
3507#define PIQ5 0x00000020
3508#define PIQ6 0x00000040
3509#define PIQ7 0x00000080
3510
3511#define PIQ8 0x00000100
3512#define PIQ9 0x00000200
3513#define PIQ10 0x00000400
3514#define PIQ11 0x00000800
3515
3516#define PIQ12 0x00001000
3517#define PIQ13 0x00002000
3518#define PIQ14 0x00004000
3519#define PIQ15 0x00008000
3520
3521#define PIQ16 0x00010000
3522#define PIQ17 0x00020000
3523#define PIQ18 0x00040000
3524#define PIQ19 0x00080000
3525
3526#define PIQ20 0x00100000
3527#define PIQ21 0x00200000
3528#define PIQ22 0x00400000
3529#define PIQ23 0x00800000
3530
3531#define PIQ24 0x01000000
3532#define PIQ25 0x02000000
3533#define PIQ26 0x04000000
3534#define PIQ27 0x08000000
3535
3536#define PIQ28 0x10000000
3537#define PIQ29 0x20000000
3538#define PIQ30 0x40000000
3539#define PIQ31 0x80000000
3540
3541/* PORT A Bit Definitions for the registers
3542PORTA, PORTA_SET, PORTA_CLEAR,
3543PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
3544PORTA_FER registers
3545*/
3546
3547#define PA0 0x0001
3548#define PA1 0x0002
3549#define PA2 0x0004
3550#define PA3 0x0008
3551#define PA4 0x0010
3552#define PA5 0x0020
3553#define PA6 0x0040
3554#define PA7 0x0080
3555#define PA8 0x0100
3556#define PA9 0x0200
3557#define PA10 0x0400
3558#define PA11 0x0800
3559#define PA12 0x1000
3560#define PA13 0x2000
3561#define PA14 0x4000
3562#define PA15 0x8000
3563
3564/* PORT B Bit Definitions for the registers
3565PORTB, PORTB_SET, PORTB_CLEAR,
3566PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
3567PORTB_FER registers
3568*/
3569
3570#define PB0 0x0001
3571#define PB1 0x0002
3572#define PB2 0x0004
3573#define PB3 0x0008
3574#define PB4 0x0010
3575#define PB5 0x0020
3576#define PB6 0x0040
3577#define PB7 0x0080
3578#define PB8 0x0100
3579#define PB9 0x0200
3580#define PB10 0x0400
3581#define PB11 0x0800
3582#define PB12 0x1000
3583#define PB13 0x2000
3584#define PB14 0x4000
3585
3586
3587/* PORT C Bit Definitions for the registers
3588PORTC, PORTC_SET, PORTC_CLEAR,
3589PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
3590PORTC_FER registers
3591*/
3592
3593
3594#define PC0 0x0001
3595#define PC1 0x0002
3596#define PC2 0x0004
3597#define PC3 0x0008
3598#define PC4 0x0010
3599#define PC5 0x0020
3600#define PC6 0x0040
3601#define PC7 0x0080
3602#define PC8 0x0100
3603#define PC9 0x0200
3604#define PC10 0x0400
3605#define PC11 0x0800
3606#define PC12 0x1000
3607#define PC13 0x2000
3608
3609
3610/* PORT D Bit Definitions for the registers
3611PORTD, PORTD_SET, PORTD_CLEAR,
3612PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
3613PORTD_FER registers
3614*/
3615
3616#define PD0 0x0001
3617#define PD1 0x0002
3618#define PD2 0x0004
3619#define PD3 0x0008
3620#define PD4 0x0010
3621#define PD5 0x0020
3622#define PD6 0x0040
3623#define PD7 0x0080
3624#define PD8 0x0100
3625#define PD9 0x0200
3626#define PD10 0x0400
3627#define PD11 0x0800
3628#define PD12 0x1000
3629#define PD13 0x2000
3630#define PD14 0x4000
3631#define PD15 0x8000
3632
3633/* PORT E Bit Definitions for the registers
3634PORTE, PORTE_SET, PORTE_CLEAR,
3635PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
3636PORTE_FER registers
3637*/
3638
3639
3640#define PE0 0x0001
3641#define PE1 0x0002
3642#define PE2 0x0004
3643#define PE3 0x0008
3644#define PE4 0x0010
3645#define PE5 0x0020
3646#define PE6 0x0040
3647#define PE7 0x0080
3648#define PE8 0x0100
3649#define PE9 0x0200
3650#define PE10 0x0400
3651#define PE11 0x0800
3652#define PE12 0x1000
3653#define PE13 0x2000
3654#define PE14 0x4000
3655#define PE15 0x8000
3656
3657/* PORT F Bit Definitions for the registers
3658PORTF, PORTF_SET, PORTF_CLEAR,
3659PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
3660PORTF_FER registers
3661*/
3662
3663
3664#define PF0 0x0001
3665#define PF1 0x0002
3666#define PF2 0x0004
3667#define PF3 0x0008
3668#define PF4 0x0010
3669#define PF5 0x0020
3670#define PF6 0x0040
3671#define PF7 0x0080
3672#define PF8 0x0100
3673#define PF9 0x0200
3674#define PF10 0x0400
3675#define PF11 0x0800
3676#define PF12 0x1000
3677#define PF13 0x2000
3678#define PF14 0x4000
3679#define PF15 0x8000
3680
3681/* PORT G Bit Definitions for the registers
3682PORTG, PORTG_SET, PORTG_CLEAR,
3683PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
3684PORTG_FER registers
3685*/
3686
3687
3688#define PG0 0x0001
3689#define PG1 0x0002
3690#define PG2 0x0004
3691#define PG3 0x0008
3692#define PG4 0x0010
3693#define PG5 0x0020
3694#define PG6 0x0040
3695#define PG7 0x0080
3696#define PG8 0x0100
3697#define PG9 0x0200
3698#define PG10 0x0400
3699#define PG11 0x0800
3700#define PG12 0x1000
3701#define PG13 0x2000
3702#define PG14 0x4000
3703#define PG15 0x8000
3704
3705/* PORT H Bit Definitions for the registers
3706PORTH, PORTH_SET, PORTH_CLEAR,
3707PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
3708PORTH_FER registers
3709*/
3710
3711
3712#define PH0 0x0001
3713#define PH1 0x0002
3714#define PH2 0x0004
3715#define PH3 0x0008
3716#define PH4 0x0010
3717#define PH5 0x0020
3718#define PH6 0x0040
3719#define PH7 0x0080
3720#define PH8 0x0100
3721#define PH9 0x0200
3722#define PH10 0x0400
3723#define PH11 0x0800
3724#define PH12 0x1000
3725#define PH13 0x2000
3726
3727
3728/* PORT I Bit Definitions for the registers
3729PORTI, PORTI_SET, PORTI_CLEAR,
3730PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
3731PORTI_FER registers
3732*/
3733
3734
3735#define PI0 0x0001
3736#define PI1 0x0002
3737#define PI2 0x0004
3738#define PI3 0x0008
3739#define PI4 0x0010
3740#define PI5 0x0020
3741#define PI6 0x0040
3742#define PI7 0x0080
3743#define PI8 0x0100
3744#define PI9 0x0200
3745#define PI10 0x0400
3746#define PI11 0x0800
3747#define PI12 0x1000
3748#define PI13 0x2000
3749#define PI14 0x4000
3750#define PI15 0x8000
3751
3752/* PORT J Bit Definitions for the registers
3753PORTJ, PORTJ_SET, PORTJ_CLEAR,
3754PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
3755PORTJ_FER registers
3756*/
3757
3758
3759#define PJ0 0x0001
3760#define PJ1 0x0002
3761#define PJ2 0x0004
3762#define PJ3 0x0008
3763#define PJ4 0x0010
3764#define PJ5 0x0020
3765#define PJ6 0x0040
3766#define PJ7 0x0080
3767#define PJ8 0x0100
3768#define PJ9 0x0200
3769#define PJ10 0x0400
3770#define PJ11 0x0800
3771#define PJ12 0x1000
3772#define PJ13 0x2000
3773
3774
3775/* Port Muxing Bit Fields for PORTx_MUX Registers */
3776
3777#define MUX0 0x00000003
3778#define MUX0_0 0x00000000
3779#define MUX0_1 0x00000001
3780#define MUX0_2 0x00000002
3781#define MUX0_3 0x00000003
3782
3783#define MUX1 0x0000000C
3784#define MUX1_0 0x00000000
3785#define MUX1_1 0x00000004
3786#define MUX1_2 0x00000008
3787#define MUX1_3 0x0000000C
3788
3789#define MUX2 0x00000030
3790#define MUX2_0 0x00000000
3791#define MUX2_1 0x00000010
3792#define MUX2_2 0x00000020
3793#define MUX2_3 0x00000030
3794
3795#define MUX3 0x000000C0
3796#define MUX3_0 0x00000000
3797#define MUX3_1 0x00000040
3798#define MUX3_2 0x00000080
3799#define MUX3_3 0x000000C0
3800
3801#define MUX4 0x00000300
3802#define MUX4_0 0x00000000
3803#define MUX4_1 0x00000100
3804#define MUX4_2 0x00000200
3805#define MUX4_3 0x00000300
3806
3807#define MUX5 0x00000C00
3808#define MUX5_0 0x00000000
3809#define MUX5_1 0x00000400
3810#define MUX5_2 0x00000800
3811#define MUX5_3 0x00000C00
3812
3813#define MUX6 0x00003000
3814#define MUX6_0 0x00000000
3815#define MUX6_1 0x00001000
3816#define MUX6_2 0x00002000
3817#define MUX6_3 0x00003000
3818
3819#define MUX7 0x0000C000
3820#define MUX7_0 0x00000000
3821#define MUX7_1 0x00004000
3822#define MUX7_2 0x00008000
3823#define MUX7_3 0x0000C000
3824
3825#define MUX8 0x00030000
3826#define MUX8_0 0x00000000
3827#define MUX8_1 0x00010000
3828#define MUX8_2 0x00020000
3829#define MUX8_3 0x00030000
3830
3831#define MUX9 0x000C0000
3832#define MUX9_0 0x00000000
3833#define MUX9_1 0x00040000
3834#define MUX9_2 0x00080000
3835#define MUX9_3 0x000C0000
3836
3837#define MUX10 0x00300000
3838#define MUX10_0 0x00000000
3839#define MUX10_1 0x00100000
3840#define MUX10_2 0x00200000
3841#define MUX10_3 0x00300000
3842
3843#define MUX11 0x00C00000
3844#define MUX11_0 0x00000000
3845#define MUX11_1 0x00400000
3846#define MUX11_2 0x00800000
3847#define MUX11_3 0x00C00000
3848
3849#define MUX12 0x03000000
3850#define MUX12_0 0x00000000
3851#define MUX12_1 0x01000000
3852#define MUX12_2 0x02000000
3853#define MUX12_3 0x03000000
3854
3855#define MUX13 0x0C000000
3856#define MUX13_0 0x00000000
3857#define MUX13_1 0x04000000
3858#define MUX13_2 0x08000000
3859#define MUX13_3 0x0C000000
3860
3861#define MUX14 0x30000000
3862#define MUX14_0 0x00000000
3863#define MUX14_1 0x10000000
3864#define MUX14_2 0x20000000
3865#define MUX14_3 0x30000000
3866
3867#define MUX15 0xC0000000
3868#define MUX15_0 0x00000000
3869#define MUX15_1 0x40000000
3870#define MUX15_2 0x80000000
3871#define MUX15_3 0xC0000000
3872
3873#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
3874 ((((b15)&3) << 30) | \
3875 (((b14)&3) << 28) | \
3876 (((b13)&3) << 26) | \
3877 (((b12)&3) << 24) | \
3878 (((b11)&3) << 22) | \
3879 (((b10)&3) << 20) | \
3880 (((b9) &3) << 18) | \
3881 (((b8) &3) << 16) | \
3882 (((b7) &3) << 14) | \
3883 (((b6) &3) << 12) | \
3884 (((b5) &3) << 10) | \
3885 (((b4) &3) << 8) | \
3886 (((b3) &3) << 6) | \
3887 (((b2) &3) << 4) | \
3888 (((b1) &3) << 2) | \
3889 (((b0) &3)))
3890
3891/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
3892
3893#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */
3894#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
3895#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
3896#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */
3897#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
3898#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
3899#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */
3900#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
3901#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
3902#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */
3903#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
3904#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
3905
3906/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
3907
3908#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
3909#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
3910#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
3911#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
3912#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
3913#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
3914#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
3915#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
3916
3917#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
3918#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
3919#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
3920#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
3921#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
3922#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
3923#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
3924#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
3925
3926#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
3927#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
3928#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
3929#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
3930#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
3931#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
3932#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
3933#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
3934
3935#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
3936#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
3937#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
3938#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
3939#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
3940#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
3941#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
3942#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
3943
3944
3945/* for legacy compatibility */
3946
3947#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
3948#define W1LMAX_MAX W1LMAX_MIN
3949#define EBIU_AMCBCTL0 EBIU_AMBCTL0
3950#define EBIU_AMCBCTL1 EBIU_AMBCTL1
3951#define PINT0_IRQ PINT0_REQUEST
3952#define PINT1_IRQ PINT1_REQUEST
3953#define PINT2_IRQ PINT2_REQUEST
3954#define PINT3_IRQ PINT3_REQUEST
3955
3956#endif /* _DEF_BF54X_H */
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
deleted file mode 100644
index 36a2ef7e7849..000000000000
--- a/include/asm-blackfin/mach-bf548/dma.h
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/dma.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define CH_SPORT0_RX 0
36#define CH_SPORT0_TX 1
37#define CH_SPORT1_RX 2
38#define CH_SPORT1_TX 3
39#define CH_SPI0 4
40#define CH_SPI1 5
41#define CH_UART0_RX 6
42#define CH_UART0_TX 7
43#define CH_UART1_RX 8
44#define CH_UART1_TX 9
45#define CH_ATAPI_RX 10
46#define CH_ATAPI_TX 11
47#define CH_EPPI0 12
48#define CH_EPPI1 13
49#define CH_EPPI2 14
50#define CH_PIXC_IMAGE 15
51#define CH_PIXC_OVERLAY 16
52#define CH_PIXC_OUTPUT 17
53#define CH_SPORT2_RX 18
54#define CH_UART2_RX 18
55#define CH_SPORT2_TX 19
56#define CH_UART2_TX 19
57#define CH_SPORT3_RX 20
58#define CH_UART3_RX 20
59#define CH_SPORT3_TX 21
60#define CH_UART3_TX 21
61#define CH_SDH 22
62#define CH_NFC 22
63#define CH_SPI2 23
64
65#define CH_MEM_STREAM0_DEST 24
66#define CH_MEM_STREAM0_SRC 25
67#define CH_MEM_STREAM1_DEST 26
68#define CH_MEM_STREAM1_SRC 27
69#define CH_MEM_STREAM2_DEST 28
70#define CH_MEM_STREAM2_SRC 29
71#define CH_MEM_STREAM3_DEST 30
72#define CH_MEM_STREAM3_SRC 31
73
74#define MAX_BLACKFIN_DMA_CHANNEL 32
75
76#endif
diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h
deleted file mode 100644
index bba82dc75f16..000000000000
--- a/include/asm-blackfin/mach-bf548/gpio.h
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/gpio.h
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30
31
32#define GPIO_PA0 0
33#define GPIO_PA1 1
34#define GPIO_PA2 2
35#define GPIO_PA3 3
36#define GPIO_PA4 4
37#define GPIO_PA5 5
38#define GPIO_PA6 6
39#define GPIO_PA7 7
40#define GPIO_PA8 8
41#define GPIO_PA9 9
42#define GPIO_PA10 10
43#define GPIO_PA11 11
44#define GPIO_PA12 12
45#define GPIO_PA13 13
46#define GPIO_PA14 14
47#define GPIO_PA15 15
48#define GPIO_PB0 16
49#define GPIO_PB1 17
50#define GPIO_PB2 18
51#define GPIO_PB3 19
52#define GPIO_PB4 20
53#define GPIO_PB5 21
54#define GPIO_PB6 22
55#define GPIO_PB7 23
56#define GPIO_PB8 24
57#define GPIO_PB9 25
58#define GPIO_PB10 26
59#define GPIO_PB11 27
60#define GPIO_PB12 28
61#define GPIO_PB13 29
62#define GPIO_PB14 30
63#define GPIO_PB15 31 /* N/A */
64#define GPIO_PC0 32
65#define GPIO_PC1 33
66#define GPIO_PC2 34
67#define GPIO_PC3 35
68#define GPIO_PC4 36
69#define GPIO_PC5 37
70#define GPIO_PC6 38
71#define GPIO_PC7 39
72#define GPIO_PC8 40
73#define GPIO_PC9 41
74#define GPIO_PC10 42
75#define GPIO_PC11 43
76#define GPIO_PC12 44
77#define GPIO_PC13 45
78#define GPIO_PC14 46 /* N/A */
79#define GPIO_PC15 47 /* N/A */
80#define GPIO_PD0 48
81#define GPIO_PD1 49
82#define GPIO_PD2 50
83#define GPIO_PD3 51
84#define GPIO_PD4 52
85#define GPIO_PD5 53
86#define GPIO_PD6 54
87#define GPIO_PD7 55
88#define GPIO_PD8 56
89#define GPIO_PD9 57
90#define GPIO_PD10 58
91#define GPIO_PD11 59
92#define GPIO_PD12 60
93#define GPIO_PD13 61
94#define GPIO_PD14 62
95#define GPIO_PD15 63
96#define GPIO_PE0 64
97#define GPIO_PE1 65
98#define GPIO_PE2 66
99#define GPIO_PE3 67
100#define GPIO_PE4 68
101#define GPIO_PE5 69
102#define GPIO_PE6 70
103#define GPIO_PE7 71
104#define GPIO_PE8 72
105#define GPIO_PE9 73
106#define GPIO_PE10 74
107#define GPIO_PE11 75
108#define GPIO_PE12 76
109#define GPIO_PE13 77
110#define GPIO_PE14 78
111#define GPIO_PE15 79
112#define GPIO_PF0 80
113#define GPIO_PF1 81
114#define GPIO_PF2 82
115#define GPIO_PF3 83
116#define GPIO_PF4 84
117#define GPIO_PF5 85
118#define GPIO_PF6 86
119#define GPIO_PF7 87
120#define GPIO_PF8 88
121#define GPIO_PF9 89
122#define GPIO_PF10 90
123#define GPIO_PF11 91
124#define GPIO_PF12 92
125#define GPIO_PF13 93
126#define GPIO_PF14 94
127#define GPIO_PF15 95
128#define GPIO_PG0 96
129#define GPIO_PG1 97
130#define GPIO_PG2 98
131#define GPIO_PG3 99
132#define GPIO_PG4 100
133#define GPIO_PG5 101
134#define GPIO_PG6 102
135#define GPIO_PG7 103
136#define GPIO_PG8 104
137#define GPIO_PG9 105
138#define GPIO_PG10 106
139#define GPIO_PG11 107
140#define GPIO_PG12 108
141#define GPIO_PG13 109
142#define GPIO_PG14 110
143#define GPIO_PG15 111
144#define GPIO_PH0 112
145#define GPIO_PH1 113
146#define GPIO_PH2 114
147#define GPIO_PH3 115
148#define GPIO_PH4 116
149#define GPIO_PH5 117
150#define GPIO_PH6 118
151#define GPIO_PH7 119
152#define GPIO_PH8 120
153#define GPIO_PH9 121
154#define GPIO_PH10 122
155#define GPIO_PH11 123
156#define GPIO_PH12 124
157#define GPIO_PH13 125
158#define GPIO_PH14 126 /* N/A */
159#define GPIO_PH15 127 /* N/A */
160#define GPIO_PI0 128
161#define GPIO_PI1 129
162#define GPIO_PI2 130
163#define GPIO_PI3 131
164#define GPIO_PI4 132
165#define GPIO_PI5 133
166#define GPIO_PI6 134
167#define GPIO_PI7 135
168#define GPIO_PI8 136
169#define GPIO_PI9 137
170#define GPIO_PI10 138
171#define GPIO_PI11 139
172#define GPIO_PI12 140
173#define GPIO_PI13 141
174#define GPIO_PI14 142
175#define GPIO_PI15 143
176#define GPIO_PJ0 144
177#define GPIO_PJ1 145
178#define GPIO_PJ2 146
179#define GPIO_PJ3 147
180#define GPIO_PJ4 148
181#define GPIO_PJ5 149
182#define GPIO_PJ6 150
183#define GPIO_PJ7 151
184#define GPIO_PJ8 152
185#define GPIO_PJ9 153
186#define GPIO_PJ10 154
187#define GPIO_PJ11 155
188#define GPIO_PJ12 156
189#define GPIO_PJ13 157
190#define GPIO_PJ14 158 /* N/A */
191#define GPIO_PJ15 159 /* N/A */
192
193#define MAX_BLACKFIN_GPIOS 160
194
195struct gpio_port_t {
196 unsigned short port_fer;
197 unsigned short dummy1;
198 unsigned short port_data;
199 unsigned short dummy2;
200 unsigned short port_set;
201 unsigned short dummy3;
202 unsigned short port_clear;
203 unsigned short dummy4;
204 unsigned short port_dir_set;
205 unsigned short dummy5;
206 unsigned short port_dir_clear;
207 unsigned short dummy6;
208 unsigned short port_inen;
209 unsigned short dummy7;
210 unsigned int port_mux;
211};
212
213struct gpio_port_s {
214 unsigned short fer;
215 unsigned short data;
216 unsigned short dir;
217 unsigned short inen;
218 unsigned int mux;
219};
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
deleted file mode 100644
index ad380d1f5872..000000000000
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ /dev/null
@@ -1,501 +0,0 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/irq.h
3 * based on: include/asm-blackfin/mach-bf537/irq.h
4 * author: Roy Huang (roy.huang@analog.com)
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF548_IRQ_H_
33#define _BF548_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38Core Emulation **
39Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47.....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52 */
53
54#define NR_PERI_INTS (32 * 3)
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /* Emulation */
59#define IRQ_RST 1 /* reset */
60#define IRQ_NMI 2 /* Non Maskable */
61#define IRQ_EVX 3 /* Exception */
62#define IRQ_UNUSED 4 /* - unused interrupt*/
63#define IRQ_HWERR 5 /* Hardware Error */
64#define IRQ_CORETMR 6 /* Core timer */
65
66#define BFIN_IRQ(x) ((x) + 7)
67
68#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
69#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
70#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
71#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
72#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
73#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
74#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
75#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
76#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
77#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
78#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
79#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
80#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
81#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
82#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
83#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
84#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
85#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
86#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
87#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
91#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
95#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
96#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
97#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
98#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
99#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
100#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
101#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
102#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
103#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
104#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
105#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
106#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
107#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
108#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
109#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
110#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
111#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
112#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
113#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
114#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
115#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
116#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
117#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
118#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
119#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
120#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
121#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
122#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
123#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
124#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
125#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
126#define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
127#define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
128#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
129#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
130#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
131#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
132#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
133#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
134#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
135#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
136#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
137#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
138#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
139#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
140#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
141#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
142#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
143#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
144#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
145#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
146#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
147#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
148#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
149#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
150#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
151#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
152#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
153#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
154#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
155#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
156#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
157#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
158#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
159#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
160
161#define SYS_IRQS IRQ_PINT3
162
163#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
164#define IRQ_PA0 BFIN_PA_IRQ(0)
165#define IRQ_PA1 BFIN_PA_IRQ(1)
166#define IRQ_PA2 BFIN_PA_IRQ(2)
167#define IRQ_PA3 BFIN_PA_IRQ(3)
168#define IRQ_PA4 BFIN_PA_IRQ(4)
169#define IRQ_PA5 BFIN_PA_IRQ(5)
170#define IRQ_PA6 BFIN_PA_IRQ(6)
171#define IRQ_PA7 BFIN_PA_IRQ(7)
172#define IRQ_PA8 BFIN_PA_IRQ(8)
173#define IRQ_PA9 BFIN_PA_IRQ(9)
174#define IRQ_PA10 BFIN_PA_IRQ(10)
175#define IRQ_PA11 BFIN_PA_IRQ(11)
176#define IRQ_PA12 BFIN_PA_IRQ(12)
177#define IRQ_PA13 BFIN_PA_IRQ(13)
178#define IRQ_PA14 BFIN_PA_IRQ(14)
179#define IRQ_PA15 BFIN_PA_IRQ(15)
180
181#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
182#define IRQ_PB0 BFIN_PB_IRQ(0)
183#define IRQ_PB1 BFIN_PB_IRQ(1)
184#define IRQ_PB2 BFIN_PB_IRQ(2)
185#define IRQ_PB3 BFIN_PB_IRQ(3)
186#define IRQ_PB4 BFIN_PB_IRQ(4)
187#define IRQ_PB5 BFIN_PB_IRQ(5)
188#define IRQ_PB6 BFIN_PB_IRQ(6)
189#define IRQ_PB7 BFIN_PB_IRQ(7)
190#define IRQ_PB8 BFIN_PB_IRQ(8)
191#define IRQ_PB9 BFIN_PB_IRQ(9)
192#define IRQ_PB10 BFIN_PB_IRQ(10)
193#define IRQ_PB11 BFIN_PB_IRQ(11)
194#define IRQ_PB12 BFIN_PB_IRQ(12)
195#define IRQ_PB13 BFIN_PB_IRQ(13)
196#define IRQ_PB14 BFIN_PB_IRQ(14)
197#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
198
199#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
200#define IRQ_PC0 BFIN_PC_IRQ(0)
201#define IRQ_PC1 BFIN_PC_IRQ(1)
202#define IRQ_PC2 BFIN_PC_IRQ(2)
203#define IRQ_PC3 BFIN_PC_IRQ(3)
204#define IRQ_PC4 BFIN_PC_IRQ(4)
205#define IRQ_PC5 BFIN_PC_IRQ(5)
206#define IRQ_PC6 BFIN_PC_IRQ(6)
207#define IRQ_PC7 BFIN_PC_IRQ(7)
208#define IRQ_PC8 BFIN_PC_IRQ(8)
209#define IRQ_PC9 BFIN_PC_IRQ(9)
210#define IRQ_PC10 BFIN_PC_IRQ(10)
211#define IRQ_PC11 BFIN_PC_IRQ(11)
212#define IRQ_PC12 BFIN_PC_IRQ(12)
213#define IRQ_PC13 BFIN_PC_IRQ(13)
214#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
215#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
216
217#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
218#define IRQ_PD0 BFIN_PD_IRQ(0)
219#define IRQ_PD1 BFIN_PD_IRQ(1)
220#define IRQ_PD2 BFIN_PD_IRQ(2)
221#define IRQ_PD3 BFIN_PD_IRQ(3)
222#define IRQ_PD4 BFIN_PD_IRQ(4)
223#define IRQ_PD5 BFIN_PD_IRQ(5)
224#define IRQ_PD6 BFIN_PD_IRQ(6)
225#define IRQ_PD7 BFIN_PD_IRQ(7)
226#define IRQ_PD8 BFIN_PD_IRQ(8)
227#define IRQ_PD9 BFIN_PD_IRQ(9)
228#define IRQ_PD10 BFIN_PD_IRQ(10)
229#define IRQ_PD11 BFIN_PD_IRQ(11)
230#define IRQ_PD12 BFIN_PD_IRQ(12)
231#define IRQ_PD13 BFIN_PD_IRQ(13)
232#define IRQ_PD14 BFIN_PD_IRQ(14)
233#define IRQ_PD15 BFIN_PD_IRQ(15)
234
235#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
236#define IRQ_PE0 BFIN_PE_IRQ(0)
237#define IRQ_PE1 BFIN_PE_IRQ(1)
238#define IRQ_PE2 BFIN_PE_IRQ(2)
239#define IRQ_PE3 BFIN_PE_IRQ(3)
240#define IRQ_PE4 BFIN_PE_IRQ(4)
241#define IRQ_PE5 BFIN_PE_IRQ(5)
242#define IRQ_PE6 BFIN_PE_IRQ(6)
243#define IRQ_PE7 BFIN_PE_IRQ(7)
244#define IRQ_PE8 BFIN_PE_IRQ(8)
245#define IRQ_PE9 BFIN_PE_IRQ(9)
246#define IRQ_PE10 BFIN_PE_IRQ(10)
247#define IRQ_PE11 BFIN_PE_IRQ(11)
248#define IRQ_PE12 BFIN_PE_IRQ(12)
249#define IRQ_PE13 BFIN_PE_IRQ(13)
250#define IRQ_PE14 BFIN_PE_IRQ(14)
251#define IRQ_PE15 BFIN_PE_IRQ(15)
252
253#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
254#define IRQ_PF0 BFIN_PF_IRQ(0)
255#define IRQ_PF1 BFIN_PF_IRQ(1)
256#define IRQ_PF2 BFIN_PF_IRQ(2)
257#define IRQ_PF3 BFIN_PF_IRQ(3)
258#define IRQ_PF4 BFIN_PF_IRQ(4)
259#define IRQ_PF5 BFIN_PF_IRQ(5)
260#define IRQ_PF6 BFIN_PF_IRQ(6)
261#define IRQ_PF7 BFIN_PF_IRQ(7)
262#define IRQ_PF8 BFIN_PF_IRQ(8)
263#define IRQ_PF9 BFIN_PF_IRQ(9)
264#define IRQ_PF10 BFIN_PF_IRQ(10)
265#define IRQ_PF11 BFIN_PF_IRQ(11)
266#define IRQ_PF12 BFIN_PF_IRQ(12)
267#define IRQ_PF13 BFIN_PF_IRQ(13)
268#define IRQ_PF14 BFIN_PF_IRQ(14)
269#define IRQ_PF15 BFIN_PF_IRQ(15)
270
271#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
272#define IRQ_PG0 BFIN_PG_IRQ(0)
273#define IRQ_PG1 BFIN_PG_IRQ(1)
274#define IRQ_PG2 BFIN_PG_IRQ(2)
275#define IRQ_PG3 BFIN_PG_IRQ(3)
276#define IRQ_PG4 BFIN_PG_IRQ(4)
277#define IRQ_PG5 BFIN_PG_IRQ(5)
278#define IRQ_PG6 BFIN_PG_IRQ(6)
279#define IRQ_PG7 BFIN_PG_IRQ(7)
280#define IRQ_PG8 BFIN_PG_IRQ(8)
281#define IRQ_PG9 BFIN_PG_IRQ(9)
282#define IRQ_PG10 BFIN_PG_IRQ(10)
283#define IRQ_PG11 BFIN_PG_IRQ(11)
284#define IRQ_PG12 BFIN_PG_IRQ(12)
285#define IRQ_PG13 BFIN_PG_IRQ(13)
286#define IRQ_PG14 BFIN_PG_IRQ(14)
287#define IRQ_PG15 BFIN_PG_IRQ(15)
288
289#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1)
290#define IRQ_PH0 BFIN_PH_IRQ(0)
291#define IRQ_PH1 BFIN_PH_IRQ(1)
292#define IRQ_PH2 BFIN_PH_IRQ(2)
293#define IRQ_PH3 BFIN_PH_IRQ(3)
294#define IRQ_PH4 BFIN_PH_IRQ(4)
295#define IRQ_PH5 BFIN_PH_IRQ(5)
296#define IRQ_PH6 BFIN_PH_IRQ(6)
297#define IRQ_PH7 BFIN_PH_IRQ(7)
298#define IRQ_PH8 BFIN_PH_IRQ(8)
299#define IRQ_PH9 BFIN_PH_IRQ(9)
300#define IRQ_PH10 BFIN_PH_IRQ(10)
301#define IRQ_PH11 BFIN_PH_IRQ(11)
302#define IRQ_PH12 BFIN_PH_IRQ(12)
303#define IRQ_PH13 BFIN_PH_IRQ(13)
304#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */
305#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */
306
307#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1)
308#define IRQ_PI0 BFIN_PI_IRQ(0)
309#define IRQ_PI1 BFIN_PI_IRQ(1)
310#define IRQ_PI2 BFIN_PI_IRQ(2)
311#define IRQ_PI3 BFIN_PI_IRQ(3)
312#define IRQ_PI4 BFIN_PI_IRQ(4)
313#define IRQ_PI5 BFIN_PI_IRQ(5)
314#define IRQ_PI6 BFIN_PI_IRQ(6)
315#define IRQ_PI7 BFIN_PI_IRQ(7)
316#define IRQ_PI8 BFIN_PI_IRQ(8)
317#define IRQ_PI9 BFIN_PI_IRQ(9)
318#define IRQ_PI10 BFIN_PI_IRQ(10)
319#define IRQ_PI11 BFIN_PI_IRQ(11)
320#define IRQ_PI12 BFIN_PI_IRQ(12)
321#define IRQ_PI13 BFIN_PI_IRQ(13)
322#define IRQ_PI14 BFIN_PI_IRQ(14)
323#define IRQ_PI15 BFIN_PI_IRQ(15)
324
325#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1)
326#define IRQ_PJ0 BFIN_PJ_IRQ(0)
327#define IRQ_PJ1 BFIN_PJ_IRQ(1)
328#define IRQ_PJ2 BFIN_PJ_IRQ(2)
329#define IRQ_PJ3 BFIN_PJ_IRQ(3)
330#define IRQ_PJ4 BFIN_PJ_IRQ(4)
331#define IRQ_PJ5 BFIN_PJ_IRQ(5)
332#define IRQ_PJ6 BFIN_PJ_IRQ(6)
333#define IRQ_PJ7 BFIN_PJ_IRQ(7)
334#define IRQ_PJ8 BFIN_PJ_IRQ(8)
335#define IRQ_PJ9 BFIN_PJ_IRQ(9)
336#define IRQ_PJ10 BFIN_PJ_IRQ(10)
337#define IRQ_PJ11 BFIN_PJ_IRQ(11)
338#define IRQ_PJ12 BFIN_PJ_IRQ(12)
339#define IRQ_PJ13 BFIN_PJ_IRQ(13)
340#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
341#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
342
343#define GPIO_IRQ_BASE IRQ_PA0
344
345#define NR_IRQS (IRQ_PJ15+1)
346
347/* For compatibility reasons with existing code */
348
349#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
350#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
351#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
352#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
353#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
354#define IRQ_UART0_ERR IRQ_UART0_ERROR
355#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
356#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
357#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
358#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
359#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
360#define IRQ_UART1_ERR IRQ_UART1_ERROR
361#define IRQ_UART2_ERR IRQ_UART2_ERROR
362#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
363#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
364#define IRQ_EPP1_ERR IRQ_EPP1_ERROR
365#define IRQ_EPP2_ERR IRQ_EPP2_ERROR
366#define IRQ_UART3_ERR IRQ_UART3_ERROR
367#define IRQ_HOST_ERR IRQ_HOST_ERROR
368#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
369#define IRQ_NFC_ERR IRQ_NFC_ERROR
370#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
371#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
372#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
373
374
375#define IVG7 7
376#define IVG8 8
377#define IVG9 9
378#define IVG10 10
379#define IVG11 11
380#define IVG12 12
381#define IVG13 13
382#define IVG14 14
383#define IVG15 15
384
385/* IAR0 BIT FIELDS */
386#define IRQ_PLL_WAKEUP_POS 0
387#define IRQ_DMAC0_ERR_POS 4
388#define IRQ_EPPI0_ERR_POS 8
389#define IRQ_SPORT0_ERR_POS 12
390#define IRQ_SPORT1_ERR_POS 16
391#define IRQ_SPI0_ERR_POS 20
392#define IRQ_UART0_ERR_POS 24
393#define IRQ_RTC_POS 28
394
395/* IAR1 BIT FIELDS */
396#define IRQ_EPPI0_POS 0
397#define IRQ_SPORT0_RX_POS 4
398#define IRQ_SPORT0_TX_POS 8
399#define IRQ_SPORT1_RX_POS 12
400#define IRQ_SPORT1_TX_POS 16
401#define IRQ_SPI0_POS 20
402#define IRQ_UART0_RX_POS 24
403#define IRQ_UART0_TX_POS 28
404
405/* IAR2 BIT FIELDS */
406#define IRQ_TIMER8_POS 0
407#define IRQ_TIMER9_POS 4
408#define IRQ_TIMER10_POS 8
409#define IRQ_PINT0_POS 12
410#define IRQ_PINT1_POS 16
411#define IRQ_MDMAS0_POS 20
412#define IRQ_MDMAS1_POS 24
413#define IRQ_WATCH_POS 28
414
415/* IAR3 BIT FIELDS */
416#define IRQ_DMAC1_ERR_POS 0
417#define IRQ_SPORT2_ERR_POS 4
418#define IRQ_SPORT3_ERR_POS 8
419#define IRQ_MXVR_DATA_POS 12
420#define IRQ_SPI1_ERR_POS 16
421#define IRQ_SPI2_ERR_POS 20
422#define IRQ_UART1_ERR_POS 24
423#define IRQ_UART2_ERR_POS 28
424
425/* IAR4 BIT FILEDS */
426#define IRQ_CAN0_ERR_POS 0
427#define IRQ_SPORT2_RX_POS 4
428#define IRQ_UART2_RX_POS 4
429#define IRQ_SPORT2_TX_POS 8
430#define IRQ_UART2_TX_POS 8
431#define IRQ_SPORT3_RX_POS 12
432#define IRQ_UART3_RX_POS 12
433#define IRQ_SPORT3_TX_POS 16
434#define IRQ_UART3_TX_POS 16
435#define IRQ_EPPI1_POS 20
436#define IRQ_EPPI2_POS 24
437#define IRQ_SPI1_POS 28
438
439/* IAR5 BIT FIELDS */
440#define IRQ_SPI2_POS 0
441#define IRQ_UART1_RX_POS 4
442#define IRQ_UART1_TX_POS 8
443#define IRQ_ATAPI_RX_POS 12
444#define IRQ_ATAPI_TX_POS 16
445#define IRQ_TWI0_POS 20
446#define IRQ_TWI1_POS 24
447#define IRQ_CAN0_RX_POS 28
448
449/* IAR6 BIT FIELDS */
450#define IRQ_CAN0_TX_POS 0
451#define IRQ_MDMAS2_POS 4
452#define IRQ_MDMAS3_POS 8
453#define IRQ_MXVR_ERR_POS 12
454#define IRQ_MXVR_MSG_POS 16
455#define IRQ_MXVR_PKT_POS 20
456#define IRQ_EPPI1_ERR_POS 24
457#define IRQ_EPPI2_ERR_POS 28
458
459/* IAR7 BIT FIELDS */
460#define IRQ_UART3_ERR_POS 0
461#define IRQ_HOST_ERR_POS 4
462#define IRQ_PIXC_ERR_POS 12
463#define IRQ_NFC_ERR_POS 16
464#define IRQ_ATAPI_ERR_POS 20
465#define IRQ_CAN1_ERR_POS 24
466#define IRQ_HS_DMA_ERR_POS 28
467
468/* IAR8 BIT FIELDS */
469#define IRQ_PIXC_IN0_POS 0
470#define IRQ_PIXC_IN1_POS 4
471#define IRQ_PIXC_OUT_POS 8
472#define IRQ_SDH_POS 12
473#define IRQ_CNT_POS 16
474#define IRQ_KEY_POS 20
475#define IRQ_CAN1_RX_POS 24
476#define IRQ_CAN1_TX_POS 28
477
478/* IAR9 BIT FIELDS */
479#define IRQ_SDH_MASK0_POS 0
480#define IRQ_SDH_MASK1_POS 4
481#define IRQ_USB_INT0_POS 12
482#define IRQ_USB_INT1_POS 16
483#define IRQ_USB_INT2_POS 20
484#define IRQ_USB_DMA_POS 24
485#define IRQ_OTPSEC_POS 28
486
487/* IAR10 BIT FIELDS */
488#define IRQ_TIMER0_POS 24
489#define IRQ_TIMER1_POS 28
490
491/* IAR11 BIT FIELDS */
492#define IRQ_TIMER2_POS 0
493#define IRQ_TIMER3_POS 4
494#define IRQ_TIMER4_POS 8
495#define IRQ_TIMER5_POS 12
496#define IRQ_TIMER6_POS 16
497#define IRQ_TIMER7_POS 20
498#define IRQ_PINT2_POS 24
499#define IRQ_PINT3_POS 28
500
501#endif /* _BF548_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
deleted file mode 100644
index ab0b863eee66..000000000000
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
33#define DDR_CLK_HZ(x) (1000*1000*1000/x)
34
35#if (CONFIG_MEM_MT46V32M16_6T)
36#define DDR_SIZE DEVSZ_512
37#define DDR_WIDTH DEVWD_16
38#define DDR_MAX_tCK 13
39
40#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
41#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
42#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
43#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
44#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
45
46#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
47#define DDR_tWTR DDR_TWTR(1)
48#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
49#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
50#endif
51
52#if (CONFIG_MEM_MT46V32M16_5B)
53#define DDR_SIZE DEVSZ_512
54#define DDR_WIDTH DEVWD_16
55#define DDR_MAX_tCK 13
56
57#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
58#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
59#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
60#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
61#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
62
63#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
64#define DDR_tWTR DDR_TWTR(2)
65#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
66#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
67#endif
68
69#if (CONFIG_MEM_GENERIC_BOARD)
70#define DDR_SIZE DEVSZ_512
71#define DDR_WIDTH DEVWD_16
72#define DDR_MAX_tCK 13
73
74#define DDR_tRCD DDR_TRCD(3)
75#define DDR_tWTR DDR_TWTR(2)
76#define DDR_tWR DDR_TWR(2)
77#define DDR_tMRD DDR_TMRD(2)
78#define DDR_tRP DDR_TRP(3)
79#define DDR_tRAS DDR_TRAS(7)
80#define DDR_tRC DDR_TRC(10)
81#define DDR_tRFC DDR_TRFC(12)
82#define DDR_tREFI DDR_TREFI(1288)
83#endif
84
85#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
86# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
87#elif(CONFIG_SCLK_HZ <= 133333333)
88# define DDR_CL CL_2
89#else
90# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
91#endif
92
93
94#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
95#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
96 | DDR_tMRD | DDR_tWR | DDR_tRCD)
97#define mem_DDRCTL2 DDR_CL
98
99
100#if defined CONFIG_CLKIN_HALF
101#define CLKIN_HALF 1
102#else
103#define CLKIN_HALF 0
104#endif
105
106#if defined CONFIG_PLL_BYPASS
107#define PLL_BYPASS 1
108#else
109#define PLL_BYPASS 0
110#endif
111
112/***************************************Currently Not Being Used *********************************/
113#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
114#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
115#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
116#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
117#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
118
119#if (flash_EBIU_AMBCTL_TT > 3)
120#define flash_EBIU_AMBCTL0_TT B0TT_4
121#endif
122#if (flash_EBIU_AMBCTL_TT == 3)
123#define flash_EBIU_AMBCTL0_TT B0TT_3
124#endif
125#if (flash_EBIU_AMBCTL_TT == 2)
126#define flash_EBIU_AMBCTL0_TT B0TT_2
127#endif
128#if (flash_EBIU_AMBCTL_TT < 2)
129#define flash_EBIU_AMBCTL0_TT B0TT_1
130#endif
131
132#if (flash_EBIU_AMBCTL_ST > 3)
133#define flash_EBIU_AMBCTL0_ST B0ST_4
134#endif
135#if (flash_EBIU_AMBCTL_ST == 3)
136#define flash_EBIU_AMBCTL0_ST B0ST_3
137#endif
138#if (flash_EBIU_AMBCTL_ST == 2)
139#define flash_EBIU_AMBCTL0_ST B0ST_2
140#endif
141#if (flash_EBIU_AMBCTL_ST < 2)
142#define flash_EBIU_AMBCTL0_ST B0ST_1
143#endif
144
145#if (flash_EBIU_AMBCTL_HT > 2)
146#define flash_EBIU_AMBCTL0_HT B0HT_3
147#endif
148#if (flash_EBIU_AMBCTL_HT == 2)
149#define flash_EBIU_AMBCTL0_HT B0HT_2
150#endif
151#if (flash_EBIU_AMBCTL_HT == 1)
152#define flash_EBIU_AMBCTL0_HT B0HT_1
153#endif
154#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
155#define flash_EBIU_AMBCTL0_HT B0HT_0
156#endif
157#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
158#define flash_EBIU_AMBCTL0_HT B0HT_1
159#endif
160
161#if (flash_EBIU_AMBCTL_WAT > 14)
162#define flash_EBIU_AMBCTL0_WAT B0WAT_15
163#endif
164#if (flash_EBIU_AMBCTL_WAT == 14)
165#define flash_EBIU_AMBCTL0_WAT B0WAT_14
166#endif
167#if (flash_EBIU_AMBCTL_WAT == 13)
168#define flash_EBIU_AMBCTL0_WAT B0WAT_13
169#endif
170#if (flash_EBIU_AMBCTL_WAT == 12)
171#define flash_EBIU_AMBCTL0_WAT B0WAT_12
172#endif
173#if (flash_EBIU_AMBCTL_WAT == 11)
174#define flash_EBIU_AMBCTL0_WAT B0WAT_11
175#endif
176#if (flash_EBIU_AMBCTL_WAT == 10)
177#define flash_EBIU_AMBCTL0_WAT B0WAT_10
178#endif
179#if (flash_EBIU_AMBCTL_WAT == 9)
180#define flash_EBIU_AMBCTL0_WAT B0WAT_9
181#endif
182#if (flash_EBIU_AMBCTL_WAT == 8)
183#define flash_EBIU_AMBCTL0_WAT B0WAT_8
184#endif
185#if (flash_EBIU_AMBCTL_WAT == 7)
186#define flash_EBIU_AMBCTL0_WAT B0WAT_7
187#endif
188#if (flash_EBIU_AMBCTL_WAT == 6)
189#define flash_EBIU_AMBCTL0_WAT B0WAT_6
190#endif
191#if (flash_EBIU_AMBCTL_WAT == 5)
192#define flash_EBIU_AMBCTL0_WAT B0WAT_5
193#endif
194#if (flash_EBIU_AMBCTL_WAT == 4)
195#define flash_EBIU_AMBCTL0_WAT B0WAT_4
196#endif
197#if (flash_EBIU_AMBCTL_WAT == 3)
198#define flash_EBIU_AMBCTL0_WAT B0WAT_3
199#endif
200#if (flash_EBIU_AMBCTL_WAT == 2)
201#define flash_EBIU_AMBCTL0_WAT B0WAT_2
202#endif
203#if (flash_EBIU_AMBCTL_WAT == 1)
204#define flash_EBIU_AMBCTL0_WAT B0WAT_1
205#endif
206
207#if (flash_EBIU_AMBCTL_RAT > 14)
208#define flash_EBIU_AMBCTL0_RAT B0RAT_15
209#endif
210#if (flash_EBIU_AMBCTL_RAT == 14)
211#define flash_EBIU_AMBCTL0_RAT B0RAT_14
212#endif
213#if (flash_EBIU_AMBCTL_RAT == 13)
214#define flash_EBIU_AMBCTL0_RAT B0RAT_13
215#endif
216#if (flash_EBIU_AMBCTL_RAT == 12)
217#define flash_EBIU_AMBCTL0_RAT B0RAT_12
218#endif
219#if (flash_EBIU_AMBCTL_RAT == 11)
220#define flash_EBIU_AMBCTL0_RAT B0RAT_11
221#endif
222#if (flash_EBIU_AMBCTL_RAT == 10)
223#define flash_EBIU_AMBCTL0_RAT B0RAT_10
224#endif
225#if (flash_EBIU_AMBCTL_RAT == 9)
226#define flash_EBIU_AMBCTL0_RAT B0RAT_9
227#endif
228#if (flash_EBIU_AMBCTL_RAT == 8)
229#define flash_EBIU_AMBCTL0_RAT B0RAT_8
230#endif
231#if (flash_EBIU_AMBCTL_RAT == 7)
232#define flash_EBIU_AMBCTL0_RAT B0RAT_7
233#endif
234#if (flash_EBIU_AMBCTL_RAT == 6)
235#define flash_EBIU_AMBCTL0_RAT B0RAT_6
236#endif
237#if (flash_EBIU_AMBCTL_RAT == 5)
238#define flash_EBIU_AMBCTL0_RAT B0RAT_5
239#endif
240#if (flash_EBIU_AMBCTL_RAT == 4)
241#define flash_EBIU_AMBCTL0_RAT B0RAT_4
242#endif
243#if (flash_EBIU_AMBCTL_RAT == 3)
244#define flash_EBIU_AMBCTL0_RAT B0RAT_3
245#endif
246#if (flash_EBIU_AMBCTL_RAT == 2)
247#define flash_EBIU_AMBCTL0_RAT B0RAT_2
248#endif
249#if (flash_EBIU_AMBCTL_RAT == 1)
250#define flash_EBIU_AMBCTL0_RAT B0RAT_1
251#endif
252
253#define flash_EBIU_AMBCTL0 \
254 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
255 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
deleted file mode 100644
index f99f47bc3a07..000000000000
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_548_H_
32#define _MEM_MAP_548_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
40#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
42#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x1000
51
52/* L1 Instruction ROM */
53
54#define L1_ROM_START 0xFFA14000
55#define L1_ROM_LENGTH 0x10000
56
57/* Level 1 Memory */
58
59/* Memory Map for ADSP-BF548 processors */
60#ifdef CONFIG_BFIN_ICACHE
61#define BFIN_ICACHESIZE (16*1024)
62#else
63#define BFIN_ICACHESIZE (0*1024)
64#endif
65
66#define L1_CODE_START 0xFFA00000
67#define L1_DATA_A_START 0xFF800000
68#define L1_DATA_B_START 0xFF900000
69
70#define L1_CODE_LENGTH 0xC000
71
72#ifdef CONFIG_BFIN_DCACHE
73
74#ifdef CONFIG_BFIN_DCACHE_BANKA
75#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
76#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
77#define L1_DATA_B_LENGTH 0x8000
78#define BFIN_DCACHESIZE (16*1024)
79#define BFIN_DSUPBANKS 1
80#else
81#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
82#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
83#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
84#define BFIN_DCACHESIZE (32*1024)
85#define BFIN_DSUPBANKS 2
86#endif
87
88#else
89#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
90#define L1_DATA_A_LENGTH 0x8000
91#define L1_DATA_B_LENGTH 0x8000
92#define BFIN_DCACHESIZE (0*1024)
93#define BFIN_DSUPBANKS 0
94#endif /*CONFIG_BFIN_DCACHE*/
95
96/* Level 2 Memory */
97#if !defined(CONFIG_BF542)
98# define L2_START 0xFEB00000
99# if defined(CONFIG_BF544)
100# define L2_LENGTH 0x10000
101# else
102# define L2_LENGTH 0x20000
103# endif
104#endif
105
106/* Scratch Pad Memory */
107
108#define L1_SCRATCH_START 0xFFB00000
109#define L1_SCRATCH_LENGTH 0x1000
110
111#endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
deleted file mode 100644
index 8177a567dcdb..000000000000
--- a/include/asm-blackfin/mach-bf548/portmux.h
+++ /dev/null
@@ -1,286 +0,0 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
6#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
7#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
8#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
9#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
10#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
11#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
12#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
13#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
14#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
15#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
16#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
17#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
18#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
19#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
20#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
21#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
22#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
23#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
24#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
25#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
26
27#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
28#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
29#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
30#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
31#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
32#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
33#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
34#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
35#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
36#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
37#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
38#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
39#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
40#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
41#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
42#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
43#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
44#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
45#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
46
47#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
48#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
49#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
50#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
51#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
52#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
53#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
54#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
55#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
56#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
57#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
58#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
59#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
60#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
61#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
62#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
63
64#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
65#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
66#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
67#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
68#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
69#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
70#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
71#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
72#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
73#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
74#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
75#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
76#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
77#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
78#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
79#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
80
81#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
82#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
83#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
84#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
85#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
86#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
87#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
88#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
89#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
90#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
91#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
92#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
93#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
94#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
95#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
96#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
97#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
98#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
99#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
100#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
101#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
102#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
103#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
104#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
105#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
106#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
107#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
108#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
109#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
110#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
111#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
112#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
113#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
114#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
115#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
116#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
117#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
118#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
119#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
120#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
121#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
122#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
123#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
124#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
125#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
126#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
127
128#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
129#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
130#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
131#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
132#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
133#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
134#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
135#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
136#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
137#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
138#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
139#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
140#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
141#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
142#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
143#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
144#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
145#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
146#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
147#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
148#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
149#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
150#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
151#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
152
153#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
154#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
155#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
156#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
157#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
158#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
159#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
160#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
161#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
162#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
163#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
164#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
165#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
166#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
167#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
168#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
169#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
170#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
171#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
172#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
173#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
174#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
175#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
176#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
177#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
178#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
179#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
180#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
181#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
182#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
183#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
184#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
185
186#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
187#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
188#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
189#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
190#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
191#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
192#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
193#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
194#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
195#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
196#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
197#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
198#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
199#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
200#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
201#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
202#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
203#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
204#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
205#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
206#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
207#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
208#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
209#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
210#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
211#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
212#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
213
214#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
215#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
216#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
217#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
218#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
219#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
220#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
221#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
222#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
223#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
224#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
225#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
226#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
227#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
228#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
229#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
230#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
231#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
232#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
233#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
234#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
235#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
236#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
237#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
238
239#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
240#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
241#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
242#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
243#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
244#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
245#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
246#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
247#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
248#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
249#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
250#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
251#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
252#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
253#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
254#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
255#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
256
257#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
258#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
259#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
260#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
261#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
262#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
263#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
264#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
265#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
266#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
267#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
268#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
269#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
270#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
271
272
273#define P_NAND_D0 (P_DONTCARE)
274#define P_NAND_D1 (P_DONTCARE)
275#define P_NAND_D2 (P_DONTCARE)
276#define P_NAND_D3 (P_DONTCARE)
277#define P_NAND_D4 (P_DONTCARE)
278#define P_NAND_D5 (P_DONTCARE)
279#define P_NAND_D6 (P_DONTCARE)
280#define P_NAND_D7 (P_DONTCARE)
281#define P_NAND_WE (P_DONTCARE)
282#define P_NAND_RE (P_DONTCARE)
283#define P_NAND_CLE (P_DONTCARE)
284#define P_NAND_ALE (P_DONTCARE)
285
286#endif /* _MACH_PORTMUX_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-01 01:04:48 -0400