diff options
| author | Roy Huang <roy.huang@analog.com> | 2007-07-12 10:41:45 -0400 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-07-12 10:41:45 -0400 |
| commit | 24a07a124198153540f8f43d9e91d16227aba66e (patch) | |
| tree | 917b2011e67e224515830833b1151e276b6c6137 /include/asm-blackfin/mach-bf548/defBF54x_base.h | |
| parent | 088eec1192a0ae60fc218796027e622008af36c0 (diff) | |
Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia
applications where system performance and cost are essential ingredients. The
integration of multimedia, human interface, and connectivity peripherals combined
with increased system bandwidth and on-chip memory provides customers a platform to
design the most demanding applications.
Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers
such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will
be submitted later.
Please enjoy the show.
Signed-off-by: Roy Huang <roy.huang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf548/defBF54x_base.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/defBF54x_base.h | 1281 |
1 files changed, 124 insertions, 1157 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index a1b200fe6a1f..2381ac50a2cf 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h | |||
| @@ -46,7 +46,7 @@ | |||
| 46 | 46 | ||
| 47 | /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ | 47 | /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ |
| 48 | 48 | ||
| 49 | #define CHIPID 0xffc00014 | 49 | #define CHIPID 0xffc00014 |
| 50 | 50 | ||
| 51 | /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ | 51 | /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ |
| 52 | 52 | ||
| @@ -1512,231 +1512,144 @@ | |||
| 1512 | /* and MULTI BIT READ MACROS */ | 1512 | /* and MULTI BIT READ MACROS */ |
| 1513 | /* ********************************************************** */ | 1513 | /* ********************************************************** */ |
| 1514 | 1514 | ||
| 1515 | /* SIC_IMASK Masks */ | ||
| 1516 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | ||
| 1517 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | ||
| 1518 | #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ | ||
| 1519 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ | ||
| 1520 | |||
| 1521 | /* SIC_IWR Masks */ | ||
| 1522 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | ||
| 1523 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | ||
| 1524 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ | ||
| 1525 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ | ||
| 1526 | |||
| 1515 | /* Bit masks for SIC_IAR0 */ | 1527 | /* Bit masks for SIC_IAR0 */ |
| 1516 | 1528 | ||
| 1517 | #define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */ | 1529 | #define PLL_WAKEUP 0x1 /* PLL Wakeup */ |
| 1518 | #define nIRQ_PLL_WAKEUP 0x0 | ||
| 1519 | 1530 | ||
| 1520 | /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ | 1531 | /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ |
| 1521 | 1532 | ||
| 1522 | #define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */ | 1533 | #define DMA0_ERR 0x2 /* DMA Controller 0 Error */ |
| 1523 | #define nIRQ_DMA0_ERR 0x0 | 1534 | #define EPPI0_ERR 0x4 /* EPPI0 Error */ |
| 1524 | #define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */ | 1535 | #define SPORT0_ERR 0x8 /* SPORT0 Error */ |
| 1525 | #define nIRQ_EPPI0_ERR 0x0 | 1536 | #define SPORT1_ERR 0x10 /* SPORT1 Error */ |
| 1526 | #define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */ | 1537 | #define SPI0_ERR 0x20 /* SPI0 Error */ |
| 1527 | #define nIRQ_SPORT0_ERR 0x0 | 1538 | #define UART0_ERR 0x40 /* UART0 Error */ |
| 1528 | #define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */ | 1539 | #define RTC 0x80 /* Real-Time Clock */ |
| 1529 | #define nIRQ_SPORT1_ERR 0x0 | 1540 | #define DMA12 0x100 /* DMA Channel 12 */ |
| 1530 | #define IRQ_SPI0_ERR 0x20 /* SPI0 Error */ | 1541 | #define DMA0 0x200 /* DMA Channel 0 */ |
| 1531 | #define nIRQ_SPI0_ERR 0x0 | 1542 | #define DMA1 0x400 /* DMA Channel 1 */ |
| 1532 | #define IRQ_UART0_ERR 0x40 /* UART0 Error */ | 1543 | #define DMA2 0x800 /* DMA Channel 2 */ |
| 1533 | #define nIRQ_UART0_ERR 0x0 | 1544 | #define DMA3 0x1000 /* DMA Channel 3 */ |
| 1534 | #define IRQ_RTC 0x80 /* Real-Time Clock */ | 1545 | #define DMA4 0x2000 /* DMA Channel 4 */ |
| 1535 | #define nIRQ_RTC 0x0 | 1546 | #define DMA6 0x4000 /* DMA Channel 6 */ |
| 1536 | #define IRQ_DMA12 0x100 /* DMA Channel 12 */ | 1547 | #define DMA7 0x8000 /* DMA Channel 7 */ |
| 1537 | #define nIRQ_DMA12 0x0 | 1548 | #define PINT0 0x80000 /* Pin Interrupt 0 */ |
| 1538 | #define IRQ_DMA0 0x200 /* DMA Channel 0 */ | 1549 | #define PINT1 0x100000 /* Pin Interrupt 1 */ |
| 1539 | #define nIRQ_DMA0 0x0 | 1550 | #define MDMA0 0x200000 /* Memory DMA Stream 0 */ |
| 1540 | #define IRQ_DMA1 0x400 /* DMA Channel 1 */ | 1551 | #define MDMA1 0x400000 /* Memory DMA Stream 1 */ |
| 1541 | #define nIRQ_DMA1 0x0 | 1552 | #define WDOG 0x800000 /* Watchdog Timer */ |
| 1542 | #define IRQ_DMA2 0x800 /* DMA Channel 2 */ | 1553 | #define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ |
| 1543 | #define nIRQ_DMA2 0x0 | 1554 | #define SPORT2_ERR 0x2000000 /* SPORT2 Error */ |
| 1544 | #define IRQ_DMA3 0x1000 /* DMA Channel 3 */ | 1555 | #define SPORT3_ERR 0x4000000 /* SPORT3 Error */ |
| 1545 | #define nIRQ_DMA3 0x0 | 1556 | #define MXVR_SD 0x8000000 /* MXVR Synchronous Data */ |
| 1546 | #define IRQ_DMA4 0x2000 /* DMA Channel 4 */ | 1557 | #define SPI1_ERR 0x10000000 /* SPI1 Error */ |
| 1547 | #define nIRQ_DMA4 0x0 | 1558 | #define SPI2_ERR 0x20000000 /* SPI2 Error */ |
| 1548 | #define IRQ_DMA6 0x4000 /* DMA Channel 6 */ | 1559 | #define UART1_ERR 0x40000000 /* UART1 Error */ |
| 1549 | #define nIRQ_DMA6 0x0 | 1560 | #define UART2_ERR 0x80000000 /* UART2 Error */ |
| 1550 | #define IRQ_DMA7 0x8000 /* DMA Channel 7 */ | ||
| 1551 | #define nIRQ_DMA7 0x0 | ||
| 1552 | #define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */ | ||
| 1553 | #define nIRQ_PINT0 0x0 | ||
| 1554 | #define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */ | ||
| 1555 | #define nIRQ_PINT1 0x0 | ||
| 1556 | #define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */ | ||
| 1557 | #define nIRQ_MDMA0 0x0 | ||
| 1558 | #define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */ | ||
| 1559 | #define nIRQ_MDMA1 0x0 | ||
| 1560 | #define IRQ_WDOG 0x800000 /* Watchdog Timer */ | ||
| 1561 | #define nIRQ_WDOG 0x0 | ||
| 1562 | #define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ | ||
| 1563 | #define nIRQ_DMA1_ERR 0x0 | ||
| 1564 | #define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */ | ||
| 1565 | #define nIRQ_SPORT2_ERR 0x0 | ||
| 1566 | #define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */ | ||
| 1567 | #define nIRQ_SPORT3_ERR 0x0 | ||
| 1568 | #define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */ | ||
| 1569 | #define nIRQ_MXVR_SD 0x0 | ||
| 1570 | #define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */ | ||
| 1571 | #define nIRQ_SPI1_ERR 0x0 | ||
| 1572 | #define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */ | ||
| 1573 | #define nIRQ_SPI2_ERR 0x0 | ||
| 1574 | #define IRQ_UART1_ERR 0x40000000 /* UART1 Error */ | ||
| 1575 | #define nIRQ_UART1_ERR 0x0 | ||
| 1576 | #define IRQ_UART2_ERR 0x80000000 /* UART2 Error */ | ||
| 1577 | #define nIRQ_UART2_ERR 0x0 | ||
| 1578 | 1561 | ||
| 1579 | /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ | 1562 | /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ |
| 1580 | 1563 | ||
| 1581 | #define IRQ_CAN0_ERR 0x1 /* CAN0 Error */ | 1564 | #define CAN0_ERR 0x1 /* CAN0 Error */ |
| 1582 | #define nIRQ_CAN0_ERR 0x0 | 1565 | #define DMA18 0x2 /* DMA Channel 18 */ |
| 1583 | #define IRQ_DMA18 0x2 /* DMA Channel 18 */ | 1566 | #define DMA19 0x4 /* DMA Channel 19 */ |
| 1584 | #define nIRQ_DMA18 0x0 | 1567 | #define DMA20 0x8 /* DMA Channel 20 */ |
| 1585 | #define IRQ_DMA19 0x4 /* DMA Channel 19 */ | 1568 | #define DMA21 0x10 /* DMA Channel 21 */ |
| 1586 | #define nIRQ_DMA19 0x0 | 1569 | #define DMA13 0x20 /* DMA Channel 13 */ |
| 1587 | #define IRQ_DMA20 0x8 /* DMA Channel 20 */ | 1570 | #define DMA14 0x40 /* DMA Channel 14 */ |
| 1588 | #define nIRQ_DMA20 0x0 | 1571 | #define DMA5 0x80 /* DMA Channel 5 */ |
| 1589 | #define IRQ_DMA21 0x10 /* DMA Channel 21 */ | 1572 | #define DMA23 0x100 /* DMA Channel 23 */ |
| 1590 | #define nIRQ_DMA21 0x0 | 1573 | #define DMA8 0x200 /* DMA Channel 8 */ |
| 1591 | #define IRQ_DMA13 0x20 /* DMA Channel 13 */ | 1574 | #define DMA9 0x400 /* DMA Channel 9 */ |
| 1592 | #define nIRQ_DMA13 0x0 | 1575 | #define DMA10 0x800 /* DMA Channel 10 */ |
| 1593 | #define IRQ_DMA14 0x40 /* DMA Channel 14 */ | 1576 | #define DMA11 0x1000 /* DMA Channel 11 */ |
| 1594 | #define nIRQ_DMA14 0x0 | 1577 | #define TWI0 0x2000 /* TWI0 */ |
| 1595 | #define IRQ_DMA5 0x80 /* DMA Channel 5 */ | 1578 | #define TWI1 0x4000 /* TWI1 */ |
| 1596 | #define nIRQ_DMA5 0x0 | 1579 | #define CAN0_RX 0x8000 /* CAN0 Receive */ |
| 1597 | #define IRQ_DMA23 0x100 /* DMA Channel 23 */ | 1580 | #define CAN0_TX 0x10000 /* CAN0 Transmit */ |
| 1598 | #define nIRQ_DMA23 0x0 | 1581 | #define MDMA2 0x20000 /* Memory DMA Stream 0 */ |
| 1599 | #define IRQ_DMA8 0x200 /* DMA Channel 8 */ | 1582 | #define MDMA3 0x40000 /* Memory DMA Stream 1 */ |
| 1600 | #define nIRQ_DMA8 0x0 | 1583 | #define MXVR_STAT 0x80000 /* MXVR Status */ |
| 1601 | #define IRQ_DMA9 0x400 /* DMA Channel 9 */ | 1584 | #define MXVR_CM 0x100000 /* MXVR Control Message */ |
| 1602 | #define nIRQ_DMA9 0x0 | 1585 | #define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ |
| 1603 | #define IRQ_DMA10 0x800 /* DMA Channel 10 */ | 1586 | #define EPPI1_ERR 0x400000 /* EPPI1 Error */ |
| 1604 | #define nIRQ_DMA10 0x0 | 1587 | #define EPPI2_ERR 0x800000 /* EPPI2 Error */ |
| 1605 | #define IRQ_DMA11 0x1000 /* DMA Channel 11 */ | 1588 | #define UART3_ERR 0x1000000 /* UART3 Error */ |
| 1606 | #define nIRQ_DMA11 0x0 | 1589 | #define HOST_ERR 0x2000000 /* Host DMA Port Error */ |
| 1607 | #define IRQ_TWI0 0x2000 /* TWI0 */ | 1590 | #define USB_ERR 0x4000000 /* USB Error */ |
| 1608 | #define nIRQ_TWI0 0x0 | 1591 | #define PIXC_ERR 0x8000000 /* Pixel Compositor Error */ |
| 1609 | #define IRQ_TWI1 0x4000 /* TWI1 */ | 1592 | #define NFC_ERR 0x10000000 /* Nand Flash Controller Error */ |
| 1610 | #define nIRQ_TWI1 0x0 | 1593 | #define ATAPI_ERR 0x20000000 /* ATAPI Error */ |
| 1611 | #define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */ | 1594 | #define CAN1_ERR 0x40000000 /* CAN1 Error */ |
| 1612 | #define nIRQ_CAN0_RX 0x0 | 1595 | #define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ |
| 1613 | #define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */ | 1596 | #define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ |
| 1614 | #define nIRQ_CAN0_TX 0x0 | 1597 | #define DMAR0 0x80000000 /* DMAR0 Block */ |
| 1615 | #define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */ | 1598 | #define DMAR1 0x80000000 /* DMAR1 Block */ |
| 1616 | #define nIRQ_MDMA2 0x0 | ||
| 1617 | #define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */ | ||
| 1618 | #define nIRQ_MDMA3 0x0 | ||
| 1619 | #define IRQ_MXVR_STAT 0x80000 /* MXVR Status */ | ||
| 1620 | #define nIRQ_MXVR_STAT 0x0 | ||
| 1621 | #define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */ | ||
| 1622 | #define nIRQ_MXVR_CM 0x0 | ||
| 1623 | #define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ | ||
| 1624 | #define nIRQ_MXVR_AP 0x0 | ||
| 1625 | #define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */ | ||
| 1626 | #define nIRQ_EPPI1_ERR 0x0 | ||
| 1627 | #define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */ | ||
| 1628 | #define nIRQ_EPPI2_ERR 0x0 | ||
| 1629 | #define IRQ_UART3_ERR 0x1000000 /* UART3 Error */ | ||
| 1630 | #define nIRQ_UART3_ERR 0x0 | ||
| 1631 | #define IRQ_HOST_ERR 0x2000000 /* Host DMA Port Error */ | ||
| 1632 | #define nIRQ_HOST_ERR 0x0 | ||
| 1633 | #define IRQ_USB_ERR 0x4000000 /* USB Error */ | ||
| 1634 | #define nIRQ_USB_ERR 0x0 | ||
| 1635 | #define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */ | ||
| 1636 | #define nIRQ_PIXC_ERR 0x0 | ||
| 1637 | #define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */ | ||
| 1638 | #define nIRQ_NFC_ERR 0x0 | ||
| 1639 | #define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */ | ||
| 1640 | #define nIRQ_ATAPI_ERR 0x0 | ||
| 1641 | #define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */ | ||
| 1642 | #define nIRQ_CAN1_ERR 0x0 | ||
| 1643 | #define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ | ||
| 1644 | #define nIRQ_DMAR0_ERR 0x0 | ||
| 1645 | #define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ | ||
| 1646 | #define nIRQ_DMAR1_ERR 0x0 | ||
| 1647 | #define IRQ_DMAR0 0x80000000 /* DMAR0 Block */ | ||
| 1648 | #define nIRQ_DMAR0 0x0 | ||
| 1649 | #define IRQ_DMAR1 0x80000000 /* DMAR1 Block */ | ||
| 1650 | #define nIRQ_DMAR1 0x0 | ||
| 1651 | 1599 | ||
| 1652 | /* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ | 1600 | /* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ |
| 1653 | 1601 | ||
| 1654 | #define IRQ_DMA15 0x1 /* DMA Channel 15 */ | 1602 | #define DMA15 0x1 /* DMA Channel 15 */ |
| 1655 | #define nIRQ_DMA15 0x0 | 1603 | #define DMA16 0x2 /* DMA Channel 16 */ |
| 1656 | #define IRQ_DMA16 0x2 /* DMA Channel 16 */ | 1604 | #define DMA17 0x4 /* DMA Channel 17 */ |
| 1657 | #define nIRQ_DMA16 0x0 | 1605 | #define DMA22 0x8 /* DMA Channel 22 */ |
| 1658 | #define IRQ_DMA17 0x4 /* DMA Channel 17 */ | 1606 | #define CNT 0x10 /* Counter */ |
| 1659 | #define nIRQ_DMA17 0x0 | 1607 | #define KEY 0x20 /* Keypad */ |
| 1660 | #define IRQ_DMA22 0x8 /* DMA Channel 22 */ | 1608 | #define CAN1_RX 0x40 /* CAN1 Receive */ |
| 1661 | #define nIRQ_DMA22 0x0 | 1609 | #define CAN1_TX 0x80 /* CAN1 Transmit */ |
| 1662 | #define IRQ_CNT 0x10 /* Counter */ | 1610 | #define SDH_INT_MASK0 0x100 /* SDH Mask 0 */ |
| 1663 | #define nIRQ_CNT 0x0 | 1611 | #define SDH_INT_MASK1 0x200 /* SDH Mask 1 */ |
| 1664 | #define IRQ_KEY 0x20 /* Keypad */ | 1612 | #define USB_EINT 0x400 /* USB Exception */ |
| 1665 | #define nIRQ_KEY 0x0 | 1613 | #define USB_INT0 0x800 /* USB Interrupt 0 */ |
| 1666 | #define IRQ_CAN1_RX 0x40 /* CAN1 Receive */ | 1614 | #define USB_INT1 0x1000 /* USB Interrupt 1 */ |
| 1667 | #define nIRQ_CAN1_RX 0x0 | 1615 | #define USB_INT2 0x2000 /* USB Interrupt 2 */ |
| 1668 | #define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */ | 1616 | #define USB_DMAINT 0x4000 /* USB DMA */ |
| 1669 | #define nIRQ_CAN1_TX 0x0 | 1617 | #define OTPSEC 0x8000 /* OTP Access Complete */ |
| 1670 | #define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */ | 1618 | #define TIMER0 0x400000 /* Timer 0 */ |
| 1671 | #define nIRQ_SDH_MASK0 0x0 | 1619 | #define TIMER1 0x800000 /* Timer 1 */ |
| 1672 | #define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */ | 1620 | #define TIMER2 0x1000000 /* Timer 2 */ |
| 1673 | #define nIRQ_SDH_MASK1 0x0 | 1621 | #define TIMER3 0x2000000 /* Timer 3 */ |
| 1674 | #define IRQ_USB_EINT 0x400 /* USB Exception */ | 1622 | #define TIMER4 0x4000000 /* Timer 4 */ |
| 1675 | #define nIRQ_USB_EINT 0x0 | 1623 | #define TIMER5 0x8000000 /* Timer 5 */ |
| 1676 | #define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */ | 1624 | #define TIMER6 0x10000000 /* Timer 6 */ |
| 1677 | #define nIRQ_USB_INT0 0x0 | 1625 | #define TIMER7 0x20000000 /* Timer 7 */ |
| 1678 | #define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */ | 1626 | #define PINT2 0x40000000 /* Pin Interrupt 2 */ |
| 1679 | #define nIRQ_USB_INT1 0x0 | 1627 | #define PINT3 0x80000000 /* Pin Interrupt 3 */ |
| 1680 | #define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */ | ||
| 1681 | #define nIRQ_USB_INT2 0x0 | ||
| 1682 | #define IRQ_USB_DMAINT 0x4000 /* USB DMA */ | ||
| 1683 | #define nIRQ_USB_DMAINT 0x0 | ||
| 1684 | #define IRQ_OTPSEC 0x8000 /* OTP Access Complete */ | ||
| 1685 | #define nIRQ_OTPSEC 0x0 | ||
| 1686 | #define IRQ_TIMER0 0x400000 /* Timer 0 */ | ||
| 1687 | #define nIRQ_TIMER0 0x0 | ||
| 1688 | #define IRQ_TIMER1 0x800000 /* Timer 1 */ | ||
| 1689 | #define nIRQ_TIMER1 0x0 | ||
| 1690 | #define IRQ_TIMER2 0x1000000 /* Timer 2 */ | ||
| 1691 | #define nIRQ_TIMER2 0x0 | ||
| 1692 | #define IRQ_TIMER3 0x2000000 /* Timer 3 */ | ||
| 1693 | #define nIRQ_TIMER3 0x0 | ||
| 1694 | #define IRQ_TIMER4 0x4000000 /* Timer 4 */ | ||
| 1695 | #define nIRQ_TIMER4 0x0 | ||
| 1696 | #define IRQ_TIMER5 0x8000000 /* Timer 5 */ | ||
| 1697 | #define nIRQ_TIMER5 0x0 | ||
| 1698 | #define IRQ_TIMER6 0x10000000 /* Timer 6 */ | ||
| 1699 | #define nIRQ_TIMER6 0x0 | ||
| 1700 | #define IRQ_TIMER7 0x20000000 /* Timer 7 */ | ||
| 1701 | #define nIRQ_TIMER7 0x0 | ||
| 1702 | #define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */ | ||
| 1703 | #define nIRQ_PINT2 0x0 | ||
| 1704 | #define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */ | ||
| 1705 | #define nIRQ_PINT3 0x0 | ||
| 1706 | 1628 | ||
| 1707 | /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ | 1629 | /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ |
| 1708 | 1630 | ||
| 1709 | #define DMAEN 0x1 /* DMA Channel Enable */ | 1631 | #define DMAEN 0x1 /* DMA Channel Enable */ |
| 1710 | #define nDMAEN 0x0 | ||
| 1711 | #define WNR 0x2 /* DMA Direction */ | 1632 | #define WNR 0x2 /* DMA Direction */ |
| 1712 | #define nWNR 0x0 | 1633 | #define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ |
| 1713 | #define WDSIZE 0xc /* Transfer Word Size */ | 1634 | #define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ |
| 1635 | #define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ | ||
| 1714 | #define DMA2D 0x10 /* DMA Mode */ | 1636 | #define DMA2D 0x10 /* DMA Mode */ |
| 1715 | #define nDMA2D 0x0 | ||
| 1716 | #define RESTART 0x20 /* Work Unit Transitions */ | 1637 | #define RESTART 0x20 /* Work Unit Transitions */ |
| 1717 | #define nRESTART 0x0 | ||
| 1718 | #define DI_SEL 0x40 /* Data Interrupt Timing Select */ | 1638 | #define DI_SEL 0x40 /* Data Interrupt Timing Select */ |
| 1719 | #define nDI_SEL 0x0 | ||
| 1720 | #define DI_EN 0x80 /* Data Interrupt Enable */ | 1639 | #define DI_EN 0x80 /* Data Interrupt Enable */ |
| 1721 | #define nDI_EN 0x0 | ||
| 1722 | #define NDSIZE 0xf00 /* Flex Descriptor Size */ | 1640 | #define NDSIZE 0xf00 /* Flex Descriptor Size */ |
| 1723 | #define DMAFLOW 0xf000 /* Next Operation */ | 1641 | #define DMAFLOW 0xf000 /* Next Operation */ |
| 1724 | 1642 | ||
| 1725 | /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ | 1643 | /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ |
| 1726 | 1644 | ||
| 1727 | #define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ | 1645 | #define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ |
| 1728 | #define nDMA_DONE 0x0 | ||
| 1729 | #define DMA_ERR 0x2 /* DMA Error Interrupt Status */ | 1646 | #define DMA_ERR 0x2 /* DMA Error Interrupt Status */ |
| 1730 | #define nDMA_ERR 0x0 | ||
| 1731 | #define DFETCH 0x4 /* DMA Descriptor Fetch */ | 1647 | #define DFETCH 0x4 /* DMA Descriptor Fetch */ |
| 1732 | #define nDFETCH 0x0 | ||
| 1733 | #define DMA_RUN 0x8 /* DMA Channel Running */ | 1648 | #define DMA_RUN 0x8 /* DMA Channel Running */ |
| 1734 | #define nDMA_RUN 0x0 | ||
| 1735 | 1649 | ||
| 1736 | /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ | 1650 | /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ |
| 1737 | 1651 | ||
| 1738 | #define CTYPE 0x40 /* DMA Channel Type */ | 1652 | #define CTYPE 0x40 /* DMA Channel Type */ |
| 1739 | #define nCTYPE 0x0 | ||
| 1740 | #define PMAP 0xf000 /* Peripheral Mapped To This Channel */ | 1653 | #define PMAP 0xf000 /* Peripheral Mapped To This Channel */ |
| 1741 | 1654 | ||
| 1742 | /* Bit masks for DMACx_TCPER */ | 1655 | /* Bit masks for DMACx_TCPER */ |
| @@ -1756,29 +1669,28 @@ | |||
| 1756 | /* Bit masks for DMAC1_PERIMUX */ | 1669 | /* Bit masks for DMAC1_PERIMUX */ |
| 1757 | 1670 | ||
| 1758 | #define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ | 1671 | #define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ |
| 1759 | #define nPMUXSDH 0x0 | ||
| 1760 | 1672 | ||
| 1761 | /* Bit masks for EBIU_AMGCTL */ | 1673 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ |
| 1674 | /* EBIU_AMGCTL Masks */ | ||
| 1675 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | ||
| 1676 | #define AMBEN_NONE 0x0000 /* All Banks Disabled */ | ||
| 1677 | #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ | ||
| 1678 | #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ | ||
| 1679 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ | ||
| 1680 | #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ | ||
| 1762 | 1681 | ||
| 1763 | #define AMCKEN 0x1 /* Async Memory Enable */ | ||
| 1764 | #define nAMCKEN 0x0 | ||
| 1765 | #define AMBEN 0xe /* Async bank enable */ | ||
| 1766 | 1682 | ||
| 1767 | /* Bit masks for EBIU_AMBCTL0 */ | 1683 | /* Bit masks for EBIU_AMBCTL0 */ |
| 1768 | 1684 | ||
| 1769 | #define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ | 1685 | #define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ |
| 1770 | #define nB0RDYEN 0x0 | ||
| 1771 | #define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ | 1686 | #define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ |
| 1772 | #define nB0RDYPOL 0x0 | ||
| 1773 | #define B0TT 0xc /* Bank 0 transition time */ | 1687 | #define B0TT 0xc /* Bank 0 transition time */ |
| 1774 | #define B0ST 0x30 /* Bank 0 Setup time */ | 1688 | #define B0ST 0x30 /* Bank 0 Setup time */ |
| 1775 | #define B0HT 0xc0 /* Bank 0 Hold time */ | 1689 | #define B0HT 0xc0 /* Bank 0 Hold time */ |
| 1776 | #define B0RAT 0xf00 /* Bank 0 Read access time */ | 1690 | #define B0RAT 0xf00 /* Bank 0 Read access time */ |
| 1777 | #define B0WAT 0xf000 /* Bank 0 write access time */ | 1691 | #define B0WAT 0xf000 /* Bank 0 write access time */ |
| 1778 | #define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ | 1692 | #define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ |
| 1779 | #define nB1RDYEN 0x0 | ||
| 1780 | #define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ | 1693 | #define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ |
| 1781 | #define nB1RDYPOL 0x0 | ||
| 1782 | #define B1TT 0xc0000 /* Bank 1 transition time */ | 1694 | #define B1TT 0xc0000 /* Bank 1 transition time */ |
| 1783 | #define B1ST 0x300000 /* Bank 1 Setup time */ | 1695 | #define B1ST 0x300000 /* Bank 1 Setup time */ |
| 1784 | #define B1HT 0xc00000 /* Bank 1 Hold time */ | 1696 | #define B1HT 0xc00000 /* Bank 1 Hold time */ |
| @@ -1788,18 +1700,14 @@ | |||
| 1788 | /* Bit masks for EBIU_AMBCTL1 */ | 1700 | /* Bit masks for EBIU_AMBCTL1 */ |
| 1789 | 1701 | ||
| 1790 | #define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ | 1702 | #define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ |
| 1791 | #define nB2RDYEN 0x0 | ||
| 1792 | #define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ | 1703 | #define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ |
| 1793 | #define nB2RDYPOL 0x0 | ||
| 1794 | #define B2TT 0xc /* Bank 2 transition time */ | 1704 | #define B2TT 0xc /* Bank 2 transition time */ |
| 1795 | #define B2ST 0x30 /* Bank 2 Setup time */ | 1705 | #define B2ST 0x30 /* Bank 2 Setup time */ |
| 1796 | #define B2HT 0xc0 /* Bank 2 Hold time */ | 1706 | #define B2HT 0xc0 /* Bank 2 Hold time */ |
| 1797 | #define B2RAT 0xf00 /* Bank 2 Read access time */ | 1707 | #define B2RAT 0xf00 /* Bank 2 Read access time */ |
| 1798 | #define B2WAT 0xf000 /* Bank 2 write access time */ | 1708 | #define B2WAT 0xf000 /* Bank 2 write access time */ |
| 1799 | #define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ | 1709 | #define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ |
| 1800 | #define nB3RDYEN 0x0 | ||
| 1801 | #define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ | 1710 | #define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ |
| 1802 | #define nB3RDYPOL 0x0 | ||
| 1803 | #define B3TT 0xc0000 /* Bank 3 transition time */ | 1711 | #define B3TT 0xc0000 /* Bank 3 transition time */ |
| 1804 | #define B3ST 0x300000 /* Bank 3 Setup time */ | 1712 | #define B3ST 0x300000 /* Bank 3 Setup time */ |
| 1805 | #define B3HT 0xc00000 /* Bank 3 Hold time */ | 1713 | #define B3HT 0xc00000 /* Bank 3 Hold time */ |
| @@ -1823,19 +1731,15 @@ | |||
| 1823 | /* Bit masks for EBIU_FCTL */ | 1731 | /* Bit masks for EBIU_FCTL */ |
| 1824 | 1732 | ||
| 1825 | #define TESTSETLOCK 0x1 /* Test set lock */ | 1733 | #define TESTSETLOCK 0x1 /* Test set lock */ |
| 1826 | #define nTESTSETLOCK 0x0 | ||
| 1827 | #define BCLK 0x6 /* Burst clock frequency */ | 1734 | #define BCLK 0x6 /* Burst clock frequency */ |
| 1828 | #define PGWS 0x38 /* Page wait states */ | 1735 | #define PGWS 0x38 /* Page wait states */ |
| 1829 | #define PGSZ 0x40 /* Page size */ | 1736 | #define PGSZ 0x40 /* Page size */ |
| 1830 | #define nPGSZ 0x0 | ||
| 1831 | #define RDDL 0x380 /* Read data delay */ | 1737 | #define RDDL 0x380 /* Read data delay */ |
| 1832 | 1738 | ||
| 1833 | /* Bit masks for EBIU_ARBSTAT */ | 1739 | /* Bit masks for EBIU_ARBSTAT */ |
| 1834 | 1740 | ||
| 1835 | #define ARBSTAT 0x1 /* Arbitration status */ | 1741 | #define ARBSTAT 0x1 /* Arbitration status */ |
| 1836 | #define nARBSTAT 0x0 | ||
| 1837 | #define BGSTAT 0x2 /* Bus grant status */ | 1742 | #define BGSTAT 0x2 /* Bus grant status */ |
| 1838 | #define nBGSTAT 0x0 | ||
| 1839 | 1743 | ||
| 1840 | /* Bit masks for EBIU_DDRCTL0 */ | 1744 | /* Bit masks for EBIU_DDRCTL0 */ |
| 1841 | 1745 | ||
| @@ -1861,9 +1765,7 @@ | |||
| 1861 | #define BURSTLENGTH 0x7 /* Burst length */ | 1765 | #define BURSTLENGTH 0x7 /* Burst length */ |
| 1862 | #define CASLATENCY 0x70 /* CAS latency */ | 1766 | #define CASLATENCY 0x70 /* CAS latency */ |
| 1863 | #define DLLRESET 0x100 /* DLL Reset */ | 1767 | #define DLLRESET 0x100 /* DLL Reset */ |
| 1864 | #define nDLLRESET 0x0 | ||
| 1865 | #define REGE 0x1000 /* Register mode enable */ | 1768 | #define REGE 0x1000 /* Register mode enable */ |
| 1866 | #define nREGE 0x0 | ||
| 1867 | 1769 | ||
| 1868 | /* Bit masks for EBIU_DDRCTL3 */ | 1770 | /* Bit masks for EBIU_DDRCTL3 */ |
| 1869 | 1771 | ||
| @@ -1876,30 +1778,19 @@ | |||
| 1876 | #define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ | 1778 | #define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ |
| 1877 | #define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ | 1779 | #define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ |
| 1878 | #define DEB1_URGENT 0x1000 /* DEB1 Urgent */ | 1780 | #define DEB1_URGENT 0x1000 /* DEB1 Urgent */ |
| 1879 | #define nDEB1_URGENT 0x0 | ||
| 1880 | #define DEB2_URGENT 0x2000 /* DEB2 Urgent */ | 1781 | #define DEB2_URGENT 0x2000 /* DEB2 Urgent */ |
| 1881 | #define nDEB2_URGENT 0x0 | ||
| 1882 | #define DEB3_URGENT 0x4000 /* DEB3 Urgent */ | 1782 | #define DEB3_URGENT 0x4000 /* DEB3 Urgent */ |
| 1883 | #define nDEB3_URGENT 0x0 | ||
| 1884 | 1783 | ||
| 1885 | /* Bit masks for EBIU_ERRMST */ | 1784 | /* Bit masks for EBIU_ERRMST */ |
| 1886 | 1785 | ||
| 1887 | #define DEB1_ERROR 0x1 /* DEB1 Error */ | 1786 | #define DEB1_ERROR 0x1 /* DEB1 Error */ |
| 1888 | #define nDEB1_ERROR 0x0 | ||
| 1889 | #define DEB2_ERROR 0x2 /* DEB2 Error */ | 1787 | #define DEB2_ERROR 0x2 /* DEB2 Error */ |
| 1890 | #define nDEB2_ERROR 0x0 | ||
| 1891 | #define DEB3_ERROR 0x4 /* DEB3 Error */ | 1788 | #define DEB3_ERROR 0x4 /* DEB3 Error */ |
| 1892 | #define nDEB3_ERROR 0x0 | ||
| 1893 | #define CORE_ERROR 0x8 /* Core error */ | 1789 | #define CORE_ERROR 0x8 /* Core error */ |
| 1894 | #define nCORE_ERROR 0x0 | ||
| 1895 | #define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ | 1790 | #define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ |
| 1896 | #define nDEB_MERROR 0x0 | ||
| 1897 | #define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ | 1791 | #define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ |
| 1898 | #define nDEB2_MERROR 0x0 | ||
| 1899 | #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ | 1792 | #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ |
| 1900 | #define nDEB3_MERROR 0x0 | ||
| 1901 | #define CORE_MERROR 0x80 /* Core Error (2nd) */ | 1793 | #define CORE_MERROR 0x80 /* Core Error (2nd) */ |
| 1902 | #define nCORE_MERROR 0x0 | ||
| 1903 | 1794 | ||
| 1904 | /* Bit masks for EBIU_ERRADD */ | 1795 | /* Bit masks for EBIU_ERRADD */ |
| 1905 | 1796 | ||
| @@ -1908,15 +1799,10 @@ | |||
| 1908 | /* Bit masks for EBIU_RSTCTL */ | 1799 | /* Bit masks for EBIU_RSTCTL */ |
| 1909 | 1800 | ||
| 1910 | #define DDRSRESET 0x1 /* DDR soft reset */ | 1801 | #define DDRSRESET 0x1 /* DDR soft reset */ |
| 1911 | #define nDDRSRESET 0x0 | ||
| 1912 | #define PFTCHSRESET 0x4 /* DDR prefetch reset */ | 1802 | #define PFTCHSRESET 0x4 /* DDR prefetch reset */ |
| 1913 | #define nPFTCHSRESET 0x0 | ||
| 1914 | #define SRREQ 0x8 /* Self-refresh request */ | 1803 | #define SRREQ 0x8 /* Self-refresh request */ |
| 1915 | #define nSRREQ 0x0 | ||
| 1916 | #define SRACK 0x10 /* Self-refresh acknowledge */ | 1804 | #define SRACK 0x10 /* Self-refresh acknowledge */ |
| 1917 | #define nSRACK 0x0 | ||
| 1918 | #define MDDRENABLE 0x20 /* Mobile DDR enable */ | 1805 | #define MDDRENABLE 0x20 /* Mobile DDR enable */ |
| 1919 | #define nMDDRENABLE 0x0 | ||
| 1920 | 1806 | ||
| 1921 | /* Bit masks for EBIU_DDRBRC0 */ | 1807 | /* Bit masks for EBIU_DDRBRC0 */ |
| 1922 | 1808 | ||
| @@ -2013,136 +1899,74 @@ | |||
| 2013 | /* Bit masks for EBIU_DDRMCEN */ | 1899 | /* Bit masks for EBIU_DDRMCEN */ |
| 2014 | 1900 | ||
| 2015 | #define B0WCENABLE 0x1 /* Bank 0 write count enable */ | 1901 | #define B0WCENABLE 0x1 /* Bank 0 write count enable */ |
| 2016 | #define nB0WCENABLE 0x0 | ||
| 2017 | #define B1WCENABLE 0x2 /* Bank 1 write count enable */ | 1902 | #define B1WCENABLE 0x2 /* Bank 1 write count enable */ |
| 2018 | #define nB1WCENABLE 0x0 | ||
| 2019 | #define B2WCENABLE 0x4 /* Bank 2 write count enable */ | 1903 | #define B2WCENABLE 0x4 /* Bank 2 write count enable */ |
| 2020 | #define nB2WCENABLE 0x0 | ||
| 2021 | #define B3WCENABLE 0x8 /* Bank 3 write count enable */ | 1904 | #define B3WCENABLE 0x8 /* Bank 3 write count enable */ |
| 2022 | #define nB3WCENABLE 0x0 | ||
| 2023 | #define B4WCENABLE 0x10 /* Bank 4 write count enable */ | 1905 | #define B4WCENABLE 0x10 /* Bank 4 write count enable */ |
| 2024 | #define nB4WCENABLE 0x0 | ||
| 2025 | #define B5WCENABLE 0x20 /* Bank 5 write count enable */ | 1906 | #define B5WCENABLE 0x20 /* Bank 5 write count enable */ |
| 2026 | #define nB5WCENABLE 0x0 | ||
| 2027 | #define B6WCENABLE 0x40 /* Bank 6 write count enable */ | 1907 | #define B6WCENABLE 0x40 /* Bank 6 write count enable */ |
| 2028 | #define nB6WCENABLE 0x0 | ||
| 2029 | #define B7WCENABLE 0x80 /* Bank 7 write count enable */ | 1908 | #define B7WCENABLE 0x80 /* Bank 7 write count enable */ |
| 2030 | #define nB7WCENABLE 0x0 | ||
| 2031 | #define B0RCENABLE 0x100 /* Bank 0 read count enable */ | 1909 | #define B0RCENABLE 0x100 /* Bank 0 read count enable */ |
| 2032 | #define nB0RCENABLE 0x0 | ||
| 2033 | #define B1RCENABLE 0x200 /* Bank 1 read count enable */ | 1910 | #define B1RCENABLE 0x200 /* Bank 1 read count enable */ |
| 2034 | #define nB1RCENABLE 0x0 | ||
| 2035 | #define B2RCENABLE 0x400 /* Bank 2 read count enable */ | 1911 | #define B2RCENABLE 0x400 /* Bank 2 read count enable */ |
| 2036 | #define nB2RCENABLE 0x0 | ||
| 2037 | #define B3RCENABLE 0x800 /* Bank 3 read count enable */ | 1912 | #define B3RCENABLE 0x800 /* Bank 3 read count enable */ |
| 2038 | #define nB3RCENABLE 0x0 | ||
| 2039 | #define B4RCENABLE 0x1000 /* Bank 4 read count enable */ | 1913 | #define B4RCENABLE 0x1000 /* Bank 4 read count enable */ |
| 2040 | #define nB4RCENABLE 0x0 | ||
| 2041 | #define B5RCENABLE 0x2000 /* Bank 5 read count enable */ | 1914 | #define B5RCENABLE 0x2000 /* Bank 5 read count enable */ |
| 2042 | #define nB5RCENABLE 0x0 | ||
| 2043 | #define B6RCENABLE 0x4000 /* Bank 6 read count enable */ | 1915 | #define B6RCENABLE 0x4000 /* Bank 6 read count enable */ |
| 2044 | #define nB6RCENABLE 0x0 | ||
| 2045 | #define B7RCENABLE 0x8000 /* Bank 7 read count enable */ | 1916 | #define B7RCENABLE 0x8000 /* Bank 7 read count enable */ |
| 2046 | #define nB7RCENABLE 0x0 | ||
| 2047 | #define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ | 1917 | #define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ |
| 2048 | #define nROWACTCENABLE 0x0 | ||
| 2049 | #define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ | 1918 | #define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ |
| 2050 | #define nRWTCENABLE 0x0 | ||
| 2051 | #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ | 1919 | #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ |
| 2052 | #define nARCENABLE 0x0 | ||
| 2053 | #define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ | 1920 | #define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ |
| 2054 | #define nGC0ENABLE 0x0 | ||
| 2055 | #define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ | 1921 | #define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ |
| 2056 | #define nGC1ENABLE 0x0 | ||
| 2057 | #define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ | 1922 | #define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ |
| 2058 | #define nGC2ENABLE 0x0 | ||
| 2059 | #define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ | 1923 | #define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ |
| 2060 | #define nGC3ENABLE 0x0 | ||
| 2061 | #define GCCONTROL 0x3000000 /* DDR Grant Count Control */ | 1924 | #define GCCONTROL 0x3000000 /* DDR Grant Count Control */ |
| 2062 | 1925 | ||
| 2063 | /* Bit masks for EBIU_DDRMCCL */ | 1926 | /* Bit masks for EBIU_DDRMCCL */ |
| 2064 | 1927 | ||
| 2065 | #define CB0WCOUNT 0x1 /* Clear write count 0 */ | 1928 | #define CB0WCOUNT 0x1 /* Clear write count 0 */ |
| 2066 | #define nCB0WCOUNT 0x0 | ||
| 2067 | #define CB1WCOUNT 0x2 /* Clear write count 1 */ | 1929 | #define CB1WCOUNT 0x2 /* Clear write count 1 */ |
| 2068 | #define nCB1WCOUNT 0x0 | ||
| 2069 | #define CB2WCOUNT 0x4 /* Clear write count 2 */ | 1930 | #define CB2WCOUNT 0x4 /* Clear write count 2 */ |
| 2070 | #define nCB2WCOUNT 0x0 | ||
| 2071 | #define CB3WCOUNT 0x8 /* Clear write count 3 */ | 1931 | #define CB3WCOUNT 0x8 /* Clear write count 3 */ |
| 2072 | #define nCB3WCOUNT 0x0 | ||
| 2073 | #define CB4WCOUNT 0x10 /* Clear write count 4 */ | 1932 | #define CB4WCOUNT 0x10 /* Clear write count 4 */ |
| 2074 | #define nCB4WCOUNT 0x0 | ||
| 2075 | #define CB5WCOUNT 0x20 /* Clear write count 5 */ | 1933 | #define CB5WCOUNT 0x20 /* Clear write count 5 */ |
| 2076 | #define nCB5WCOUNT 0x0 | ||
| 2077 | #define CB6WCOUNT 0x40 /* Clear write count 6 */ | 1934 | #define CB6WCOUNT 0x40 /* Clear write count 6 */ |
| 2078 | #define nCB6WCOUNT 0x0 | ||
| 2079 | #define CB7WCOUNT 0x80 /* Clear write count 7 */ | 1935 | #define CB7WCOUNT 0x80 /* Clear write count 7 */ |
| 2080 | #define nCB7WCOUNT 0x0 | ||
| 2081 | #define CBRCOUNT 0x100 /* Clear read count 0 */ | 1936 | #define CBRCOUNT 0x100 /* Clear read count 0 */ |
| 2082 | #define nCBRCOUNT 0x0 | ||
| 2083 | #define CB1RCOUNT 0x200 /* Clear read count 1 */ | 1937 | #define CB1RCOUNT 0x200 /* Clear read count 1 */ |
| 2084 | #define nCB1RCOUNT 0x0 | ||
| 2085 | #define CB2RCOUNT 0x400 /* Clear read count 2 */ | 1938 | #define CB2RCOUNT 0x400 /* Clear read count 2 */ |
| 2086 | #define nCB2RCOUNT 0x0 | ||
| 2087 | #define CB3RCOUNT 0x800 /* Clear read count 3 */ | 1939 | #define CB3RCOUNT 0x800 /* Clear read count 3 */ |
| 2088 | #define nCB3RCOUNT 0x0 | ||
| 2089 | #define CB4RCOUNT 0x1000 /* Clear read count 4 */ | 1940 | #define CB4RCOUNT 0x1000 /* Clear read count 4 */ |
| 2090 | #define nCB4RCOUNT 0x0 | ||
| 2091 | #define CB5RCOUNT 0x2000 /* Clear read count 5 */ | 1941 | #define CB5RCOUNT 0x2000 /* Clear read count 5 */ |
| 2092 | #define nCB5RCOUNT 0x0 | ||
| 2093 | #define CB6RCOUNT 0x4000 /* Clear read count 6 */ | 1942 | #define CB6RCOUNT 0x4000 /* Clear read count 6 */ |
| 2094 | #define nCB6RCOUNT 0x0 | ||
| 2095 | #define CB7RCOUNT 0x8000 /* Clear read count 7 */ | 1943 | #define CB7RCOUNT 0x8000 /* Clear read count 7 */ |
| 2096 | #define nCB7RCOUNT 0x0 | ||
| 2097 | #define CRACOUNT 0x10000 /* Clear row activation count */ | 1944 | #define CRACOUNT 0x10000 /* Clear row activation count */ |
| 2098 | #define nCRACOUNT 0x0 | ||
| 2099 | #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ | 1945 | #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ |
| 2100 | #define nCRWTACOUNT 0x0 | ||
| 2101 | #define CARCOUNT 0x40000 /* Clear auto-refresh count */ | 1946 | #define CARCOUNT 0x40000 /* Clear auto-refresh count */ |
| 2102 | #define nCARCOUNT 0x0 | ||
| 2103 | #define CG0COUNT 0x100000 /* Clear grant count 0 */ | 1947 | #define CG0COUNT 0x100000 /* Clear grant count 0 */ |
| 2104 | #define nCG0COUNT 0x0 | ||
| 2105 | #define CG1COUNT 0x200000 /* Clear grant count 1 */ | 1948 | #define CG1COUNT 0x200000 /* Clear grant count 1 */ |
| 2106 | #define nCG1COUNT 0x0 | ||
| 2107 | #define CG2COUNT 0x400000 /* Clear grant count 2 */ | 1949 | #define CG2COUNT 0x400000 /* Clear grant count 2 */ |
| 2108 | #define nCG2COUNT 0x0 | ||
| 2109 | #define CG3COUNT 0x800000 /* Clear grant count 3 */ | 1950 | #define CG3COUNT 0x800000 /* Clear grant count 3 */ |
| 2110 | #define nCG3COUNT 0x0 | ||
| 2111 | 1951 | ||
| 2112 | /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ | 1952 | /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ |
| 2113 | 1953 | ||
| 2114 | #define Px0 0x1 /* GPIO 0 */ | 1954 | #define Px0 0x1 /* GPIO 0 */ |
| 2115 | #define nPx0 0x0 | ||
| 2116 | #define Px1 0x2 /* GPIO 1 */ | 1955 | #define Px1 0x2 /* GPIO 1 */ |
| 2117 | #define nPx1 0x0 | ||
| 2118 | #define Px2 0x4 /* GPIO 2 */ | 1956 | #define Px2 0x4 /* GPIO 2 */ |
| 2119 | #define nPx2 0x0 | ||
| 2120 | #define Px3 0x8 /* GPIO 3 */ | 1957 | #define Px3 0x8 /* GPIO 3 */ |
| 2121 | #define nPx3 0x0 | ||
| 2122 | #define Px4 0x10 /* GPIO 4 */ | 1958 | #define Px4 0x10 /* GPIO 4 */ |
| 2123 | #define nPx4 0x0 | ||
| 2124 | #define Px5 0x20 /* GPIO 5 */ | 1959 | #define Px5 0x20 /* GPIO 5 */ |
| 2125 | #define nPx5 0x0 | ||
| 2126 | #define Px6 0x40 /* GPIO 6 */ | 1960 | #define Px6 0x40 /* GPIO 6 */ |
| 2127 | #define nPx6 0x0 | ||
| 2128 | #define Px7 0x80 /* GPIO 7 */ | 1961 | #define Px7 0x80 /* GPIO 7 */ |
| 2129 | #define nPx7 0x0 | ||
| 2130 | #define Px8 0x100 /* GPIO 8 */ | 1962 | #define Px8 0x100 /* GPIO 8 */ |
| 2131 | #define nPx8 0x0 | ||
| 2132 | #define Px9 0x200 /* GPIO 9 */ | 1963 | #define Px9 0x200 /* GPIO 9 */ |
| 2133 | #define nPx9 0x0 | ||
| 2134 | #define Px10 0x400 /* GPIO 10 */ | 1964 | #define Px10 0x400 /* GPIO 10 */ |
| 2135 | #define nPx10 0x0 | ||
| 2136 | #define Px11 0x800 /* GPIO 11 */ | 1965 | #define Px11 0x800 /* GPIO 11 */ |
| 2137 | #define nPx11 0x0 | ||
| 2138 | #define Px12 0x1000 /* GPIO 12 */ | 1966 | #define Px12 0x1000 /* GPIO 12 */ |
| 2139 | #define nPx12 0x0 | ||
| 2140 | #define Px13 0x2000 /* GPIO 13 */ | 1967 | #define Px13 0x2000 /* GPIO 13 */ |
| 2141 | #define nPx13 0x0 | ||
| 2142 | #define Px14 0x4000 /* GPIO 14 */ | 1968 | #define Px14 0x4000 /* GPIO 14 */ |
| 2143 | #define nPx14 0x0 | ||
| 2144 | #define Px15 0x8000 /* GPIO 15 */ | 1969 | #define Px15 0x8000 /* GPIO 15 */ |
| 2145 | #define nPx15 0x0 | ||
| 2146 | 1970 | ||
| 2147 | /* Bit masks for PORTA_MUX - PORTJ_MUX */ | 1971 | /* Bit masks for PORTA_MUX - PORTJ_MUX */ |
| 2148 | 1972 | ||
| @@ -2167,223 +1991,129 @@ | |||
| 2167 | /* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ | 1991 | /* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ |
| 2168 | 1992 | ||
| 2169 | #define IB0 0x1 /* Interrupt Bit 0 */ | 1993 | #define IB0 0x1 /* Interrupt Bit 0 */ |
| 2170 | #define nIB0 0x0 | ||
| 2171 | #define IB1 0x2 /* Interrupt Bit 1 */ | 1994 | #define IB1 0x2 /* Interrupt Bit 1 */ |
| 2172 | #define nIB1 0x0 | ||
| 2173 | #define IB2 0x4 /* Interrupt Bit 2 */ | 1995 | #define IB2 0x4 /* Interrupt Bit 2 */ |
| 2174 | #define nIB2 0x0 | ||
| 2175 | #define IB3 0x8 /* Interrupt Bit 3 */ | 1996 | #define IB3 0x8 /* Interrupt Bit 3 */ |
| 2176 | #define nIB3 0x0 | ||
| 2177 | #define IB4 0x10 /* Interrupt Bit 4 */ | 1997 | #define IB4 0x10 /* Interrupt Bit 4 */ |
| 2178 | #define nIB4 0x0 | ||
| 2179 | #define IB5 0x20 /* Interrupt Bit 5 */ | 1998 | #define IB5 0x20 /* Interrupt Bit 5 */ |
| 2180 | #define nIB5 0x0 | ||
| 2181 | #define IB6 0x40 /* Interrupt Bit 6 */ | 1999 | #define IB6 0x40 /* Interrupt Bit 6 */ |
| 2182 | #define nIB6 0x0 | ||
| 2183 | #define IB7 0x80 /* Interrupt Bit 7 */ | 2000 | #define IB7 0x80 /* Interrupt Bit 7 */ |
| 2184 | #define nIB7 0x0 | ||
| 2185 | #define IB8 0x100 /* Interrupt Bit 8 */ | 2001 | #define IB8 0x100 /* Interrupt Bit 8 */ |
| 2186 | #define nIB8 0x0 | ||
| 2187 | #define IB9 0x200 /* Interrupt Bit 9 */ | 2002 | #define IB9 0x200 /* Interrupt Bit 9 */ |
| 2188 | #define nIB9 0x0 | ||
| 2189 | #define IB10 0x400 /* Interrupt Bit 10 */ | 2003 | #define IB10 0x400 /* Interrupt Bit 10 */ |
| 2190 | #define nIB10 0x0 | ||
| 2191 | #define IB11 0x800 /* Interrupt Bit 11 */ | 2004 | #define IB11 0x800 /* Interrupt Bit 11 */ |
| 2192 | #define nIB11 0x0 | ||
| 2193 | #define IB12 0x1000 /* Interrupt Bit 12 */ | 2005 | #define IB12 0x1000 /* Interrupt Bit 12 */ |
| 2194 | #define nIB12 0x0 | ||
| 2195 | #define IB13 0x2000 /* Interrupt Bit 13 */ | 2006 | #define IB13 0x2000 /* Interrupt Bit 13 */ |
| 2196 | #define nIB13 0x0 | ||
| 2197 | #define IB14 0x4000 /* Interrupt Bit 14 */ | 2007 | #define IB14 0x4000 /* Interrupt Bit 14 */ |
| 2198 | #define nIB14 0x0 | ||
| 2199 | #define IB15 0x8000 /* Interrupt Bit 15 */ | 2008 | #define IB15 0x8000 /* Interrupt Bit 15 */ |
| 2200 | #define nIB15 0x0 | ||
| 2201 | 2009 | ||
| 2202 | /* Bit masks for TIMERx_CONFIG */ | 2010 | /* Bit masks for TIMERx_CONFIG */ |
| 2203 | 2011 | ||
| 2204 | #define TMODE 0x3 /* Timer Mode */ | 2012 | #define TMODE 0x3 /* Timer Mode */ |
| 2205 | #define PULSE_HI 0x4 /* Pulse Polarity */ | 2013 | #define PULSE_HI 0x4 /* Pulse Polarity */ |
| 2206 | #define nPULSE_HI 0x0 | ||
| 2207 | #define PERIOD_CNT 0x8 /* Period Count */ | 2014 | #define PERIOD_CNT 0x8 /* Period Count */ |
| 2208 | #define nPERIOD_CNT 0x0 | ||
| 2209 | #define IRQ_ENA 0x10 /* Interrupt Request Enable */ | 2015 | #define IRQ_ENA 0x10 /* Interrupt Request Enable */ |
| 2210 | #define nIRQ_ENA 0x0 | ||
| 2211 | #define TIN_SEL 0x20 /* Timer Input Select */ | 2016 | #define TIN_SEL 0x20 /* Timer Input Select */ |
| 2212 | #define nTIN_SEL 0x0 | ||
| 2213 | #define OUT_DIS 0x40 /* Output Pad Disable */ | 2017 | #define OUT_DIS 0x40 /* Output Pad Disable */ |
| 2214 | #define nOUT_DIS 0x0 | ||
| 2215 | #define CLK_SEL 0x80 /* Timer Clock Select */ | 2018 | #define CLK_SEL 0x80 /* Timer Clock Select */ |
| 2216 | #define nCLK_SEL 0x0 | ||
| 2217 | #define TOGGLE_HI 0x100 /* Toggle Mode */ | 2019 | #define TOGGLE_HI 0x100 /* Toggle Mode */ |
| 2218 | #define nTOGGLE_HI 0x0 | ||
| 2219 | #define EMU_RUN 0x200 /* Emulation Behavior Select */ | 2020 | #define EMU_RUN 0x200 /* Emulation Behavior Select */ |
| 2220 | #define nEMU_RUN 0x0 | ||
| 2221 | #define ERR_TYP 0xc000 /* Error Type */ | 2021 | #define ERR_TYP 0xc000 /* Error Type */ |
| 2222 | 2022 | ||
| 2223 | /* Bit masks for TIMER_ENABLE0 */ | 2023 | /* Bit masks for TIMER_ENABLE0 */ |
| 2224 | 2024 | ||
| 2225 | #define TIMEN0 0x1 /* Timer 0 Enable */ | 2025 | #define TIMEN0 0x1 /* Timer 0 Enable */ |
| 2226 | #define nTIMEN0 0x0 | ||
| 2227 | #define TIMEN1 0x2 /* Timer 1 Enable */ | 2026 | #define TIMEN1 0x2 /* Timer 1 Enable */ |
| 2228 | #define nTIMEN1 0x0 | ||
| 2229 | #define TIMEN2 0x4 /* Timer 2 Enable */ | 2027 | #define TIMEN2 0x4 /* Timer 2 Enable */ |
| 2230 | #define nTIMEN2 0x0 | ||
| 2231 | #define TIMEN3 0x8 /* Timer 3 Enable */ | 2028 | #define TIMEN3 0x8 /* Timer 3 Enable */ |
| 2232 | #define nTIMEN3 0x0 | ||
| 2233 | #define TIMEN4 0x10 /* Timer 4 Enable */ | 2029 | #define TIMEN4 0x10 /* Timer 4 Enable */ |
| 2234 | #define nTIMEN4 0x0 | ||
| 2235 | #define TIMEN5 0x20 /* Timer 5 Enable */ | 2030 | #define TIMEN5 0x20 /* Timer 5 Enable */ |
| 2236 | #define nTIMEN5 0x0 | ||
| 2237 | #define TIMEN6 0x40 /* Timer 6 Enable */ | 2031 | #define TIMEN6 0x40 /* Timer 6 Enable */ |
| 2238 | #define nTIMEN6 0x0 | ||
| 2239 | #define TIMEN7 0x80 /* Timer 7 Enable */ | 2032 | #define TIMEN7 0x80 /* Timer 7 Enable */ |
| 2240 | #define nTIMEN7 0x0 | ||
| 2241 | 2033 | ||
| 2242 | /* Bit masks for TIMER_DISABLE0 */ | 2034 | /* Bit masks for TIMER_DISABLE0 */ |
| 2243 | 2035 | ||
| 2244 | #define TIMDIS0 0x1 /* Timer 0 Disable */ | 2036 | #define TIMDIS0 0x1 /* Timer 0 Disable */ |
| 2245 | #define nTIMDIS0 0x0 | ||
| 2246 | #define TIMDIS1 0x2 /* Timer 1 Disable */ | 2037 | #define TIMDIS1 0x2 /* Timer 1 Disable */ |
| 2247 | #define nTIMDIS1 0x0 | ||
| 2248 | #define TIMDIS2 0x4 /* Timer 2 Disable */ | 2038 | #define TIMDIS2 0x4 /* Timer 2 Disable */ |
| 2249 | #define nTIMDIS2 0x0 | ||
| 2250 | #define TIMDIS3 0x8 /* Timer 3 Disable */ | 2039 | #define TIMDIS3 0x8 /* Timer 3 Disable */ |
| 2251 | #define nTIMDIS3 0x0 | ||
| 2252 | #define TIMDIS4 0x10 /* Timer 4 Disable */ | 2040 | #define TIMDIS4 0x10 /* Timer 4 Disable */ |
| 2253 | #define nTIMDIS4 0x0 | ||
| 2254 | #define TIMDIS5 0x20 /* Timer 5 Disable */ | 2041 | #define TIMDIS5 0x20 /* Timer 5 Disable */ |
| 2255 | #define nTIMDIS5 0x0 | ||
| 2256 | #define TIMDIS6 0x40 /* Timer 6 Disable */ | 2042 | #define TIMDIS6 0x40 /* Timer 6 Disable */ |
| 2257 | #define nTIMDIS6 0x0 | ||
| 2258 | #define TIMDIS7 0x80 /* Timer 7 Disable */ | 2043 | #define TIMDIS7 0x80 /* Timer 7 Disable */ |
| 2259 | #define nTIMDIS7 0x0 | ||
| 2260 | 2044 | ||
| 2261 | /* Bit masks for TIMER_STATUS0 */ | 2045 | /* Bit masks for TIMER_STATUS0 */ |
| 2262 | 2046 | ||
| 2263 | #define TIMIL0 0x1 /* Timer 0 Interrupt */ | 2047 | #define TIMIL0 0x1 /* Timer 0 Interrupt */ |
| 2264 | #define nTIMIL0 0x0 | ||
| 2265 | #define TIMIL1 0x2 /* Timer 1 Interrupt */ | 2048 | #define TIMIL1 0x2 /* Timer 1 Interrupt */ |
| 2266 | #define nTIMIL1 0x0 | ||
| 2267 | #define TIMIL2 0x4 /* Timer 2 Interrupt */ | 2049 | #define TIMIL2 0x4 /* Timer 2 Interrupt */ |
| 2268 | #define nTIMIL2 0x0 | ||
| 2269 | #define TIMIL3 0x8 /* Timer 3 Interrupt */ | 2050 | #define TIMIL3 0x8 /* Timer 3 Interrupt */ |
| 2270 | #define nTIMIL3 0x0 | ||
| 2271 | #define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ | 2051 | #define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ |
| 2272 | #define nTOVF_ERR0 0x0 | ||
| 2273 | #define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ | 2052 | #define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ |
| 2274 | #define nTOVF_ERR1 0x0 | ||
| 2275 | #define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ | 2053 | #define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ |
| 2276 | #define nTOVF_ERR2 0x0 | ||
| 2277 | #define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ | 2054 | #define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ |
| 2278 | #define nTOVF_ERR3 0x0 | ||
| 2279 | #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ | 2055 | #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ |
| 2280 | #define nTRUN0 0x0 | ||
| 2281 | #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ | 2056 | #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ |
| 2282 | #define nTRUN1 0x0 | ||
| 2283 | #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ | 2057 | #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ |
| 2284 | #define nTRUN2 0x0 | ||
| 2285 | #define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ | 2058 | #define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ |
| 2286 | #define nTRUN3 0x0 | ||
| 2287 | #define TIMIL4 0x10000 /* Timer 4 Interrupt */ | 2059 | #define TIMIL4 0x10000 /* Timer 4 Interrupt */ |
| 2288 | #define nTIMIL4 0x0 | ||
| 2289 | #define TIMIL5 0x20000 /* Timer 5 Interrupt */ | 2060 | #define TIMIL5 0x20000 /* Timer 5 Interrupt */ |
| 2290 | #define nTIMIL5 0x0 | ||
| 2291 | #define TIMIL6 0x40000 /* Timer 6 Interrupt */ | 2061 | #define TIMIL6 0x40000 /* Timer 6 Interrupt */ |
| 2292 | #define nTIMIL6 0x0 | ||
| 2293 | #define TIMIL7 0x80000 /* Timer 7 Interrupt */ | 2062 | #define TIMIL7 0x80000 /* Timer 7 Interrupt */ |
| 2294 | #define nTIMIL7 0x0 | ||
| 2295 | #define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ | 2063 | #define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ |
| 2296 | #define nTOVF_ERR4 0x0 | ||
| 2297 | #define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ | 2064 | #define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ |
| 2298 | #define nTOVF_ERR5 0x0 | ||
| 2299 | #define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ | 2065 | #define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ |
| 2300 | #define nTOVF_ERR6 0x0 | ||
| 2301 | #define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ | 2066 | #define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ |
| 2302 | #define nTOVF_ERR7 0x0 | ||
| 2303 | #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ | 2067 | #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ |
| 2304 | #define nTRUN4 0x0 | ||
| 2305 | #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ | 2068 | #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ |
| 2306 | #define nTRUN5 0x0 | ||
| 2307 | #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ | 2069 | #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ |
| 2308 | #define nTRUN6 0x0 | ||
| 2309 | #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ | 2070 | #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ |
| 2310 | #define nTRUN7 0x0 | ||
| 2311 | 2071 | ||
| 2312 | /* Bit masks for WDOG_CTL */ | 2072 | /* Bit masks for WDOG_CTL */ |
| 2313 | 2073 | ||
| 2314 | #define WDEV 0x6 /* Watchdog Event */ | 2074 | #define WDEV 0x6 /* Watchdog Event */ |
| 2315 | #define WDEN 0xff0 /* Watchdog Enable */ | 2075 | #define WDEN 0xff0 /* Watchdog Enable */ |
| 2316 | #define WDRO 0x8000 /* Watchdog Rolled Over */ | 2076 | #define WDRO 0x8000 /* Watchdog Rolled Over */ |
| 2317 | #define nWDRO 0x0 | ||
| 2318 | 2077 | ||
| 2319 | /* Bit masks for CNT_CONFIG */ | 2078 | /* Bit masks for CNT_CONFIG */ |
| 2320 | 2079 | ||
| 2321 | #define CNTE 0x1 /* Counter Enable */ | 2080 | #define CNTE 0x1 /* Counter Enable */ |
| 2322 | #define nCNTE 0x0 | ||
| 2323 | #define DEBE 0x2 /* Debounce Enable */ | 2081 | #define DEBE 0x2 /* Debounce Enable */ |
| 2324 | #define nDEBE 0x0 | ||
| 2325 | #define CDGINV 0x10 /* CDG Pin Polarity Invert */ | 2082 | #define CDGINV 0x10 /* CDG Pin Polarity Invert */ |
| 2326 | #define nCDGINV 0x0 | ||
| 2327 | #define CUDINV 0x20 /* CUD Pin Polarity Invert */ | 2083 | #define CUDINV 0x20 /* CUD Pin Polarity Invert */ |
| 2328 | #define nCUDINV 0x0 | ||
| 2329 | #define CZMINV 0x40 /* CZM Pin Polarity Invert */ | 2084 | #define CZMINV 0x40 /* CZM Pin Polarity Invert */ |
| 2330 | #define nCZMINV 0x0 | ||
| 2331 | #define CNTMODE 0x700 /* Counter Operating Mode */ | 2085 | #define CNTMODE 0x700 /* Counter Operating Mode */ |
| 2332 | #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ | 2086 | #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ |
| 2333 | #define nZMZC 0x0 | ||
| 2334 | #define BNDMODE 0x3000 /* Boundary register Mode */ | 2087 | #define BNDMODE 0x3000 /* Boundary register Mode */ |
| 2335 | #define INPDIS 0x8000 /* CUG and CDG Input Disable */ | 2088 | #define INPDIS 0x8000 /* CUG and CDG Input Disable */ |
| 2336 | #define nINPDIS 0x0 | ||
| 2337 | 2089 | ||
| 2338 | /* Bit masks for CNT_IMASK */ | 2090 | /* Bit masks for CNT_IMASK */ |
| 2339 | 2091 | ||
| 2340 | #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ | 2092 | #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ |
| 2341 | #define nICIE 0x0 | ||
| 2342 | #define UCIE 0x2 /* Up count Interrupt Enable */ | 2093 | #define UCIE 0x2 /* Up count Interrupt Enable */ |
| 2343 | #define nUCIE 0x0 | ||
| 2344 | #define DCIE 0x4 /* Down count Interrupt Enable */ | 2094 | #define DCIE 0x4 /* Down count Interrupt Enable */ |
| 2345 | #define nDCIE 0x0 | ||
| 2346 | #define MINCIE 0x8 /* Min Count Interrupt Enable */ | 2095 | #define MINCIE 0x8 /* Min Count Interrupt Enable */ |
| 2347 | #define nMINCIE 0x0 | ||
| 2348 | #define MAXCIE 0x10 /* Max Count Interrupt Enable */ | 2096 | #define MAXCIE 0x10 /* Max Count Interrupt Enable */ |
| 2349 | #define nMAXCIE 0x0 | ||
| 2350 | #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ | 2097 | #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ |
| 2351 | #define nCOV31IE 0x0 | ||
| 2352 | #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ | 2098 | #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ |
| 2353 | #define nCOV15IE 0x0 | ||
| 2354 | #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ | 2099 | #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ |
| 2355 | #define nCZEROIE 0x0 | ||
| 2356 | #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ | 2100 | #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ |
| 2357 | #define nCZMIE 0x0 | ||
| 2358 | #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ | 2101 | #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ |
| 2359 | #define nCZMEIE 0x0 | ||
| 2360 | #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ | 2102 | #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ |
| 2361 | #define nCZMZIE 0x0 | ||
| 2362 | 2103 | ||
| 2363 | /* Bit masks for CNT_STATUS */ | 2104 | /* Bit masks for CNT_STATUS */ |
| 2364 | 2105 | ||
| 2365 | #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ | 2106 | #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ |
| 2366 | #define nICII 0x0 | ||
| 2367 | #define UCII 0x2 /* Up count Interrupt Identifier */ | 2107 | #define UCII 0x2 /* Up count Interrupt Identifier */ |
| 2368 | #define nUCII 0x0 | ||
| 2369 | #define DCII 0x4 /* Down count Interrupt Identifier */ | 2108 | #define DCII 0x4 /* Down count Interrupt Identifier */ |
| 2370 | #define nDCII 0x0 | ||
| 2371 | #define MINCII 0x8 /* Min Count Interrupt Identifier */ | 2109 | #define MINCII 0x8 /* Min Count Interrupt Identifier */ |
| 2372 | #define nMINCII 0x0 | ||
| 2373 | #define MAXCII 0x10 /* Max Count Interrupt Identifier */ | 2110 | #define MAXCII 0x10 /* Max Count Interrupt Identifier */ |
| 2374 | #define nMAXCII 0x0 | ||
| 2375 | #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ | 2111 | #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ |
| 2376 | #define nCOV31II 0x0 | ||
| 2377 | #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ | 2112 | #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ |
| 2378 | #define nCOV15II 0x0 | ||
| 2379 | #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ | 2113 | #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ |
| 2380 | #define nCZEROII 0x0 | ||
| 2381 | #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ | 2114 | #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ |
| 2382 | #define nCZMII 0x0 | ||
| 2383 | #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ | 2115 | #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ |
| 2384 | #define nCZMEII 0x0 | ||
| 2385 | #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ | 2116 | #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ |
| 2386 | #define nCZMZII 0x0 | ||
| 2387 | 2117 | ||
| 2388 | /* Bit masks for CNT_COMMAND */ | 2118 | /* Bit masks for CNT_COMMAND */ |
| 2389 | 2119 | ||
| @@ -2391,7 +2121,6 @@ | |||
| 2391 | #define W1LMIN 0xf0 /* Load Min Register */ | 2121 | #define W1LMIN 0xf0 /* Load Min Register */ |
| 2392 | #define W1LMAX 0xf00 /* Load Max Register */ | 2122 | #define W1LMAX 0xf00 /* Load Max Register */ |
| 2393 | #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ | 2123 | #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ |
| 2394 | #define nW1ZMONCE 0x0 | ||
| 2395 | 2124 | ||
| 2396 | /* Bit masks for CNT_DEBOUNCE */ | 2125 | /* Bit masks for CNT_DEBOUNCE */ |
| 2397 | 2126 | ||
| @@ -2407,42 +2136,25 @@ | |||
| 2407 | /* Bit masks for RTC_ICTL */ | 2136 | /* Bit masks for RTC_ICTL */ |
| 2408 | 2137 | ||
| 2409 | #define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ | 2138 | #define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ |
| 2410 | #define nSTOPWATCH_INTERRUPT_ENABLE 0x0 | ||
| 2411 | #define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ | 2139 | #define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ |
| 2412 | #define nALARM_INTERRUPT_ENABLE 0x0 | ||
| 2413 | #define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ | 2140 | #define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ |
| 2414 | #define nSECONDS_INTERRUPT_ENABLE 0x0 | ||
| 2415 | #define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ | 2141 | #define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ |
| 2416 | #define nMINUTES_INTERRUPT_ENABLE 0x0 | ||
| 2417 | #define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ | 2142 | #define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ |
| 2418 | #define nHOURS_INTERRUPT_ENABLE 0x0 | ||
| 2419 | #define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ | 2143 | #define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ |
| 2420 | #define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0 | ||
| 2421 | #define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ | 2144 | #define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ |
| 2422 | #define nDAY_ALARM_INTERRUPT_ENABLE 0x0 | ||
| 2423 | #define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ | 2145 | #define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ |
| 2424 | #define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0 | ||
| 2425 | 2146 | ||
| 2426 | /* Bit masks for RTC_ISTAT */ | 2147 | /* Bit masks for RTC_ISTAT */ |
| 2427 | 2148 | ||
| 2428 | #define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ | 2149 | #define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ |
| 2429 | #define nSTOPWATCH_EVENT_FLAG 0x0 | ||
| 2430 | #define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ | 2150 | #define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ |
| 2431 | #define nALARM_EVENT_FLAG 0x0 | ||
| 2432 | #define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ | 2151 | #define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ |
| 2433 | #define nSECONDS_EVENT_FLAG 0x0 | ||
| 2434 | #define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ | 2152 | #define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ |
| 2435 | #define nMINUTES_EVENT_FLAG 0x0 | ||
| 2436 | #define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ | 2153 | #define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ |
| 2437 | #define nHOURS_EVENT_FLAG 0x0 | ||
| 2438 | #define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ | 2154 | #define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ |
| 2439 | #define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0 | ||
| 2440 | #define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ | 2155 | #define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ |
| 2441 | #define nDAY_ALARM_EVENT_FLAG 0x0 | ||
| 2442 | #define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ | 2156 | #define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ |
| 2443 | #define nWRITE_PENDING__STATUS 0x0 | ||
| 2444 | #define WRITE_COMPLETE 0x8000 /* Write Complete */ | 2157 | #define WRITE_COMPLETE 0x8000 /* Write Complete */ |
| 2445 | #define nWRITE_COMPLETE 0x0 | ||
| 2446 | 2158 | ||
| 2447 | /* Bit masks for RTC_SWCNT */ | 2159 | /* Bit masks for RTC_SWCNT */ |
| 2448 | 2160 | ||
| @@ -2458,21 +2170,15 @@ | |||
| 2458 | /* Bit masks for RTC_PREN */ | 2170 | /* Bit masks for RTC_PREN */ |
| 2459 | 2171 | ||
| 2460 | #define PREN 0x1 /* Prescaler Enable */ | 2172 | #define PREN 0x1 /* Prescaler Enable */ |
| 2461 | #define nPREN 0x0 | ||
| 2462 | 2173 | ||
| 2463 | /* Bit masks for OTP_CONTROL */ | 2174 | /* Bit masks for OTP_CONTROL */ |
| 2464 | 2175 | ||
| 2465 | #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ | 2176 | #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ |
| 2466 | #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ | 2177 | #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ |
| 2467 | #define nFIEN 0x0 | ||
| 2468 | #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ | 2178 | #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ |
| 2469 | #define nFTESTDEC 0x0 | ||
| 2470 | #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ | 2179 | #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ |
| 2471 | #define nFWRTEST 0x0 | ||
| 2472 | #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ | 2180 | #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ |
| 2473 | #define nFRDEN 0x0 | ||
| 2474 | #define FWREN 0x8000 /* OTP/Fuse Write Enable */ | 2181 | #define FWREN 0x8000 /* OTP/Fuse Write Enable */ |
| 2475 | #define nFWREN 0x0 | ||
| 2476 | 2182 | ||
| 2477 | /* Bit masks for OTP_BEN */ | 2183 | /* Bit masks for OTP_BEN */ |
| 2478 | 2184 | ||
| @@ -2481,15 +2187,10 @@ | |||
| 2481 | /* Bit masks for OTP_STATUS */ | 2187 | /* Bit masks for OTP_STATUS */ |
| 2482 | 2188 | ||
| 2483 | #define FCOMP 0x1 /* OTP/Fuse Access Complete */ | 2189 | #define FCOMP 0x1 /* OTP/Fuse Access Complete */ |
| 2484 | #define nFCOMP 0x0 | ||
| 2485 | #define FERROR 0x2 /* OTP/Fuse Access Error */ | 2190 | #define FERROR 0x2 /* OTP/Fuse Access Error */ |
| 2486 | #define nFERROR 0x0 | ||
| 2487 | #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ | 2191 | #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ |
| 2488 | #define nMMRGLOAD 0x0 | ||
| 2489 | #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ | 2192 | #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ |
| 2490 | #define nMMRGLOCK 0x0 | ||
| 2491 | #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ | 2193 | #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ |
| 2492 | #define nFPGMEN 0x0 | ||
| 2493 | 2194 | ||
| 2494 | /* Bit masks for OTP_TIMING */ | 2195 | /* Bit masks for OTP_TIMING */ |
| 2495 | 2196 | ||
| @@ -2503,42 +2204,29 @@ | |||
| 2503 | /* Bit masks for SECURE_SYSSWT */ | 2204 | /* Bit masks for SECURE_SYSSWT */ |
| 2504 | 2205 | ||
| 2505 | #define EMUDABL 0x1 /* Emulation Disable. */ | 2206 | #define EMUDABL 0x1 /* Emulation Disable. */ |
| 2506 | #define nEMUDABL 0x0 | ||
| 2507 | #define RSTDABL 0x2 /* Reset Disable */ | 2207 | #define RSTDABL 0x2 /* Reset Disable */ |
| 2508 | #define nRSTDABL 0x0 | ||
| 2509 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ | 2208 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ |
| 2510 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ | 2209 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ |
| 2511 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ | 2210 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ |
| 2512 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ | 2211 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ |
| 2513 | #define nDMA0OVR 0x0 | ||
| 2514 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ | 2212 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ |
| 2515 | #define nDMA1OVR 0x0 | ||
| 2516 | #define EMUOVR 0x4000 /* Emulation Override */ | 2213 | #define EMUOVR 0x4000 /* Emulation Override */ |
| 2517 | #define nEMUOVR 0x0 | ||
| 2518 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ | 2214 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ |
| 2519 | #define nOTPSEN 0x0 | ||
| 2520 | #define L2DABL 0x70000 /* L2 Memory Disable. */ | 2215 | #define L2DABL 0x70000 /* L2 Memory Disable. */ |
| 2521 | 2216 | ||
| 2522 | /* Bit masks for SECURE_CONTROL */ | 2217 | /* Bit masks for SECURE_CONTROL */ |
| 2523 | 2218 | ||
| 2524 | #define SECURE0 0x1 /* SECURE 0 */ | 2219 | #define SECURE0 0x1 /* SECURE 0 */ |
| 2525 | #define nSECURE0 0x0 | ||
| 2526 | #define SECURE1 0x2 /* SECURE 1 */ | 2220 | #define SECURE1 0x2 /* SECURE 1 */ |
| 2527 | #define nSECURE1 0x0 | ||
| 2528 | #define SECURE2 0x4 /* SECURE 2 */ | 2221 | #define SECURE2 0x4 /* SECURE 2 */ |
| 2529 | #define nSECURE2 0x0 | ||
| 2530 | #define SECURE3 0x8 /* SECURE 3 */ | 2222 | #define SECURE3 0x8 /* SECURE 3 */ |
| 2531 | #define nSECURE3 0x0 | ||
| 2532 | 2223 | ||
| 2533 | /* Bit masks for SECURE_STATUS */ | 2224 | /* Bit masks for SECURE_STATUS */ |
| 2534 | 2225 | ||
| 2535 | #define SECMODE 0x3 /* Secured Mode Control State */ | 2226 | #define SECMODE 0x3 /* Secured Mode Control State */ |
| 2536 | #define NMI 0x4 /* Non Maskable Interrupt */ | 2227 | #define NMI 0x4 /* Non Maskable Interrupt */ |
| 2537 | #define nNMI 0x0 | ||
| 2538 | #define AFVALID 0x8 /* Authentication Firmware Valid */ | 2228 | #define AFVALID 0x8 /* Authentication Firmware Valid */ |
| 2539 | #define nAFVALID 0x0 | ||
| 2540 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ | 2229 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ |
| 2541 | #define nAFEXIT 0x0 | ||
| 2542 | #define SECSTAT 0xe0 /* Secure Status */ | 2230 | #define SECSTAT 0xe0 /* Secure Status */ |
| 2543 | 2231 | ||
| 2544 | /* Bit masks for PLL_DIV */ | 2232 | /* Bit masks for PLL_DIV */ |
| @@ -2550,42 +2238,25 @@ | |||
| 2550 | 2238 | ||
| 2551 | #define MSEL 0x7e00 /* Multiplier Select */ | 2239 | #define MSEL 0x7e00 /* Multiplier Select */ |
| 2552 | #define BYPASS 0x100 /* PLL Bypass Enable */ | 2240 | #define BYPASS 0x100 /* PLL Bypass Enable */ |
| 2553 | #define nBYPASS 0x0 | ||
| 2554 | #define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ | 2241 | #define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ |
| 2555 | #define nOUTPUT_DELAY 0x0 | ||
| 2556 | #define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ | 2242 | #define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ |
| 2557 | #define nINPUT_DELAY 0x0 | ||
| 2558 | #define PDWN 0x20 /* Power Down */ | 2243 | #define PDWN 0x20 /* Power Down */ |
| 2559 | #define nPDWN 0x0 | ||
| 2560 | #define STOPCK 0x8 /* Stop Clock */ | 2244 | #define STOPCK 0x8 /* Stop Clock */ |
| 2561 | #define nSTOPCK 0x0 | ||
| 2562 | #define PLL_OFF 0x2 /* Disable PLL */ | 2245 | #define PLL_OFF 0x2 /* Disable PLL */ |
| 2563 | #define nPLL_OFF 0x0 | ||
| 2564 | #define DF 0x1 /* Divide Frequency */ | 2246 | #define DF 0x1 /* Divide Frequency */ |
| 2565 | #define nDF 0x0 | ||
| 2566 | 2247 | ||
| 2567 | /* Bit masks for PLL_STAT */ | 2248 | /* Bit masks for PLL_STAT */ |
| 2568 | 2249 | ||
| 2569 | #define PLL_LOCKED 0x20 /* PLL Locked Status */ | 2250 | #define PLL_LOCKED 0x20 /* PLL Locked Status */ |
| 2570 | #define nPLL_LOCKED 0x0 | ||
| 2571 | #define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ | 2251 | #define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ |
| 2572 | #define nACTIVE_PLLDISABLED 0x0 | ||
| 2573 | #define FULL_ON 0x2 /* Full-On Mode */ | 2252 | #define FULL_ON 0x2 /* Full-On Mode */ |
| 2574 | #define nFULL_ON 0x0 | ||
| 2575 | #define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ | 2253 | #define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ |
| 2576 | #define nACTIVE_PLLENABLED 0x0 | ||
| 2577 | #define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ | 2254 | #define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ |
| 2578 | #define nRTCWS 0x0 | ||
| 2579 | #define CANWS 0x800 /* CAN Wake-Up Status */ | 2255 | #define CANWS 0x800 /* CAN Wake-Up Status */ |
| 2580 | #define nCANWS 0x0 | ||
| 2581 | #define USBWS 0x2000 /* USB Wake-Up Status */ | 2256 | #define USBWS 0x2000 /* USB Wake-Up Status */ |
| 2582 | #define nUSBWS 0x0 | ||
| 2583 | #define KPADWS 0x4000 /* Keypad Wake-Up Status */ | 2257 | #define KPADWS 0x4000 /* Keypad Wake-Up Status */ |
| 2584 | #define nKPADWS 0x0 | ||
| 2585 | #define ROTWS 0x8000 /* Rotary Wake-Up Status */ | 2258 | #define ROTWS 0x8000 /* Rotary Wake-Up Status */ |
| 2586 | #define nROTWS 0x0 | ||
| 2587 | #define GPWS 0x1000 /* General-Purpose Wake-Up Status */ | 2259 | #define GPWS 0x1000 /* General-Purpose Wake-Up Status */ |
| 2588 | #define nGPWS 0x0 | ||
| 2589 | 2260 | ||
| 2590 | /* Bit masks for VR_CTL */ | 2261 | /* Bit masks for VR_CTL */ |
| 2591 | 2262 | ||
| @@ -2593,79 +2264,52 @@ | |||
| 2593 | #define GAIN 0xc /* Voltage Output Level Gain */ | 2264 | #define GAIN 0xc /* Voltage Output Level Gain */ |
| 2594 | #define VLEV 0xf0 /* Internal Voltage Level */ | 2265 | #define VLEV 0xf0 /* Internal Voltage Level */ |
| 2595 | #define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ | 2266 | #define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ |
| 2596 | #define nSCKELOW 0x0 | ||
| 2597 | #define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ | 2267 | #define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ |
| 2598 | #define nWAKE 0x0 | ||
| 2599 | #define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ | 2268 | #define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ |
| 2600 | #define nCANWE 0x0 | ||
| 2601 | #define GPWE 0x400 /* General-Purpose Wake-Up Enable */ | 2269 | #define GPWE 0x400 /* General-Purpose Wake-Up Enable */ |
| 2602 | #define nGPWE 0x0 | ||
| 2603 | #define USBWE 0x800 /* USB Wake-Up Enable */ | 2270 | #define USBWE 0x800 /* USB Wake-Up Enable */ |
| 2604 | #define nUSBWE 0x0 | ||
| 2605 | #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ | 2271 | #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ |
| 2606 | #define nKPADWE 0x0 | ||
| 2607 | #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ | 2272 | #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ |
| 2608 | #define nROTWE 0x0 | ||
| 2609 | 2273 | ||
| 2610 | /* Bit masks for NFC_CTL */ | 2274 | /* Bit masks for NFC_CTL */ |
| 2611 | 2275 | ||
| 2612 | #define WR_DLY 0xf /* Write Strobe Delay */ | 2276 | #define WR_DLY 0xf /* Write Strobe Delay */ |
| 2613 | #define RD_DLY 0xf0 /* Read Strobe Delay */ | 2277 | #define RD_DLY 0xf0 /* Read Strobe Delay */ |
| 2614 | #define NWIDTH 0x100 /* NAND Data Width */ | 2278 | #define NWIDTH 0x100 /* NAND Data Width */ |
| 2615 | #define nNWIDTH 0x0 | ||
| 2616 | #define PG_SIZE 0x200 /* Page Size */ | 2279 | #define PG_SIZE 0x200 /* Page Size */ |
| 2617 | #define nPG_SIZE 0x0 | ||
| 2618 | 2280 | ||
| 2619 | /* Bit masks for NFC_STAT */ | 2281 | /* Bit masks for NFC_STAT */ |
| 2620 | 2282 | ||
| 2621 | #define NBUSY 0x1 /* Not Busy */ | 2283 | #define NBUSY 0x1 /* Not Busy */ |
| 2622 | #define nNBUSY 0x0 | ||
| 2623 | #define WB_FULL 0x2 /* Write Buffer Full */ | 2284 | #define WB_FULL 0x2 /* Write Buffer Full */ |
| 2624 | #define nWB_FULL 0x0 | ||
| 2625 | #define PG_WR_STAT 0x4 /* Page Write Pending */ | 2285 | #define PG_WR_STAT 0x4 /* Page Write Pending */ |
| 2626 | #define nPG_WR_STAT 0x0 | ||
| 2627 | #define PG_RD_STAT 0x8 /* Page Read Pending */ | 2286 | #define PG_RD_STAT 0x8 /* Page Read Pending */ |
| 2628 | #define nPG_RD_STAT 0x0 | ||
| 2629 | #define WB_EMPTY 0x10 /* Write Buffer Empty */ | 2287 | #define WB_EMPTY 0x10 /* Write Buffer Empty */ |
| 2630 | #define nWB_EMPTY 0x0 | ||
| 2631 | 2288 | ||
| 2632 | /* Bit masks for NFC_IRQSTAT */ | 2289 | /* Bit masks for NFC_IRQSTAT */ |
| 2633 | 2290 | ||
| 2634 | #define NBUSYIRQ 0x1 /* Not Busy IRQ */ | 2291 | #define NBUSYIRQ 0x1 /* Not Busy IRQ */ |
| 2635 | #define nNBUSYIRQ 0x0 | ||
| 2636 | #define WB_OVF 0x2 /* Write Buffer Overflow */ | 2292 | #define WB_OVF 0x2 /* Write Buffer Overflow */ |
| 2637 | #define nWB_OVF 0x0 | ||
| 2638 | #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ | 2293 | #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ |
| 2639 | #define nWB_EDGE 0x0 | ||
| 2640 | #define RD_RDY 0x8 /* Read Data Ready */ | 2294 | #define RD_RDY 0x8 /* Read Data Ready */ |
| 2641 | #define nRD_RDY 0x0 | ||
| 2642 | #define WR_DONE 0x10 /* Page Write Done */ | 2295 | #define WR_DONE 0x10 /* Page Write Done */ |
| 2643 | #define nWR_DONE 0x0 | ||
| 2644 | 2296 | ||
| 2645 | /* Bit masks for NFC_IRQMASK */ | 2297 | /* Bit masks for NFC_IRQMASK */ |
| 2646 | 2298 | ||
| 2647 | #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ | 2299 | #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ |
| 2648 | #define nMASK_BUSYIRQ 0x0 | ||
| 2649 | #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ | 2300 | #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ |
| 2650 | #define nMASK_WBOVF 0x0 | ||
| 2651 | #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ | 2301 | #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ |
| 2652 | #define nMASK_WBEMPTY 0x0 | ||
| 2653 | #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ | 2302 | #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ |
| 2654 | #define nMASK_RDRDY 0x0 | ||
| 2655 | #define MASK_WRDONE 0x10 /* Mask Write Done */ | 2303 | #define MASK_WRDONE 0x10 /* Mask Write Done */ |
| 2656 | #define nMASK_WRDONE 0x0 | ||
| 2657 | 2304 | ||
| 2658 | /* Bit masks for NFC_RST */ | 2305 | /* Bit masks for NFC_RST */ |
| 2659 | 2306 | ||
| 2660 | #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ | 2307 | #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ |
| 2661 | #define nECC_RST 0x0 | ||
| 2662 | 2308 | ||
| 2663 | /* Bit masks for NFC_PGCTL */ | 2309 | /* Bit masks for NFC_PGCTL */ |
| 2664 | 2310 | ||
| 2665 | #define PG_RD_START 0x1 /* Page Read Start */ | 2311 | #define PG_RD_START 0x1 /* Page Read Start */ |
| 2666 | #define nPG_RD_START 0x0 | ||
| 2667 | #define PG_WR_START 0x2 /* Page Write Start */ | 2312 | #define PG_WR_START 0x2 /* Page Write Start */ |
| 2668 | #define nPG_WR_START 0x0 | ||
| 2669 | 2313 | ||
| 2670 | /* Bit masks for NFC_ECC0 */ | 2314 | /* Bit masks for NFC_ECC0 */ |
| 2671 | 2315 | ||
| @@ -2690,56 +2334,34 @@ | |||
| 2690 | /* Bit masks for CAN0_CONTROL */ | 2334 | /* Bit masks for CAN0_CONTROL */ |
| 2691 | 2335 | ||
| 2692 | #define SRS 0x1 /* Software Reset */ | 2336 | #define SRS 0x1 /* Software Reset */ |
| 2693 | #define nSRS 0x0 | ||
| 2694 | #define DNM 0x2 /* DeviceNet Mode */ | 2337 | #define DNM 0x2 /* DeviceNet Mode */ |
| 2695 | #define nDNM 0x0 | ||
| 2696 | #define ABO 0x4 /* Auto Bus On */ | 2338 | #define ABO 0x4 /* Auto Bus On */ |
| 2697 | #define nABO 0x0 | ||
| 2698 | #define WBA 0x10 /* Wakeup On CAN Bus Activity */ | 2339 | #define WBA 0x10 /* Wakeup On CAN Bus Activity */ |
| 2699 | #define nWBA 0x0 | ||
| 2700 | #define SMR 0x20 /* Sleep Mode Request */ | 2340 | #define SMR 0x20 /* Sleep Mode Request */ |
| 2701 | #define nSMR 0x0 | ||
| 2702 | #define CSR 0x40 /* CAN Suspend Mode Request */ | 2341 | #define CSR 0x40 /* CAN Suspend Mode Request */ |
| 2703 | #define nCSR 0x0 | ||
| 2704 | #define CCR 0x80 /* CAN Configuration Mode Request */ | 2342 | #define CCR 0x80 /* CAN Configuration Mode Request */ |
| 2705 | #define nCCR 0x0 | ||
| 2706 | 2343 | ||
| 2707 | /* Bit masks for CAN0_STATUS */ | 2344 | /* Bit masks for CAN0_STATUS */ |
| 2708 | 2345 | ||
| 2709 | #define WT 0x1 /* CAN Transmit Warning Flag */ | 2346 | #define WT 0x1 /* CAN Transmit Warning Flag */ |
| 2710 | #define nWT 0x0 | ||
| 2711 | #define WR 0x2 /* CAN Receive Warning Flag */ | 2347 | #define WR 0x2 /* CAN Receive Warning Flag */ |
| 2712 | #define nWR 0x0 | ||
| 2713 | #define EP 0x4 /* CAN Error Passive Mode */ | 2348 | #define EP 0x4 /* CAN Error Passive Mode */ |
| 2714 | #define nEP 0x0 | ||
| 2715 | #define EBO 0x8 /* CAN Error Bus Off Mode */ | 2349 | #define EBO 0x8 /* CAN Error Bus Off Mode */ |
| 2716 | #define nEBO 0x0 | ||
| 2717 | #define CSA 0x40 /* CAN Suspend Mode Acknowledge */ | 2350 | #define CSA 0x40 /* CAN Suspend Mode Acknowledge */ |
| 2718 | #define nCSA 0x0 | ||
| 2719 | #define CCA 0x80 /* CAN Configuration Mode Acknowledge */ | 2351 | #define CCA 0x80 /* CAN Configuration Mode Acknowledge */ |
| 2720 | #define nCCA 0x0 | ||
| 2721 | #define MBPTR 0x1f00 /* Mailbox Pointer */ | 2352 | #define MBPTR 0x1f00 /* Mailbox Pointer */ |
| 2722 | #define TRM 0x4000 /* Transmit Mode Status */ | 2353 | #define TRM 0x4000 /* Transmit Mode Status */ |
| 2723 | #define nTRM 0x0 | ||
| 2724 | #define REC 0x8000 /* Receive Mode Status */ | 2354 | #define REC 0x8000 /* Receive Mode Status */ |
| 2725 | #define nREC 0x0 | ||
| 2726 | 2355 | ||
| 2727 | /* Bit masks for CAN0_DEBUG */ | 2356 | /* Bit masks for CAN0_DEBUG */ |
| 2728 | 2357 | ||
| 2729 | #define DEC 0x1 /* Disable Transmit/Receive Error Counters */ | 2358 | #define DEC 0x1 /* Disable Transmit/Receive Error Counters */ |
| 2730 | #define nDEC 0x0 | ||
| 2731 | #define DRI 0x2 /* Disable CANRX Input Pin */ | 2359 | #define DRI 0x2 /* Disable CANRX Input Pin */ |
| 2732 | #define nDRI 0x0 | ||
| 2733 | #define DTO 0x4 /* Disable CANTX Output Pin */ | 2360 | #define DTO 0x4 /* Disable CANTX Output Pin */ |
| 2734 | #define nDTO 0x0 | ||
| 2735 | #define DIL 0x8 /* Disable Internal Loop */ | 2361 | #define DIL 0x8 /* Disable Internal Loop */ |
| 2736 | #define nDIL 0x0 | ||
| 2737 | #define MAA 0x10 /* Mode Auto-Acknowledge */ | 2362 | #define MAA 0x10 /* Mode Auto-Acknowledge */ |
| 2738 | #define nMAA 0x0 | ||
| 2739 | #define MRB 0x20 /* Mode Read Back */ | 2363 | #define MRB 0x20 /* Mode Read Back */ |
| 2740 | #define nMRB 0x0 | ||
| 2741 | #define CDE 0x8000 /* CAN Debug Mode Enable */ | 2364 | #define CDE 0x8000 /* CAN Debug Mode Enable */ |
| 2742 | #define nCDE 0x0 | ||
| 2743 | 2365 | ||
| 2744 | /* Bit masks for CAN0_CLOCK */ | 2366 | /* Bit masks for CAN0_CLOCK */ |
| 2745 | 2367 | ||
| @@ -2749,111 +2371,69 @@ | |||
| 2749 | 2371 | ||
| 2750 | #define SJW 0x300 /* Synchronization Jump Width */ | 2372 | #define SJW 0x300 /* Synchronization Jump Width */ |
| 2751 | #define SAM 0x80 /* Sampling */ | 2373 | #define SAM 0x80 /* Sampling */ |
| 2752 | #define nSAM 0x0 | ||
| 2753 | #define TSEG2 0x70 /* Time Segment 2 */ | 2374 | #define TSEG2 0x70 /* Time Segment 2 */ |
| 2754 | #define TSEG1 0xf /* Time Segment 1 */ | 2375 | #define TSEG1 0xf /* Time Segment 1 */ |
| 2755 | 2376 | ||
| 2756 | /* Bit masks for CAN0_INTR */ | 2377 | /* Bit masks for CAN0_INTR */ |
| 2757 | 2378 | ||
| 2758 | #define CANRX 0x80 /* Serial Input From Transceiver */ | 2379 | #define CANRX 0x80 /* Serial Input From Transceiver */ |
| 2759 | #define nCANRX 0x0 | ||
| 2760 | #define CANTX 0x40 /* Serial Output To Transceiver */ | 2380 | #define CANTX 0x40 /* Serial Output To Transceiver */ |
| 2761 | #define nCANTX 0x0 | ||
| 2762 | #define SMACK 0x8 /* Sleep Mode Acknowledge */ | 2381 | #define SMACK 0x8 /* Sleep Mode Acknowledge */ |
| 2763 | #define nSMACK 0x0 | ||
| 2764 | #define GIRQ 0x4 /* Global Interrupt Request Status */ | 2382 | #define GIRQ 0x4 /* Global Interrupt Request Status */ |
| 2765 | #define nGIRQ 0x0 | ||
| 2766 | #define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ | 2383 | #define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ |
| 2767 | #define nMBTIRQ 0x0 | ||
| 2768 | #define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ | 2384 | #define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ |
| 2769 | #define nMBRIRQ 0x0 | ||
| 2770 | 2385 | ||
| 2771 | /* Bit masks for CAN0_GIM */ | 2386 | /* Bit masks for CAN0_GIM */ |
| 2772 | 2387 | ||
| 2773 | #define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ | 2388 | #define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ |
| 2774 | #define nEWTIM 0x0 | ||
| 2775 | #define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ | 2389 | #define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ |
| 2776 | #define nEWRIM 0x0 | ||
| 2777 | #define EPIM 0x4 /* Error Passive Interrupt Mask */ | 2390 | #define EPIM 0x4 /* Error Passive Interrupt Mask */ |
| 2778 | #define nEPIM 0x0 | ||
| 2779 | #define BOIM 0x8 /* Bus Off Interrupt Mask */ | 2391 | #define BOIM 0x8 /* Bus Off Interrupt Mask */ |
| 2780 | #define nBOIM 0x0 | ||
| 2781 | #define WUIM 0x10 /* Wakeup Interrupt Mask */ | 2392 | #define WUIM 0x10 /* Wakeup Interrupt Mask */ |
| 2782 | #define nWUIM 0x0 | ||
| 2783 | #define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ | 2393 | #define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ |
| 2784 | #define nUIAIM 0x0 | ||
| 2785 | #define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ | 2394 | #define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ |
| 2786 | #define nAAIM 0x0 | ||
| 2787 | #define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ | 2395 | #define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ |
| 2788 | #define nRMLIM 0x0 | ||
| 2789 | #define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ | 2396 | #define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ |
| 2790 | #define nUCEIM 0x0 | ||
| 2791 | #define ADIM 0x400 /* Access Denied Interrupt Mask */ | 2397 | #define ADIM 0x400 /* Access Denied Interrupt Mask */ |
| 2792 | #define nADIM 0x0 | ||
| 2793 | 2398 | ||
| 2794 | /* Bit masks for CAN0_GIS */ | 2399 | /* Bit masks for CAN0_GIS */ |
| 2795 | 2400 | ||
| 2796 | #define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ | 2401 | #define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ |
| 2797 | #define nEWTIS 0x0 | ||
| 2798 | #define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ | 2402 | #define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ |
| 2799 | #define nEWRIS 0x0 | ||
| 2800 | #define EPIS 0x4 /* Error Passive Interrupt Status */ | 2403 | #define EPIS 0x4 /* Error Passive Interrupt Status */ |
| 2801 | #define nEPIS 0x0 | ||
| 2802 | #define BOIS 0x8 /* Bus Off Interrupt Status */ | 2404 | #define BOIS 0x8 /* Bus Off Interrupt Status */ |
| 2803 | #define nBOIS 0x0 | ||
| 2804 | #define WUIS 0x10 /* Wakeup Interrupt Status */ | 2405 | #define WUIS 0x10 /* Wakeup Interrupt Status */ |
| 2805 | #define nWUIS 0x0 | ||
| 2806 | #define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ | 2406 | #define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ |
| 2807 | #define nUIAIS 0x0 | ||
| 2808 | #define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ | 2407 | #define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ |
| 2809 | #define nAAIS 0x0 | ||
| 2810 | #define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ | 2408 | #define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ |
| 2811 | #define nRMLIS 0x0 | ||
| 2812 | #define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ | 2409 | #define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ |
| 2813 | #define nUCEIS 0x0 | ||
| 2814 | #define ADIS 0x400 /* Access Denied Interrupt Status */ | 2410 | #define ADIS 0x400 /* Access Denied Interrupt Status */ |
| 2815 | #define nADIS 0x0 | ||
| 2816 | 2411 | ||
| 2817 | /* Bit masks for CAN0_GIF */ | 2412 | /* Bit masks for CAN0_GIF */ |
| 2818 | 2413 | ||
| 2819 | #define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ | 2414 | #define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ |
| 2820 | #define nEWTIF 0x0 | ||
| 2821 | #define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ | 2415 | #define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ |
| 2822 | #define nEWRIF 0x0 | ||
| 2823 | #define EPIF 0x4 /* Error Passive Interrupt Flag */ | 2416 | #define EPIF 0x4 /* Error Passive Interrupt Flag */ |
| 2824 | #define nEPIF 0x0 | ||
| 2825 | #define BOIF 0x8 /* Bus Off Interrupt Flag */ | 2417 | #define BOIF 0x8 /* Bus Off Interrupt Flag */ |
| 2826 | #define nBOIF 0x0 | ||
| 2827 | #define WUIF 0x10 /* Wakeup Interrupt Flag */ | 2418 | #define WUIF 0x10 /* Wakeup Interrupt Flag */ |
| 2828 | #define nWUIF 0x0 | ||
| 2829 | #define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ | 2419 | #define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ |
| 2830 | #define nUIAIF 0x0 | ||
| 2831 | #define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ | 2420 | #define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ |
| 2832 | #define nAAIF 0x0 | ||
| 2833 | #define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ | 2421 | #define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ |
| 2834 | #define nRMLIF 0x0 | ||
| 2835 | #define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ | 2422 | #define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ |
| 2836 | #define nUCEIF 0x0 | ||
| 2837 | #define ADIF 0x400 /* Access Denied Interrupt Flag */ | 2423 | #define ADIF 0x400 /* Access Denied Interrupt Flag */ |
| 2838 | #define nADIF 0x0 | ||
| 2839 | 2424 | ||
| 2840 | /* Bit masks for CAN0_MBTD */ | 2425 | /* Bit masks for CAN0_MBTD */ |
| 2841 | 2426 | ||
| 2842 | #define TDR 0x80 /* Temporary Disable Request */ | 2427 | #define TDR 0x80 /* Temporary Disable Request */ |
| 2843 | #define nTDR 0x0 | ||
| 2844 | #define TDA 0x40 /* Temporary Disable Acknowledge */ | 2428 | #define TDA 0x40 /* Temporary Disable Acknowledge */ |
| 2845 | #define nTDA 0x0 | ||
| 2846 | #define TDPTR 0x1f /* Temporary Disable Pointer */ | 2429 | #define TDPTR 0x1f /* Temporary Disable Pointer */ |
| 2847 | 2430 | ||
| 2848 | /* Bit masks for CAN0_UCCNF */ | 2431 | /* Bit masks for CAN0_UCCNF */ |
| 2849 | 2432 | ||
| 2850 | #define UCCNF 0xf /* Universal Counter Configuration */ | 2433 | #define UCCNF 0xf /* Universal Counter Configuration */ |
| 2851 | #define UCRC 0x20 /* Universal Counter Reload/Clear */ | 2434 | #define UCRC 0x20 /* Universal Counter Reload/Clear */ |
| 2852 | #define nUCRC 0x0 | ||
| 2853 | #define UCCT 0x40 /* Universal Counter CAN Trigger */ | 2435 | #define UCCT 0x40 /* Universal Counter CAN Trigger */ |
| 2854 | #define nUCCT 0x0 | ||
| 2855 | #define UCE 0x80 /* Universal Counter Enable */ | 2436 | #define UCE 0x80 /* Universal Counter Enable */ |
| 2856 | #define nUCE 0x0 | ||
| 2857 | 2437 | ||
| 2858 | /* Bit masks for CAN0_UCCNT */ | 2438 | /* Bit masks for CAN0_UCCNT */ |
| 2859 | 2439 | ||
| @@ -2871,17 +2451,11 @@ | |||
| 2871 | /* Bit masks for CAN0_ESR */ | 2451 | /* Bit masks for CAN0_ESR */ |
| 2872 | 2452 | ||
| 2873 | #define FER 0x80 /* Form Error */ | 2453 | #define FER 0x80 /* Form Error */ |
| 2874 | #define nFER 0x0 | ||
| 2875 | #define BEF 0x40 /* Bit Error Flag */ | 2454 | #define BEF 0x40 /* Bit Error Flag */ |
| 2876 | #define nBEF 0x0 | ||
| 2877 | #define SA0 0x20 /* Stuck At Dominant */ | 2455 | #define SA0 0x20 /* Stuck At Dominant */ |
| 2878 | #define nSA0 0x0 | ||
| 2879 | #define CRCE 0x10 /* CRC Error */ | 2456 | #define CRCE 0x10 /* CRC Error */ |
| 2880 | #define nCRCE 0x0 | ||
| 2881 | #define SER 0x8 /* Stuff Bit Error */ | 2457 | #define SER 0x8 /* Stuff Bit Error */ |
| 2882 | #define nSER 0x0 | ||
| 2883 | #define ACKE 0x4 /* Acknowledge Error */ | 2458 | #define ACKE 0x4 /* Acknowledge Error */ |
| 2884 | #define nACKE 0x0 | ||
| 2885 | 2459 | ||
| 2886 | /* Bit masks for CAN0_EWR */ | 2460 | /* Bit masks for CAN0_EWR */ |
| 2887 | 2461 | ||
| @@ -2891,11 +2465,8 @@ | |||
| 2891 | /* Bit masks for CAN0_AMxx_H */ | 2465 | /* Bit masks for CAN0_AMxx_H */ |
| 2892 | 2466 | ||
| 2893 | #define FDF 0x8000 /* Filter On Data Field */ | 2467 | #define FDF 0x8000 /* Filter On Data Field */ |
| 2894 | #define nFDF 0x0 | ||
| 2895 | #define FMD 0x4000 /* Full Mask Data */ | 2468 | #define FMD 0x4000 /* Full Mask Data */ |
| 2896 | #define nFMD 0x0 | ||
| 2897 | #define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ | 2469 | #define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ |
| 2898 | #define nAMIDE 0x0 | ||
| 2899 | #define BASEID 0x1ffc /* Base Identifier */ | 2470 | #define BASEID 0x1ffc /* Base Identifier */ |
| 2900 | #define EXTID_HI 0x3 /* Extended Identifier High Bits */ | 2471 | #define EXTID_HI 0x3 /* Extended Identifier High Bits */ |
| 2901 | 2472 | ||
| @@ -2907,11 +2478,8 @@ | |||
| 2907 | /* Bit masks for CAN0_MBxx_ID1 */ | 2478 | /* Bit masks for CAN0_MBxx_ID1 */ |
| 2908 | 2479 | ||
| 2909 | #define AME 0x8000 /* Acceptance Mask Enable */ | 2480 | #define AME 0x8000 /* Acceptance Mask Enable */ |
| 2910 | #define nAME 0x0 | ||
| 2911 | #define RTR 0x4000 /* Remote Transmission Request */ | 2481 | #define RTR 0x4000 /* Remote Transmission Request */ |
| 2912 | #define nRTR 0x0 | ||
| 2913 | #define IDE 0x2000 /* Identifier Extension */ | 2482 | #define IDE 0x2000 /* Identifier Extension */ |
| 2914 | #define nIDE 0x0 | ||
| 2915 | #define BASEID 0x1ffc /* Base Identifier */ | 2483 | #define BASEID 0x1ffc /* Base Identifier */ |
| 2916 | #define EXTID_HI 0x3 /* Extended Identifier High Bits */ | 2484 | #define EXTID_HI 0x3 /* Extended Identifier High Bits */ |
| 2917 | 2485 | ||
| @@ -2951,977 +2519,534 @@ | |||
| 2951 | /* Bit masks for CAN0_MC1 */ | 2519 | /* Bit masks for CAN0_MC1 */ |
| 2952 | 2520 | ||
| 2953 | #define MC0 0x1 /* Mailbox 0 Enable */ | 2521 | #define MC0 0x1 /* Mailbox 0 Enable */ |
| 2954 | #define nMC0 0x0 | ||
| 2955 | #define MC1 0x2 /* Mailbox 1 Enable */ | 2522 | #define MC1 0x2 /* Mailbox 1 Enable */ |
| 2956 | #define nMC1 0x0 | ||
| 2957 | #define MC2 0x4 /* Mailbox 2 Enable */ | 2523 | #define MC2 0x4 /* Mailbox 2 Enable */ |
| 2958 | #define nMC2 0x0 | ||
| 2959 | #define MC3 0x8 /* Mailbox 3 Enable */ | 2524 | #define MC3 0x8 /* Mailbox 3 Enable */ |
| 2960 | #define nMC3 0x0 | ||
| 2961 | #define MC4 0x10 /* Mailbox 4 Enable */ | 2525 | #define MC4 0x10 /* Mailbox 4 Enable */ |
| 2962 | #define nMC4 0x0 | ||
| 2963 | #define MC5 0x20 /* Mailbox 5 Enable */ | 2526 | #define MC5 0x20 /* Mailbox 5 Enable */ |
| 2964 | #define nMC5 0x0 | ||
| 2965 | #define MC6 0x40 /* Mailbox 6 Enable */ | 2527 | #define MC6 0x40 /* Mailbox 6 Enable */ |
| 2966 | #define nMC6 0x0 | ||
| 2967 | #define MC7 0x80 /* Mailbox 7 Enable */ | 2528 | #define MC7 0x80 /* Mailbox 7 Enable */ |
| 2968 | #define nMC7 0x0 | ||
| 2969 | #define MC8 0x100 /* Mailbox 8 Enable */ | 2529 | #define MC8 0x100 /* Mailbox 8 Enable */ |
| 2970 | #define nMC8 0x0 | ||
| 2971 | #define MC9 0x200 /* Mailbox 9 Enable */ | 2530 | #define MC9 0x200 /* Mailbox 9 Enable */ |
| 2972 | #define nMC9 0x0 | ||
| 2973 | #define MC10 0x400 /* Mailbox 10 Enable */ | 2531 | #define MC10 0x400 /* Mailbox 10 Enable */ |
| 2974 | #define nMC10 0x0 | ||
| 2975 | #define MC11 0x800 /* Mailbox 11 Enable */ | 2532 | #define MC11 0x800 /* Mailbox 11 Enable */ |
| 2976 | #define nMC11 0x0 | ||
| 2977 | #define MC12 0x1000 /* Mailbox 12 Enable */ | 2533 | #define MC12 0x1000 /* Mailbox 12 Enable */ |
| 2978 | #define nMC12 0x0 | ||
| 2979 | #define MC13 0x2000 /* Mailbox 13 Enable */ | 2534 | #define MC13 0x2000 /* Mailbox 13 Enable */ |
| 2980 | #define nMC13 0x0 | ||
| 2981 | #define MC14 0x4000 /* Mailbox 14 Enable */ | 2535 | #define MC14 0x4000 /* Mailbox 14 Enable */ |
| 2982 | #define nMC14 0x0 | ||
| 2983 | #define MC15 0x8000 /* Mailbox 15 Enable */ | 2536 | #define MC15 0x8000 /* Mailbox 15 Enable */ |
| 2984 | #define nMC15 0x0 | ||
| 2985 | 2537 | ||
| 2986 | /* Bit masks for CAN0_MC2 */ | 2538 | /* Bit masks for CAN0_MC2 */ |
| 2987 | 2539 | ||
| 2988 | #define MC16 0x1 /* Mailbox 16 Enable */ | 2540 | #define MC16 0x1 /* Mailbox 16 Enable */ |
| 2989 | #define nMC16 0x0 | ||
| 2990 | #define MC17 0x2 /* Mailbox 17 Enable */ | 2541 | #define MC17 0x2 /* Mailbox 17 Enable */ |
| 2991 | #define nMC17 0x0 | ||
| 2992 | #define MC18 0x4 /* Mailbox 18 Enable */ | 2542 | #define MC18 0x4 /* Mailbox 18 Enable */ |
| 2993 | #define nMC18 0x0 | ||
| 2994 | #define MC19 0x8 /* Mailbox 19 Enable */ | 2543 | #define MC19 0x8 /* Mailbox 19 Enable */ |
| 2995 | #define nMC19 0x0 | ||
| 2996 | #define MC20 0x10 /* Mailbox 20 Enable */ | 2544 | #define MC20 0x10 /* Mailbox 20 Enable */ |
| 2997 | #define nMC20 0x0 | ||
| 2998 | #define MC21 0x20 /* Mailbox 21 Enable */ | 2545 | #define MC21 0x20 /* Mailbox 21 Enable */ |
| 2999 | #define nMC21 0x0 | ||
| 3000 | #define MC22 0x40 /* Mailbox 22 Enable */ | 2546 | #define MC22 0x40 /* Mailbox 22 Enable */ |
| 3001 | #define nMC22 0x0 | ||
| 3002 | #define MC23 0x80 /* Mailbox 23 Enable */ | 2547 | #define MC23 0x80 /* Mailbox 23 Enable */ |
| 3003 | #define nMC23 0x0 | ||
| 3004 | #define MC24 0x100 /* Mailbox 24 Enable */ | 2548 | #define MC24 0x100 /* Mailbox 24 Enable */ |
| 3005 | #define nMC24 0x0 | ||
| 3006 | #define MC25 0x200 /* Mailbox 25 Enable */ | 2549 | #define MC25 0x200 /* Mailbox 25 Enable */ |
| 3007 | #define nMC25 0x0 | ||
| 3008 | #define MC26 0x400 /* Mailbox 26 Enable */ | 2550 | #define MC26 0x400 /* Mailbox 26 Enable */ |
| 3009 | #define nMC26 0x0 | ||
| 3010 | #define MC27 0x800 /* Mailbox 27 Enable */ | 2551 | #define MC27 0x800 /* Mailbox 27 Enable */ |
| 3011 | #define nMC27 0x0 | ||
| 3012 | #define MC28 0x1000 /* Mailbox 28 Enable */ | 2552 | #define MC28 0x1000 /* Mailbox 28 Enable */ |
| 3013 | #define nMC28 0x0 | ||
| 3014 | #define MC29 0x2000 /* Mailbox 29 Enable */ | 2553 | #define MC29 0x2000 /* Mailbox 29 Enable */ |
| 3015 | #define nMC29 0x0 | ||
| 3016 | #define MC30 0x4000 /* Mailbox 30 Enable */ | 2554 | #define MC30 0x4000 /* Mailbox 30 Enable */ |
| 3017 | #define nMC30 0x0 | ||
| 3018 | #define MC31 0x8000 /* Mailbox 31 Enable */ | 2555 | #define MC31 0x8000 /* Mailbox 31 Enable */ |
| 3019 | #define nMC31 0x0 | ||
| 3020 | 2556 | ||
| 3021 | /* Bit masks for CAN0_MD1 */ | 2557 | /* Bit masks for CAN0_MD1 */ |
| 3022 | 2558 | ||
| 3023 | #define MD0 0x1 /* Mailbox 0 Receive Enable */ | 2559 | #define MD0 0x1 /* Mailbox 0 Receive Enable */ |
| 3024 | #define nMD0 0x0 | ||
| 3025 | #define MD1 0x2 /* Mailbox 1 Receive Enable */ | 2560 | #define MD1 0x2 /* Mailbox 1 Receive Enable */ |
| 3026 | #define nMD1 0x0 | ||
| 3027 | #define MD2 0x4 /* Mailbox 2 Receive Enable */ | 2561 | #define MD2 0x4 /* Mailbox 2 Receive Enable */ |
| 3028 | #define nMD2 0x0 | ||
| 3029 | #define MD3 0x8 /* Mailbox 3 Receive Enable */ | 2562 | #define MD3 0x8 /* Mailbox 3 Receive Enable */ |
| 3030 | #define nMD3 0x0 | ||
| 3031 | #define MD4 0x10 /* Mailbox 4 Receive Enable */ | 2563 | #define MD4 0x10 /* Mailbox 4 Receive Enable */ |
| 3032 | #define nMD4 0x0 | ||
| 3033 | #define MD5 0x20 /* Mailbox 5 Receive Enable */ | 2564 | #define MD5 0x20 /* Mailbox 5 Receive Enable */ |
| 3034 | #define nMD5 0x0 | ||
| 3035 | #define MD6 0x40 /* Mailbox 6 Receive Enable */ | 2565 | #define MD6 0x40 /* Mailbox 6 Receive Enable */ |
| 3036 | #define nMD6 0x0 | ||
| 3037 | #define MD7 0x80 /* Mailbox 7 Receive Enable */ | 2566 | #define MD7 0x80 /* Mailbox 7 Receive Enable */ |
| 3038 | #define nMD7 0x0 | ||
| 3039 | #define MD8 0x100 /* Mailbox 8 Receive Enable */ | 2567 | #define MD8 0x100 /* Mailbox 8 Receive Enable */ |
| 3040 | #define nMD8 0x0 | ||
| 3041 | #define MD9 0x200 /* Mailbox 9 Receive Enable */ | 2568 | #define MD9 0x200 /* Mailbox 9 Receive Enable */ |
| 3042 | #define nMD9 0x0 | ||
| 3043 | #define MD10 0x400 /* Mailbox 10 Receive Enable */ | 2569 | #define MD10 0x400 /* Mailbox 10 Receive Enable */ |
| 3044 | #define nMD10 0x0 | ||
| 3045 | #define MD11 0x800 /* Mailbox 11 Receive Enable */ | 2570 | #define MD11 0x800 /* Mailbox 11 Receive Enable */ |
| 3046 | #define nMD11 0x0 | ||
| 3047 | #define MD12 0x1000 /* Mailbox 12 Receive Enable */ | 2571 | #define MD12 0x1000 /* Mailbox 12 Receive Enable */ |
| 3048 | #define nMD12 0x0 | ||
| 3049 | #define MD13 0x2000 /* Mailbox 13 Receive Enable */ | 2572 | #define MD13 0x2000 /* Mailbox 13 Receive Enable */ |
| 3050 | #define nMD13 0x0 | ||
| 3051 | #define MD14 0x4000 /* Mailbox 14 Receive Enable */ | 2573 | #define MD14 0x4000 /* Mailbox 14 Receive Enable */ |
| 3052 | #define nMD14 0x0 | ||
| 3053 | #define MD15 0x8000 /* Mailbox 15 Receive Enable */ | 2574 | #define MD15 0x8000 /* Mailbox 15 Receive Enable */ |
| 3054 | #define nMD15 0x0 | ||
| 3055 | 2575 | ||
| 3056 | /* Bit masks for CAN0_MD2 */ | 2576 | /* Bit masks for CAN0_MD2 */ |
| 3057 | 2577 | ||
| 3058 | #define MD16 0x1 /* Mailbox 16 Receive Enable */ | 2578 | #define MD16 0x1 /* Mailbox 16 Receive Enable */ |
| 3059 | #define nMD16 0x0 | ||
| 3060 | #define MD17 0x2 /* Mailbox 17 Receive Enable */ | 2579 | #define MD17 0x2 /* Mailbox 17 Receive Enable */ |
| 3061 | #define nMD17 0x0 | ||
| 3062 | #define MD18 0x4 /* Mailbox 18 Receive Enable */ | 2580 | #define MD18 0x4 /* Mailbox 18 Receive Enable */ |
| 3063 | #define nMD18 0x0 | ||
| 3064 | #define MD19 0x8 /* Mailbox 19 Receive Enable */ | 2581 | #define MD19 0x8 /* Mailbox 19 Receive Enable */ |
| 3065 | #define nMD19 0x0 | ||
| 3066 | #define MD20 0x10 /* Mailbox 20 Receive Enable */ | 2582 | #define MD20 0x10 /* Mailbox 20 Receive Enable */ |
| 3067 | #define nMD20 0x0 | ||
| 3068 | #define MD21 0x20 /* Mailbox 21 Receive Enable */ | 2583 | #define MD21 0x20 /* Mailbox 21 Receive Enable */ |
| 3069 | #define nMD21 0x0 | ||
| 3070 | #define MD22 0x40 /* Mailbox 22 Receive Enable */ | 2584 | #define MD22 0x40 /* Mailbox 22 Receive Enable */ |
| 3071 | #define nMD22 0x0 | ||
| 3072 | #define MD23 0x80 /* Mailbox 23 Receive Enable */ | 2585 | #define MD23 0x80 /* Mailbox 23 Receive Enable */ |
| 3073 | #define nMD23 0x0 | ||
| 3074 | #define MD24 0x100 /* Mailbox 24 Receive Enable */ | 2586 | #define MD24 0x100 /* Mailbox 24 Receive Enable */ |
| 3075 | #define nMD24 0x0 | ||
| 3076 | #define MD25 0x200 /* Mailbox 25 Receive Enable */ | 2587 | #define MD25 0x200 /* Mailbox 25 Receive Enable */ |
| 3077 | #define nMD25 0x0 | ||
| 3078 | #define MD26 0x400 /* Mailbox 26 Receive Enable */ | 2588 | #define MD26 0x400 /* Mailbox 26 Receive Enable */ |
| 3079 | #define nMD26 0x0 | ||
| 3080 | #define MD27 0x800 /* Mailbox 27 Receive Enable */ | 2589 | #define MD27 0x800 /* Mailbox 27 Receive Enable */ |
| 3081 | #define nMD27 0x0 | ||
| 3082 | #define MD28 0x1000 /* Mailbox 28 Receive Enable */ | 2590 | #define MD28 0x1000 /* Mailbox 28 Receive Enable */ |
| 3083 | #define nMD28 0x0 | ||
| 3084 | #define MD29 0x2000 /* Mailbox 29 Receive Enable */ | 2591 | #define MD29 0x2000 /* Mailbox 29 Receive Enable */ |
| 3085 | #define nMD29 0x0 | ||
| 3086 | #define MD30 0x4000 /* Mailbox 30 Receive Enable */ | 2592 | #define MD30 0x4000 /* Mailbox 30 Receive Enable */ |
| 3087 | #define nMD30 0x0 | ||
| 3088 | #define MD31 0x8000 /* Mailbox 31 Receive Enable */ | 2593 | #define MD31 0x8000 /* Mailbox 31 Receive Enable */ |
| 3089 | #define nMD31 0x0 | ||
| 3090 | 2594 | ||
| 3091 | /* Bit masks for CAN0_RMP1 */ | 2595 | /* Bit masks for CAN0_RMP1 */ |
| 3092 | 2596 | ||
| 3093 | #define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ | 2597 | #define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ |
| 3094 | #define nRMP0 0x0 | ||
| 3095 | #define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ | 2598 | #define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ |
| 3096 | #define nRMP1 0x0 | ||
| 3097 | #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ | 2599 | #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ |
| 3098 | #define nRMP2 0x0 | ||
| 3099 | #define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ | 2600 | #define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ |
| 3100 | #define nRMP3 0x0 | ||
| 3101 | #define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ | 2601 | #define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ |
| 3102 | #define nRMP4 0x0 | ||
| 3103 | #define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ | 2602 | #define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ |
| 3104 | #define nRMP5 0x0 | ||
| 3105 | #define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ | 2603 | #define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ |
| 3106 | #define nRMP6 0x0 | ||
| 3107 | #define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ | 2604 | #define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ |
| 3108 | #define nRMP7 0x0 | ||
| 3109 | #define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ | 2605 | #define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ |
| 3110 | #define nRMP8 0x0 | ||
| 3111 | #define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ | 2606 | #define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ |
| 3112 | #define nRMP9 0x0 | ||
| 3113 | #define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ | 2607 | #define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ |
| 3114 | #define nRMP10 0x0 | ||
| 3115 | #define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ | 2608 | #define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ |
| 3116 | #define nRMP11 0x0 | ||
| 3117 | #define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ | 2609 | #define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ |
| 3118 | #define nRMP12 0x0 | ||
| 3119 | #define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ | 2610 | #define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ |
| 3120 | #define nRMP13 0x0 | ||
| 3121 | #define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ | 2611 | #define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ |
| 3122 | #define nRMP14 0x0 | ||
| 3123 | #define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ | 2612 | #define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ |
| 3124 | #define nRMP15 0x0 | ||
| 3125 | 2613 | ||
| 3126 | /* Bit masks for CAN0_RMP2 */ | 2614 | /* Bit masks for CAN0_RMP2 */ |
| 3127 | 2615 | ||
| 3128 | #define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ | 2616 | #define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ |
| 3129 | #define nRMP16 0x0 | ||
| 3130 | #define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ | 2617 | #define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ |
| 3131 | #define nRMP17 0x0 | ||
| 3132 | #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ | 2618 | #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ |
| 3133 | #define nRMP18 0x0 | ||
| 3134 | #define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ | 2619 | #define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ |
| 3135 | #define nRMP19 0x0 | ||
| 3136 | #define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ | 2620 | #define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ |
| 3137 | #define nRMP20 0x0 | ||
| 3138 | #define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ | 2621 | #define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ |
| 3139 | #define nRMP21 0x0 | ||
| 3140 | #define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ | 2622 | #define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ |
| 3141 | #define nRMP22 0x0 | ||
| 3142 | #define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ | 2623 | #define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ |
| 3143 | #define nRMP23 0x0 | ||
| 3144 | #define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ | 2624 | #define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ |
| 3145 | #define nRMP24 0x0 | ||
| 3146 | #define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ | 2625 | #define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ |
| 3147 | #define nRMP25 0x0 | ||
| 3148 | #define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ | 2626 | #define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ |
| 3149 | #define nRMP26 0x0 | ||
| 3150 | #define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ | 2627 | #define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ |
| 3151 | #define nRMP27 0x0 | ||
| 3152 | #define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ | 2628 | #define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ |
| 3153 | #define nRMP28 0x0 | ||
| 3154 | #define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ | 2629 | #define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ |
| 3155 | #define nRMP29 0x0 | ||
| 3156 | #define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ | 2630 | #define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ |
| 3157 | #define nRMP30 0x0 | ||
| 3158 | #define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ | 2631 | #define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ |
| 3159 | #define nRMP31 0x0 | ||
| 3160 | 2632 | ||
| 3161 | /* Bit masks for CAN0_RML1 */ | 2633 | /* Bit masks for CAN0_RML1 */ |
| 3162 | 2634 | ||
| 3163 | #define RML0 0x1 /* Mailbox 0 Receive Message Lost */ | 2635 | #define RML0 0x1 /* Mailbox 0 Receive Message Lost */ |
| 3164 | #define nRML0 0x0 | ||
| 3165 | #define RML1 0x2 /* Mailbox 1 Receive Message Lost */ | 2636 | #define RML1 0x2 /* Mailbox 1 Receive Message Lost */ |
| 3166 | #define nRML1 0x0 | ||
| 3167 | #define RML2 0x4 /* Mailbox 2 Receive Message Lost */ | 2637 | #define RML2 0x4 /* Mailbox 2 Receive Message Lost */ |
| 3168 | #define nRML2 0x0 | ||
| 3169 | #define RML3 0x8 /* Mailbox 3 Receive Message Lost */ | 2638 | #define RML3 0x8 /* Mailbox 3 Receive Message Lost */ |
| 3170 | #define nRML3 0x0 | ||
| 3171 | #define RML4 0x10 /* Mailbox 4 Receive Message Lost */ | 2639 | #define RML4 0x10 /* Mailbox 4 Receive Message Lost */ |
| 3172 | #define nRML4 0x0 | ||
| 3173 | #define RML5 0x20 /* Mailbox 5 Receive Message Lost */ | 2640 | #define RML5 0x20 /* Mailbox 5 Receive Message Lost */ |
| 3174 | #define nRML5 0x0 | ||
| 3175 | #define RML6 0x40 /* Mailbox 6 Receive Message Lost */ | 2641 | #define RML6 0x40 /* Mailbox 6 Receive Message Lost */ |
| 3176 | #define nRML6 0x0 | ||
| 3177 | #define RML7 0x80 /* Mailbox 7 Receive Message Lost */ | 2642 | #define RML7 0x80 /* Mailbox 7 Receive Message Lost */ |
| 3178 | #define nRML7 0x0 | ||
| 3179 | #define RML8 0x100 /* Mailbox 8 Receive Message Lost */ | 2643 | #define RML8 0x100 /* Mailbox 8 Receive Message Lost */ |
| 3180 | #define nRML8 0x0 | ||
| 3181 | #define RML9 0x200 /* Mailbox 9 Receive Message Lost */ | 2644 | #define RML9 0x200 /* Mailbox 9 Receive Message Lost */ |
| 3182 | #define nRML9 0x0 | ||
| 3183 | #define RML10 0x400 /* Mailbox 10 Receive Message Lost */ | 2645 | #define RML10 0x400 /* Mailbox 10 Receive Message Lost */ |
| 3184 | #define nRML10 0x0 | ||
| 3185 | #define RML11 0x800 /* Mailbox 11 Receive Message Lost */ | 2646 | #define RML11 0x800 /* Mailbox 11 Receive Message Lost */ |
| 3186 | #define nRML11 0x0 | ||
| 3187 | #define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ | 2647 | #define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ |
| 3188 | #define nRML12 0x0 | ||
| 3189 | #define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ | 2648 | #define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ |
| 3190 | #define nRML13 0x0 | ||
| 3191 | #define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ | 2649 | #define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ |
| 3192 | #define nRML14 0x0 | ||
| 3193 | #define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ | 2650 | #define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ |
| 3194 | #define nRML15 0x0 | ||
| 3195 | 2651 | ||
| 3196 | /* Bit masks for CAN0_RML2 */ | 2652 | /* Bit masks for CAN0_RML2 */ |
| 3197 | 2653 | ||
| 3198 | #define RML16 0x1 /* Mailbox 16 Receive Message Lost */ | 2654 | #define RML16 0x1 /* Mailbox 16 Receive Message Lost */ |
| 3199 | #define nRML16 0x0 | ||
| 3200 | #define RML17 0x2 /* Mailbox 17 Receive Message Lost */ | 2655 | #define RML17 0x2 /* Mailbox 17 Receive Message Lost */ |
| 3201 | #define nRML17 0x0 | ||
| 3202 | #define RML18 0x4 /* Mailbox 18 Receive Message Lost */ | 2656 | #define RML18 0x4 /* Mailbox 18 Receive Message Lost */ |
| 3203 | #define nRML18 0x0 | ||
| 3204 | #define RML19 0x8 /* Mailbox 19 Receive Message Lost */ | 2657 | #define RML19 0x8 /* Mailbox 19 Receive Message Lost */ |
| 3205 | #define nRML19 0x0 | ||
| 3206 | #define RML20 0x10 /* Mailbox 20 Receive Message Lost */ | 2658 | #define RML20 0x10 /* Mailbox 20 Receive Message Lost */ |
| 3207 | #define nRML20 0x0 | ||
| 3208 | #define RML21 0x20 /* Mailbox 21 Receive Message Lost */ | 2659 | #define RML21 0x20 /* Mailbox 21 Receive Message Lost */ |
| 3209 | #define nRML21 0x0 | ||
| 3210 | #define RML22 0x40 /* Mailbox 22 Receive Message Lost */ | 2660 | #define RML22 0x40 /* Mailbox 22 Receive Message Lost */ |
| 3211 | #define nRML22 0x0 | ||
| 3212 | #define RML23 0x80 /* Mailbox 23 Receive Message Lost */ | 2661 | #define RML23 0x80 /* Mailbox 23 Receive Message Lost */ |
| 3213 | #define nRML23 0x0 | ||
| 3214 | #define RML24 0x100 /* Mailbox 24 Receive Message Lost */ | 2662 | #define RML24 0x100 /* Mailbox 24 Receive Message Lost */ |
| 3215 | #define nRML24 0x0 | ||
| 3216 | #define RML25 0x200 /* Mailbox 25 Receive Message Lost */ | 2663 | #define RML25 0x200 /* Mailbox 25 Receive Message Lost */ |
| 3217 | #define nRML25 0x0 | ||
| 3218 | #define RML26 0x400 /* Mailbox 26 Receive Message Lost */ | 2664 | #define RML26 0x400 /* Mailbox 26 Receive Message Lost */ |
| 3219 | #define nRML26 0x0 | ||
| 3220 | #define RML27 0x800 /* Mailbox 27 Receive Message Lost */ | 2665 | #define RML27 0x800 /* Mailbox 27 Receive Message Lost */ |
| 3221 | #define nRML27 0x0 | ||
| 3222 | #define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ | 2666 | #define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ |
| 3223 | #define nRML28 0x0 | ||
| 3224 | #define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ | 2667 | #define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ |
| 3225 | #define nRML29 0x0 | ||
| 3226 | #define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ | 2668 | #define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ |
| 3227 | #define nRML30 0x0 | ||
| 3228 | #define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ | 2669 | #define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ |
| 3229 | #define nRML31 0x0 | ||
| 3230 | 2670 | ||
| 3231 | /* Bit masks for CAN0_OPSS1 */ | 2671 | /* Bit masks for CAN0_OPSS1 */ |
| 3232 | 2672 | ||
| 3233 | #define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ | 2673 | #define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3234 | #define nOPSS0 0x0 | ||
| 3235 | #define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ | 2674 | #define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3236 | #define nOPSS1 0x0 | ||
| 3237 | #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ | 2675 | #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3238 | #define nOPSS2 0x0 | ||
| 3239 | #define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ | 2676 | #define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3240 | #define nOPSS3 0x0 | ||
| 3241 | #define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ | 2677 | #define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3242 | #define nOPSS4 0x0 | ||
| 3243 | #define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ | 2678 | #define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3244 | #define nOPSS5 0x0 | ||
| 3245 | #define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ | 2679 | #define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3246 | #define nOPSS6 0x0 | ||
| 3247 | #define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ | 2680 | #define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3248 | #define nOPSS7 0x0 | ||
| 3249 | #define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ | 2681 | #define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3250 | #define nOPSS8 0x0 | ||
| 3251 | #define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ | 2682 | #define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3252 | #define nOPSS9 0x0 | ||
| 3253 | #define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ | 2683 | #define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3254 | #define nOPSS10 0x0 | ||
| 3255 | #define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ | 2684 | #define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3256 | #define nOPSS11 0x0 | ||
| 3257 | #define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ | 2685 | #define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3258 | #define nOPSS12 0x0 | ||
| 3259 | #define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ | 2686 | #define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3260 | #define nOPSS13 0x0 | ||
| 3261 | #define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ | 2687 | #define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3262 | #define nOPSS14 0x0 | ||
| 3263 | #define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ | 2688 | #define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3264 | #define nOPSS15 0x0 | ||
| 3265 | 2689 | ||
| 3266 | /* Bit masks for CAN0_OPSS2 */ | 2690 | /* Bit masks for CAN0_OPSS2 */ |
| 3267 | 2691 | ||
| 3268 | #define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ | 2692 | #define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3269 | #define nOPSS16 0x0 | ||
| 3270 | #define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ | 2693 | #define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3271 | #define nOPSS17 0x0 | ||
| 3272 | #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ | 2694 | #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3273 | #define nOPSS18 0x0 | ||
| 3274 | #define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ | 2695 | #define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3275 | #define nOPSS19 0x0 | ||
| 3276 | #define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ | 2696 | #define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3277 | #define nOPSS20 0x0 | ||
| 3278 | #define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ | 2697 | #define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3279 | #define nOPSS21 0x0 | ||
| 3280 | #define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ | 2698 | #define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3281 | #define nOPSS22 0x0 | ||
| 3282 | #define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ | 2699 | #define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3283 | #define nOPSS23 0x0 | ||
| 3284 | #define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ | 2700 | #define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3285 | #define nOPSS24 0x0 | ||
| 3286 | #define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ | 2701 | #define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3287 | #define nOPSS25 0x0 | ||
| 3288 | #define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ | 2702 | #define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3289 | #define nOPSS26 0x0 | ||
| 3290 | #define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ | 2703 | #define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3291 | #define nOPSS27 0x0 | ||
| 3292 | #define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ | 2704 | #define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3293 | #define nOPSS28 0x0 | ||
| 3294 | #define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ | 2705 | #define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3295 | #define nOPSS29 0x0 | ||
| 3296 | #define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ | 2706 | #define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3297 | #define nOPSS30 0x0 | ||
| 3298 | #define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ | 2707 | #define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ |
| 3299 | #define nOPSS31 0x0 | ||
| 3300 | 2708 | ||
| 3301 | /* Bit masks for CAN0_TRS1 */ | 2709 | /* Bit masks for CAN0_TRS1 */ |
| 3302 | 2710 | ||
| 3303 | #define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ | 2711 | #define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ |
| 3304 | #define nTRS0 0x0 | ||
| 3305 | #define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ | 2712 | #define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ |
| 3306 | #define nTRS1 0x0 | ||
| 3307 | #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ | 2713 | #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ |
| 3308 | #define nTRS2 0x0 | ||
| 3309 | #define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ | 2714 | #define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ |
| 3310 | #define nTRS3 0x0 | ||
| 3311 | #define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ | 2715 | #define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ |
| 3312 | #define nTRS4 0x0 | ||
| 3313 | #define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ | 2716 | #define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ |
| 3314 | #define nTRS5 0x0 | ||
| 3315 | #define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ | 2717 | #define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ |
| 3316 | #define nTRS6 0x0 | ||
| 3317 | #define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ | 2718 | #define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ |
| 3318 | #define nTRS7 0x0 | ||
| 3319 | #define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ | 2719 | #define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ |
| 3320 | #define nTRS8 0x0 | ||
| 3321 | #define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ | 2720 | #define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ |
| 3322 | #define nTRS9 0x0 | ||
| 3323 | #define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ | 2721 | #define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ |
| 3324 | #define nTRS10 0x0 | ||
| 3325 | #define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ | 2722 | #define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ |
| 3326 | #define nTRS11 0x0 | ||
| 3327 | #define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ | 2723 | #define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ |
| 3328 | #define nTRS12 0x0 | ||
| 3329 | #define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ | 2724 | #define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ |
| 3330 | #define nTRS13 0x0 | ||
| 3331 | #define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ | 2725 | #define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ |
| 3332 | #define nTRS14 0x0 | ||
| 3333 | #define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ | 2726 | #define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ |
| 3334 | #define nTRS15 0x0 | ||
| 3335 | 2727 | ||
| 3336 | /* Bit masks for CAN0_TRS2 */ | 2728 | /* Bit masks for CAN0_TRS2 */ |
| 3337 | 2729 | ||
| 3338 | #define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ | 2730 | #define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ |
| 3339 | #define nTRS16 0x0 | ||
| 3340 | #define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ | 2731 | #define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ |
| 3341 | #define nTRS17 0x0 | ||
| 3342 | #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ | 2732 | #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ |
| 3343 | #define nTRS18 0x0 | ||
| 3344 | #define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ | 2733 | #define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ |
| 3345 | #define nTRS19 0x0 | ||
| 3346 | #define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ | 2734 | #define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ |
| 3347 | #define nTRS20 0x0 | ||
| 3348 | #define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ | 2735 | #define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ |
| 3349 | #define nTRS21 0x0 | ||
| 3350 | #define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ | 2736 | #define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ |
| 3351 | #define nTRS22 0x0 | ||
| 3352 | #define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ | 2737 | #define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ |
| 3353 | #define nTRS23 0x0 | ||
| 3354 | #define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ | 2738 | #define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ |
| 3355 | #define nTRS24 0x0 | ||
| 3356 | #define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ | 2739 | #define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ |
| 3357 | #define nTRS25 0x0 | ||
| 3358 | #define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ | 2740 | #define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ |
| 3359 | #define nTRS26 0x0 | ||
| 3360 | #define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ | 2741 | #define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ |
| 3361 | #define nTRS27 0x0 | ||
| 3362 | #define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ | 2742 | #define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ |
| 3363 | #define nTRS28 0x0 | ||
| 3364 | #define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ | 2743 | #define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ |
| 3365 | #define nTRS29 0x0 | ||
| 3366 | #define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ | 2744 | #define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ |
| 3367 | #define nTRS30 0x0 | ||
| 3368 | #define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ | 2745 | #define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ |
| 3369 | #define nTRS31 0x0 | ||
| 3370 | 2746 | ||
| 3371 | /* Bit masks for CAN0_TRR1 */ | 2747 | /* Bit masks for CAN0_TRR1 */ |
| 3372 | 2748 | ||
| 3373 | #define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ | 2749 | #define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ |
| 3374 | #define nTRR0 0x0 | ||
| 3375 | #define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ | 2750 | #define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ |
| 3376 | #define nTRR1 0x0 | ||
| 3377 | #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ | 2751 | #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ |
| 3378 | #define nTRR2 0x0 | ||
| 3379 | #define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ | 2752 | #define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ |
| 3380 | #define nTRR3 0x0 | ||
| 3381 | #define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ | 2753 | #define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ |
| 3382 | #define nTRR4 0x0 | ||
| 3383 | #define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ | 2754 | #define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ |
| 3384 | #define nTRR5 0x0 | ||
| 3385 | #define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ | 2755 | #define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ |
| 3386 | #define nTRR6 0x0 | ||
| 3387 | #define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ | 2756 | #define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ |
| 3388 | #define nTRR7 0x0 | ||
| 3389 | #define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ | 2757 | #define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ |
| 3390 | #define nTRR8 0x0 | ||
| 3391 | #define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ | 2758 | #define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ |
| 3392 | #define nTRR9 0x0 | ||
| 3393 | #define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ | 2759 | #define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ |
| 3394 | #define nTRR10 0x0 | ||
| 3395 | #define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ | 2760 | #define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ |
| 3396 | #define nTRR11 0x0 | ||
| 3397 | #define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ | 2761 | #define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ |
| 3398 | #define nTRR12 0x0 | ||
| 3399 | #define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ | 2762 | #define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ |
| 3400 | #define nTRR13 0x0 | ||
| 3401 | #define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ | 2763 | #define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ |
| 3402 | #define nTRR14 0x0 | ||
| 3403 | #define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ | 2764 | #define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ |
| 3404 | #define nTRR15 0x0 | ||
| 3405 | 2765 | ||
| 3406 | /* Bit masks for CAN0_TRR2 */ | 2766 | /* Bit masks for CAN0_TRR2 */ |
| 3407 | 2767 | ||
| 3408 | #define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ | 2768 | #define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ |
| 3409 | #define nTRR16 0x0 | ||
| 3410 | #define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ | 2769 | #define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ |
| 3411 | #define nTRR17 0x0 | ||
| 3412 | #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ | 2770 | #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ |
| 3413 | #define nTRR18 0x0 | ||
| 3414 | #define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ | 2771 | #define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ |
| 3415 | #define nTRR19 0x0 | ||
| 3416 | #define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ | 2772 | #define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ |
| 3417 | #define nTRR20 0x0 | ||
| 3418 | #define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ | 2773 | #define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ |
| 3419 | #define nTRR21 0x0 | ||
| 3420 | #define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ | 2774 | #define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ |
| 3421 | #define nTRR22 0x0 | ||
| 3422 | #define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ | 2775 | #define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ |
| 3423 | #define nTRR23 0x0 | ||
| 3424 | #define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ | 2776 | #define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ |
| 3425 | #define nTRR24 0x0 | ||
| 3426 | #define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ | 2777 | #define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ |
| 3427 | #define nTRR25 0x0 | ||
| 3428 | #define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ | 2778 | #define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ |
| 3429 | #define nTRR26 0x0 | ||
| 3430 | #define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ | 2779 | #define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ |
| 3431 | #define nTRR27 0x0 | ||
| 3432 | #define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ | 2780 | #define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ |
| 3433 | #define nTRR28 0x0 | ||
| 3434 | #define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ | 2781 | #define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ |
| 3435 | #define nTRR29 0x0 | ||
| 3436 | #define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ | 2782 | #define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ |
| 3437 | #define nTRR30 0x0 | ||
| 3438 | #define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ | 2783 | #define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ |
| 3439 | #define nTRR31 0x0 | ||
| 3440 | 2784 | ||
| 3441 | /* Bit masks for CAN0_AA1 */ | 2785 | /* Bit masks for CAN0_AA1 */ |
| 3442 | 2786 | ||
| 3443 | #define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ | 2787 | #define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ |
| 3444 | #define nAA0 0x0 | ||
| 3445 | #define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ | 2788 | #define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ |
| 3446 | #define nAA1 0x0 | ||
| 3447 | #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ | 2789 | #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ |
| 3448 | #define nAA2 0x0 | ||
| 3449 | #define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ | 2790 | #define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ |
| 3450 | #define nAA3 0x0 | ||
| 3451 | #define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ | 2791 | #define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ |
| 3452 | #define nAA4 0x0 | ||
| 3453 | #define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ | 2792 | #define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ |
| 3454 | #define nAA5 0x0 | ||
| 3455 | #define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ | 2793 | #define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ |
| 3456 | #define nAA6 0x0 | ||
| 3457 | #define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ | 2794 | #define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ |
| 3458 | #define nAA7 0x0 | ||
| 3459 | #define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ | 2795 | #define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ |
| 3460 | #define nAA8 0x0 | ||
| 3461 | #define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ | 2796 | #define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ |
| 3462 | #define nAA9 0x0 | ||
| 3463 | #define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ | 2797 | #define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ |
| 3464 | #define nAA10 0x0 | ||
| 3465 | #define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ | 2798 | #define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ |
| 3466 | #define nAA11 0x0 | ||
| 3467 | #define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ | 2799 | #define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ |
| 3468 | #define nAA12 0x0 | ||
| 3469 | #define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ | 2800 | #define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ |
| 3470 | #define nAA13 0x0 | ||
| 3471 | #define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ | 2801 | #define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ |
| 3472 | #define nAA14 0x0 | ||
| 3473 | #define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ | 2802 | #define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ |
| 3474 | #define nAA15 0x0 | ||
| 3475 | 2803 | ||
| 3476 | /* Bit masks for CAN0_AA2 */ | 2804 | /* Bit masks for CAN0_AA2 */ |
| 3477 | 2805 | ||
| 3478 | #define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ | 2806 | #define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ |
| 3479 | #define nAA16 0x0 | ||
| 3480 | #define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ | 2807 | #define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ |
| 3481 | #define nAA17 0x0 | ||
| 3482 | #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ | 2808 | #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ |
| 3483 | #define nAA18 0x0 | ||
| 3484 | #define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ | 2809 | #define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ |
| 3485 | #define nAA19 0x0 | ||
| 3486 | #define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ | 2810 | #define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ |
| 3487 | #define nAA20 0x0 | ||
| 3488 | #define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ | 2811 | #define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ |
| 3489 | #define nAA21 0x0 | ||
| 3490 | #define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ | 2812 | #define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ |
| 3491 | #define nAA22 0x0 | ||
| 3492 | #define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ | 2813 | #define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ |
| 3493 | #define nAA23 0x0 | ||
| 3494 | #define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ | 2814 | #define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ |
| 3495 | #define nAA24 0x0 | ||
| 3496 | #define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ | 2815 | #define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ |
| 3497 | #define nAA25 0x0 | ||
| 3498 | #define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ | 2816 | #define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ |
| 3499 | #define nAA26 0x0 | ||
| 3500 | #define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ | 2817 | #define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ |
| 3501 | #define nAA27 0x0 | ||
| 3502 | #define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ | 2818 | #define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ |
| 3503 | #define nAA28 0x0 | ||
| 3504 | #define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ | 2819 | #define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ |
| 3505 | #define nAA29 0x0 | ||
| 3506 | #define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ | 2820 | #define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ |
| 3507 | #define nAA30 0x0 | ||
| 3508 | #define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ | 2821 | #define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ |
| 3509 | #define nAA31 0x0 | ||
| 3510 | 2822 | ||
| 3511 | /* Bit masks for CAN0_TA1 */ | 2823 | /* Bit masks for CAN0_TA1 */ |
| 3512 | 2824 | ||
| 3513 | #define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ | 2825 | #define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ |
| 3514 | #define nTA0 0x0 | ||
| 3515 | #define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ | 2826 | #define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ |
| 3516 | #define nTA1 0x0 | ||
| 3517 | #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ | 2827 | #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ |
| 3518 | #define nTA2 0x0 | ||
| 3519 | #define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ | 2828 | #define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ |
| 3520 | #define nTA3 0x0 | ||
| 3521 | #define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ | 2829 | #define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ |
| 3522 | #define nTA4 0x0 | ||
| 3523 | #define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ | 2830 | #define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ |
| 3524 | #define nTA5 0x0 | ||
| 3525 | #define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ | 2831 | #define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ |
| 3526 | #define nTA6 0x0 | ||
| 3527 | #define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ | 2832 | #define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ |
| 3528 | #define nTA7 0x0 | ||
| 3529 | #define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ | 2833 | #define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ |
| 3530 | #define nTA8 0x0 | ||
| 3531 | #define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ | 2834 | #define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ |
| 3532 | #define nTA9 0x0 | ||
| 3533 | #define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ | 2835 | #define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ |
| 3534 | #define nTA10 0x0 | ||
| 3535 | #define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ | 2836 | #define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ |
| 3536 | #define nTA11 0x0 | ||
| 3537 | #define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ | 2837 | #define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ |
| 3538 | #define nTA12 0x0 | ||
| 3539 | #define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ | 2838 | #define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ |
| 3540 | #define nTA13 0x0 | ||
| 3541 | #define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ | 2839 | #define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ |
| 3542 | #define nTA14 0x0 | ||
| 3543 | #define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ | 2840 | #define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ |
| 3544 | #define nTA15 0x0 | ||
| 3545 | 2841 | ||
| 3546 | /* Bit masks for CAN0_TA2 */ | 2842 | /* Bit masks for CAN0_TA2 */ |
| 3547 | 2843 | ||
| 3548 | #define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ | 2844 | #define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ |
| 3549 | #define nTA16 0x0 | ||
| 3550 | #define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ | 2845 | #define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ |
| 3551 | #define nTA17 0x0 | ||
| 3552 | #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ | 2846 | #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ |
| 3553 | #define nTA18 0x0 | ||
| 3554 | #define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ | 2847 | #define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ |
| 3555 | #define nTA19 0x0 | ||
| 3556 | #define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ | 2848 | #define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ |
| 3557 | #define nTA20 0x0 | ||
| 3558 | #define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ | 2849 | #define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ |
| 3559 | #define nTA21 0x0 | ||
| 3560 | #define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ | 2850 | #define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ |
| 3561 | #define nTA22 0x0 | ||
| 3562 | #define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ | 2851 | #define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ |
| 3563 | #define nTA23 0x0 | ||
| 3564 | #define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ | 2852 | #define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ |
| 3565 | #define nTA24 0x0 | ||
| 3566 | #define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ | 2853 | #define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ |
| 3567 | #define nTA25 0x0 | ||
| 3568 | #define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ | 2854 | #define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ |
| 3569 | #define nTA26 0x0 | ||
| 3570 | #define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ | 2855 | #define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ |
| 3571 | #define nTA27 0x0 | ||
| 3572 | #define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ | 2856 | #define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ |
| 3573 | #define nTA28 0x0 | ||
| 3574 | #define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ | 2857 | #define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ |
| 3575 | #define nTA29 0x0 | ||
| 3576 | #define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ | 2858 | #define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ |
| 3577 | #define nTA30 0x0 | ||
| 3578 | #define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ | 2859 | #define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ |
| 3579 | #define nTA31 0x0 | ||
| 3580 | 2860 | ||
| 3581 | /* Bit masks for CAN0_RFH1 */ | 2861 | /* Bit masks for CAN0_RFH1 */ |
| 3582 | 2862 | ||
| 3583 | #define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ | 2863 | #define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ |
| 3584 | #define nRFH0 0x0 | ||
| 3585 | #define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ | 2864 | #define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ |
| 3586 | #define nRFH1 0x0 | ||
| 3587 | #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ | 2865 | #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ |
| 3588 | #define nRFH2 0x0 | ||
| 3589 | #define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ | 2866 | #define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ |
| 3590 | #define nRFH3 0x0 | ||
| 3591 | #define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ | 2867 | #define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ |
| 3592 | #define nRFH4 0x0 | ||
| 3593 | #define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ | 2868 | #define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ |
| 3594 | #define nRFH5 0x0 | ||
| 3595 | #define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ | 2869 | #define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ |
| 3596 | #define nRFH6 0x0 | ||
| 3597 | #define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ | 2870 | #define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ |
| 3598 | #define nRFH7 0x0 | ||
| 3599 | #define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ | 2871 | #define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ |
| 3600 | #define nRFH8 0x0 | ||
| 3601 | #define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ | 2872 | #define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ |
| 3602 | #define nRFH9 0x0 | ||
| 3603 | #define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ | 2873 | #define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ |
| 3604 | #define nRFH10 0x0 | ||
| 3605 | #define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ | 2874 | #define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ |
| 3606 | #define nRFH11 0x0 | ||
| 3607 | #define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ | 2875 | #define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ |
| 3608 | #define nRFH12 0x0 | ||
| 3609 | #define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ | 2876 | #define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ |
| 3610 | #define nRFH13 0x0 | ||
| 3611 | #define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ | 2877 | #define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ |
| 3612 | #define nRFH14 0x0 | ||
| 3613 | #define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ | 2878 | #define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ |
| 3614 | #define nRFH15 0x0 | ||
| 3615 | 2879 | ||
| 3616 | /* Bit masks for CAN0_RFH2 */ | 2880 | /* Bit masks for CAN0_RFH2 */ |
| 3617 | 2881 | ||
| 3618 | #define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ | 2882 | #define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ |
| 3619 | #define nRFH16 0x0 | ||
| 3620 | #define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ | 2883 | #define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ |
| 3621 | #define nRFH17 0x0 | ||
| 3622 | #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ | 2884 | #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ |
| 3623 | #define nRFH18 0x0 | ||
| 3624 | #define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ | 2885 | #define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ |
| 3625 | #define nRFH19 0x0 | ||
| 3626 | #define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ | 2886 | #define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ |
| 3627 | #define nRFH20 0x0 | ||
| 3628 | #define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ | 2887 | #define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ |
| 3629 | #define nRFH21 0x0 | ||
| 3630 | #define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ | 2888 | #define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ |
| 3631 | #define nRFH22 0x0 | ||
| 3632 | #define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ | 2889 | #define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ |
| 3633 | #define nRFH23 0x0 | ||
| 3634 | #define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ | 2890 | #define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ |
| 3635 | #define nRFH24 0x0 | ||
| 3636 | #define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ | 2891 | #define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ |
| 3637 | #define nRFH25 0x0 | ||
| 3638 | #define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ | 2892 | #define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ |
| 3639 | #define nRFH26 0x0 | ||
| 3640 | #define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ | 2893 | #define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ |
| 3641 | #define nRFH27 0x0 | ||
| 3642 | #define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ | 2894 | #define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ |
| 3643 | #define nRFH28 0x0 | ||
| 3644 | #define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ | 2895 | #define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ |
| 3645 | #define nRFH29 0x0 | ||
| 3646 | #define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ | 2896 | #define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ |
| 3647 | #define nRFH30 0x0 | ||
| 3648 | #define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ | 2897 | #define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ |
| 3649 | #define nRFH31 0x0 | ||
| 3650 | 2898 | ||
| 3651 | /* Bit masks for CAN0_MBIM1 */ | 2899 | /* Bit masks for CAN0_MBIM1 */ |
| 3652 | 2900 | ||
| 3653 | #define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ | 2901 | #define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ |
| 3654 | #define nMBIM0 0x0 | ||
| 3655 | #define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ | 2902 | #define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ |
| 3656 | #define nMBIM1 0x0 | ||
| 3657 | #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ | 2903 | #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ |
| 3658 | #define nMBIM2 0x0 | ||
| 3659 | #define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ | 2904 | #define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ |
| 3660 | #define nMBIM3 0x0 | ||
| 3661 | #define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ | 2905 | #define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ |
| 3662 | #define nMBIM4 0x0 | ||
| 3663 | #define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ | 2906 | #define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ |
| 3664 | #define nMBIM5 0x0 | ||
| 3665 | #define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ | 2907 | #define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ |
| 3666 | #define nMBIM6 0x0 | ||
| 3667 | #define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ | 2908 | #define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ |
| 3668 | #define nMBIM7 0x0 | ||
| 3669 | #define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ | 2909 | #define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ |
| 3670 | #define nMBIM8 0x0 | ||
| 3671 | #define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ | 2910 | #define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ |
| 3672 | #define nMBIM9 0x0 | ||
| 3673 | #define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ | 2911 | #define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ |
| 3674 | #define nMBIM10 0x0 | ||
| 3675 | #define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ | 2912 | #define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ |
| 3676 | #define nMBIM11 0x0 | ||
| 3677 | #define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ | 2913 | #define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ |
| 3678 | #define nMBIM12 0x0 | ||
| 3679 | #define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ | 2914 | #define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ |
| 3680 | #define nMBIM13 0x0 | ||
| 3681 | #define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ | 2915 | #define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ |
| 3682 | #define nMBIM14 0x0 | ||
| 3683 | #define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ | 2916 | #define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ |
| 3684 | #define nMBIM15 0x0 | ||
| 3685 | 2917 | ||
| 3686 | /* Bit masks for CAN0_MBIM2 */ | 2918 | /* Bit masks for CAN0_MBIM2 */ |
| 3687 | 2919 | ||
| 3688 | #define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ | 2920 | #define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ |
| 3689 | #define nMBIM16 0x0 | ||
| 3690 | #define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ | 2921 | #define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ |
| 3691 | #define nMBIM17 0x0 | ||
| 3692 | #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ | 2922 | #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ |
| 3693 | #define nMBIM18 0x0 | ||
| 3694 | #define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ | 2923 | #define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ |
| 3695 | #define nMBIM19 0x0 | ||
| 3696 | #define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ | 2924 | #define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ |
| 3697 | #define nMBIM20 0x0 | ||
| 3698 | #define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ | 2925 | #define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ |
| 3699 | #define nMBIM21 0x0 | ||
| 3700 | #define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ | 2926 | #define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ |
| 3701 | #define nMBIM22 0x0 | ||
| 3702 | #define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ | 2927 | #define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ |
| 3703 | #define nMBIM23 0x0 | ||
| 3704 | #define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ | 2928 | #define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ |
| 3705 | #define nMBIM24 0x0 | ||
| 3706 | #define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ | 2929 | #define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ |
| 3707 | #define nMBIM25 0x0 | ||
| 3708 | #define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ | 2930 | #define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ |
| 3709 | #define nMBIM26 0x0 | ||
| 3710 | #define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ | 2931 | #define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ |
| 3711 | #define nMBIM27 0x0 | ||
| 3712 | #define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ | 2932 | #define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ |
| 3713 | #define nMBIM28 0x0 | ||
| 3714 | #define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ | 2933 | #define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ |
| 3715 | #define nMBIM29 0x0 | ||
| 3716 | #define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ | 2934 | #define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ |
| 3717 | #define nMBIM30 0x0 | ||
| 3718 | #define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ | 2935 | #define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ |
| 3719 | #define nMBIM31 0x0 | ||
| 3720 | 2936 | ||
| 3721 | /* Bit masks for CAN0_MBTIF1 */ | 2937 | /* Bit masks for CAN0_MBTIF1 */ |
| 3722 | 2938 | ||
| 3723 | #define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ | 2939 | #define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ |
| 3724 | #define nMBTIF0 0x0 | ||
| 3725 | #define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ | 2940 | #define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ |
| 3726 | #define nMBTIF1 0x0 | ||
| 3727 | #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ | 2941 | #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ |
| 3728 | #define nMBTIF2 0x0 | ||
| 3729 | #define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ | 2942 | #define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ |
| 3730 | #define nMBTIF3 0x0 | ||
| 3731 | #define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ | 2943 | #define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ |
| 3732 | #define nMBTIF4 0x0 | ||
| 3733 | #define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ | 2944 | #define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ |
| 3734 | #define nMBTIF5 0x0 | ||
| 3735 | #define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ | 2945 | #define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ |
| 3736 | #define nMBTIF6 0x0 | ||
| 3737 | #define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ | 2946 | #define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ |
| 3738 | #define nMBTIF7 0x0 | ||
| 3739 | #define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ | 2947 | #define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ |
| 3740 | #define nMBTIF8 0x0 | ||
| 3741 | #define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ | 2948 | #define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ |
| 3742 | #define nMBTIF9 0x0 | ||
| 3743 | #define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ | 2949 | #define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ |
| 3744 | #define nMBTIF10 0x0 | ||
| 3745 | #define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ | 2950 | #define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ |
| 3746 | #define nMBTIF11 0x0 | ||
| 3747 | #define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ | 2951 | #define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ |
| 3748 | #define nMBTIF12 0x0 | ||
| 3749 | #define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ | 2952 | #define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ |
| 3750 | #define nMBTIF13 0x0 | ||
| 3751 | #define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ | 2953 | #define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ |
| 3752 | #define nMBTIF14 0x0 | ||
| 3753 | #define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ | 2954 | #define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ |
| 3754 | #define nMBTIF15 0x0 | ||
| 3755 | 2955 | ||
| 3756 | /* Bit masks for CAN0_MBTIF2 */ | 2956 | /* Bit masks for CAN0_MBTIF2 */ |
| 3757 | 2957 | ||
| 3758 | #define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ | 2958 | #define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ |
| 3759 | #define nMBTIF16 0x0 | ||
| 3760 | #define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ | 2959 | #define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ |
| 3761 | #define nMBTIF17 0x0 | ||
| 3762 | #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ | 2960 | #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ |
| 3763 | #define nMBTIF18 0x0 | ||
| 3764 | #define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ | 2961 | #define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ |
| 3765 | #define nMBTIF19 0x0 | ||
| 3766 | #define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ | 2962 | #define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ |
| 3767 | #define nMBTIF20 0x0 | ||
| 3768 | #define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ | 2963 | #define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ |
| 3769 | #define nMBTIF21 0x0 | ||
| 3770 | #define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ | 2964 | #define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ |
| 3771 | #define nMBTIF22 0x0 | ||
| 3772 | #define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ | 2965 | #define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ |
| 3773 | #define nMBTIF23 0x0 | ||
| 3774 | #define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ | 2966 | #define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ |
| 3775 | #define nMBTIF24 0x0 | ||
| 3776 | #define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ | 2967 | #define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ |
| 3777 | #define nMBTIF25 0x0 | ||
| 3778 | #define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ | 2968 | #define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ |
| 3779 | #define nMBTIF26 0x0 | ||
| 3780 | #define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ | 2969 | #define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ |
| 3781 | #define nMBTIF27 0x0 | ||
| 3782 | #define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ | 2970 | #define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ |
| 3783 | #define nMBTIF28 0x0 | ||
| 3784 | #define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ | 2971 | #define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ |
| 3785 | #define nMBTIF29 0x0 | ||
| 3786 | #define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ | 2972 | #define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ |
| 3787 | #define nMBTIF30 0x0 | ||
| 3788 | #define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ | 2973 | #define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ |
| 3789 | #define nMBTIF31 0x0 | ||
| 3790 | 2974 | ||
| 3791 | /* Bit masks for CAN0_MBRIF1 */ | 2975 | /* Bit masks for CAN0_MBRIF1 */ |
| 3792 | 2976 | ||
| 3793 | #define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ | 2977 | #define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ |
| 3794 | #define nMBRIF0 0x0 | ||
| 3795 | #define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ | 2978 | #define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ |
| 3796 | #define nMBRIF1 0x0 | ||
| 3797 | #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ | 2979 | #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ |
| 3798 | #define nMBRIF2 0x0 | ||
| 3799 | #define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ | 2980 | #define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ |
| 3800 | #define nMBRIF3 0x0 | ||
| 3801 | #define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ | 2981 | #define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ |
| 3802 | #define nMBRIF4 0x0 | ||
| 3803 | #define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ | 2982 | #define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ |
| 3804 | #define nMBRIF5 0x0 | ||
| 3805 | #define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ | 2983 | #define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ |
| 3806 | #define nMBRIF6 0x0 | ||
| 3807 | #define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ | 2984 | #define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ |
| 3808 | #define nMBRIF7 0x0 | ||
| 3809 | #define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ | 2985 | #define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ |
| 3810 | #define nMBRIF8 0x0 | ||
| 3811 | #define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ | 2986 | #define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ |
| 3812 | #define nMBRIF9 0x0 | ||
| 3813 | #define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ | 2987 | #define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ |
| 3814 | #define nMBRIF10 0x0 | ||
| 3815 | #define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ | 2988 | #define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ |
| 3816 | #define nMBRIF11 0x0 | ||
| 3817 | #define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ | 2989 | #define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ |
| 3818 | #define nMBRIF12 0x0 | ||
| 3819 | #define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ | 2990 | #define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ |
| 3820 | #define nMBRIF13 0x0 | ||
| 3821 | #define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ | 2991 | #define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ |
| 3822 | #define nMBRIF14 0x0 | ||
| 3823 | #define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ | 2992 | #define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ |
| 3824 | #define nMBRIF15 0x0 | ||
| 3825 | 2993 | ||
| 3826 | /* Bit masks for CAN0_MBRIF2 */ | 2994 | /* Bit masks for CAN0_MBRIF2 */ |
| 3827 | 2995 | ||
| 3828 | #define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ | 2996 | #define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ |
| 3829 | #define nMBRIF16 0x0 | ||
| 3830 | #define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ | 2997 | #define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ |
| 3831 | #define nMBRIF17 0x0 | ||
| 3832 | #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ | 2998 | #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ |
| 3833 | #define nMBRIF18 0x0 | ||
| 3834 | #define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ | 2999 | #define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ |
| 3835 | #define nMBRIF19 0x0 | ||
| 3836 | #define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ | 3000 | #define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ |
| 3837 | #define nMBRIF20 0x0 | ||
| 3838 | #define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ | 3001 | #define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ |
| 3839 | #define nMBRIF21 0x0 | ||
| 3840 | #define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ | 3002 | #define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ |
| 3841 | #define nMBRIF22 0x0 | ||
| 3842 | #define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ | 3003 | #define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ |
| 3843 | #define nMBRIF23 0x0 | ||
| 3844 | #define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ | 3004 | #define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ |
| 3845 | #define nMBRIF24 0x0 | ||
| 3846 | #define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ | 3005 | #define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ |
| 3847 | #define nMBRIF25 0x0 | ||
| 3848 | #define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ | 3006 | #define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ |
| 3849 | #define nMBRIF26 0x0 | ||
| 3850 | #define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ | 3007 | #define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ |
| 3851 | #define nMBRIF27 0x0 | ||
| 3852 | #define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ | 3008 | #define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ |
| 3853 | #define nMBRIF28 0x0 | ||
| 3854 | #define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ | 3009 | #define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ |
| 3855 | #define nMBRIF29 0x0 | ||
| 3856 | #define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ | 3010 | #define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ |
| 3857 | #define nMBRIF30 0x0 | ||
| 3858 | #define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ | 3011 | #define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ |
| 3859 | #define nMBRIF31 0x0 | ||
| 3860 | 3012 | ||
| 3861 | /* Bit masks for EPPIx_STATUS */ | 3013 | /* Bit masks for EPPIx_STATUS */ |
| 3862 | 3014 | ||
| 3863 | #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ | 3015 | #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ |
| 3864 | #define nCFIFO_ERR 0x0 | ||
| 3865 | #define YFIFO_ERR 0x2 /* Luma FIFO Error */ | 3016 | #define YFIFO_ERR 0x2 /* Luma FIFO Error */ |
| 3866 | #define nYFIFO_ERR 0x0 | ||
| 3867 | #define LTERR_OVR 0x4 /* Line Track Overflow */ | 3017 | #define LTERR_OVR 0x4 /* Line Track Overflow */ |
| 3868 | #define nLTERR_OVR 0x0 | ||
| 3869 | #define LTERR_UNDR 0x8 /* Line Track Underflow */ | 3018 | #define LTERR_UNDR 0x8 /* Line Track Underflow */ |
| 3870 | #define nLTERR_UNDR 0x0 | ||
| 3871 | #define FTERR_OVR 0x10 /* Frame Track Overflow */ | 3019 | #define FTERR_OVR 0x10 /* Frame Track Overflow */ |
| 3872 | #define nFTERR_OVR 0x0 | ||
| 3873 | #define FTERR_UNDR 0x20 /* Frame Track Underflow */ | 3020 | #define FTERR_UNDR 0x20 /* Frame Track Underflow */ |
| 3874 | #define nFTERR_UNDR 0x0 | ||
| 3875 | #define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ | 3021 | #define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ |
| 3876 | #define nERR_NCOR 0x0 | ||
| 3877 | #define DMA1URQ 0x80 /* DMA1 Urgent Request */ | 3022 | #define DMA1URQ 0x80 /* DMA1 Urgent Request */ |
| 3878 | #define nDMA1URQ 0x0 | ||
| 3879 | #define DMA0URQ 0x100 /* DMA0 Urgent Request */ | 3023 | #define DMA0URQ 0x100 /* DMA0 Urgent Request */ |
| 3880 | #define nDMA0URQ 0x0 | ||
| 3881 | #define ERR_DET 0x4000 /* Preamble Error Detected */ | 3024 | #define ERR_DET 0x4000 /* Preamble Error Detected */ |
| 3882 | #define nERR_DET 0x0 | ||
| 3883 | #define FLD 0x8000 /* Field */ | 3025 | #define FLD 0x8000 /* Field */ |
| 3884 | #define nFLD 0x0 | ||
| 3885 | 3026 | ||
| 3886 | /* Bit masks for EPPIx_CONTROL */ | 3027 | /* Bit masks for EPPIx_CONTROL */ |
| 3887 | 3028 | ||
| 3888 | #define EPPI_EN 0x1 /* Enable */ | 3029 | #define EPPI_EN 0x1 /* Enable */ |
| 3889 | #define nEPPI_EN 0x0 | ||
| 3890 | #define EPPI_DIR 0x2 /* Direction */ | 3030 | #define EPPI_DIR 0x2 /* Direction */ |
| 3891 | #define nEPPI_DIR 0x0 | ||
| 3892 | #define XFR_TYPE 0xc /* Operating Mode */ | 3031 | #define XFR_TYPE 0xc /* Operating Mode */ |
| 3893 | #define FS_CFG 0x30 /* Frame Sync Configuration */ | 3032 | #define FS_CFG 0x30 /* Frame Sync Configuration */ |
| 3894 | #define FLD_SEL 0x40 /* Field Select/Trigger */ | 3033 | #define FLD_SEL 0x40 /* Field Select/Trigger */ |
| 3895 | #define nFLD_SEL 0x0 | ||
| 3896 | #define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ | 3034 | #define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ |
| 3897 | #define nITU_TYPE 0x0 | ||
| 3898 | #define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ | 3035 | #define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ |
| 3899 | #define nBLANKGEN 0x0 | ||
| 3900 | #define ICLKGEN 0x200 /* Internal Clock Generation */ | 3036 | #define ICLKGEN 0x200 /* Internal Clock Generation */ |
| 3901 | #define nICLKGEN 0x0 | ||
| 3902 | #define IFSGEN 0x400 /* Internal Frame Sync Generation */ | 3037 | #define IFSGEN 0x400 /* Internal Frame Sync Generation */ |
| 3903 | #define nIFSGEN 0x0 | ||
| 3904 | #define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ | 3038 | #define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ |
| 3905 | #define POLS 0x6000 /* Frame Sync Polarity */ | 3039 | #define POLS 0x6000 /* Frame Sync Polarity */ |
| 3906 | #define DLENGTH 0x38000 /* Data Length */ | 3040 | #define DLENGTH 0x38000 /* Data Length */ |
| 3907 | #define SKIP_EN 0x40000 /* Skip Enable */ | 3041 | #define SKIP_EN 0x40000 /* Skip Enable */ |
| 3908 | #define nSKIP_EN 0x0 | ||
| 3909 | #define SKIP_EO 0x80000 /* Skip Even or Odd */ | 3042 | #define SKIP_EO 0x80000 /* Skip Even or Odd */ |
| 3910 | #define nSKIP_EO 0x0 | ||
| 3911 | #define PACKEN 0x100000 /* Packing/Unpacking Enable */ | 3043 | #define PACKEN 0x100000 /* Packing/Unpacking Enable */ |
| 3912 | #define nPACKEN 0x0 | ||
| 3913 | #define SWAPEN 0x200000 /* Swap Enable */ | 3044 | #define SWAPEN 0x200000 /* Swap Enable */ |
| 3914 | #define nSWAPEN 0x0 | ||
| 3915 | #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ | 3045 | #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ |
| 3916 | #define nSIGN_EXT 0x0 | ||
| 3917 | #define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ | 3046 | #define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ |
| 3918 | #define nSPLT_EVEN_ODD 0x0 | ||
| 3919 | #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ | 3047 | #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ |
| 3920 | #define nSUBSPLT_ODD 0x0 | ||
| 3921 | #define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ | 3048 | #define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ |
| 3922 | #define nDMACFG 0x0 | ||
| 3923 | #define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ | 3049 | #define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ |
| 3924 | #define nRGB_FMT_EN 0x0 | ||
| 3925 | #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ | 3050 | #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ |
| 3926 | #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ | 3051 | #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ |
| 3927 | 3052 | ||
| @@ -3951,60 +3076,36 @@ | |||
| 3951 | /* Bit masks for SPIx_CTL */ | 3076 | /* Bit masks for SPIx_CTL */ |
| 3952 | 3077 | ||
| 3953 | #define SPE 0x4000 /* SPI Enable */ | 3078 | #define SPE 0x4000 /* SPI Enable */ |
| 3954 | #define nSPE 0x0 | ||
| 3955 | #define WOM 0x2000 /* Write Open Drain Master */ | 3079 | #define WOM 0x2000 /* Write Open Drain Master */ |
| 3956 | #define nWOM 0x0 | ||
| 3957 | #define MSTR 0x1000 /* Master Mode */ | 3080 | #define MSTR 0x1000 /* Master Mode */ |
| 3958 | #define nMSTR 0x0 | ||
| 3959 | #define CPOL 0x800 /* Clock Polarity */ | 3081 | #define CPOL 0x800 /* Clock Polarity */ |
| 3960 | #define nCPOL 0x0 | ||
| 3961 | #define CPHA 0x400 /* Clock Phase */ | 3082 | #define CPHA 0x400 /* Clock Phase */ |
| 3962 | #define nCPHA 0x0 | ||
| 3963 | #define LSBF 0x200 /* LSB First */ | 3083 | #define LSBF 0x200 /* LSB First */ |
| 3964 | #define nLSBF 0x0 | ||
| 3965 | #define SIZE 0x100 /* Size of Words */ | 3084 | #define SIZE 0x100 /* Size of Words */ |
| 3966 | #define nSIZE 0x0 | ||
| 3967 | #define EMISO 0x20 /* Enable MISO Output */ | 3085 | #define EMISO 0x20 /* Enable MISO Output */ |
| 3968 | #define nEMISO 0x0 | ||
| 3969 | #define PSSE 0x10 /* Slave-Select Enable */ | 3086 | #define PSSE 0x10 /* Slave-Select Enable */ |
| 3970 | #define nPSSE 0x0 | ||
| 3971 | #define GM 0x8 /* Get More Data */ | 3087 | #define GM 0x8 /* Get More Data */ |
| 3972 | #define nGM 0x0 | ||
| 3973 | #define SZ 0x4 /* Send Zero */ | 3088 | #define SZ 0x4 /* Send Zero */ |
| 3974 | #define nSZ 0x0 | ||
| 3975 | #define TIMOD 0x3 /* Transfer Initiation Mode */ | 3089 | #define TIMOD 0x3 /* Transfer Initiation Mode */ |
| 3976 | 3090 | ||
| 3977 | /* Bit masks for SPIx_FLG */ | 3091 | /* Bit masks for SPIx_FLG */ |
| 3978 | 3092 | ||
| 3979 | #define FLS1 0x2 /* Slave Select Enable 1 */ | 3093 | #define FLS1 0x2 /* Slave Select Enable 1 */ |
| 3980 | #define nFLS1 0x0 | ||
| 3981 | #define FLS2 0x4 /* Slave Select Enable 2 */ | 3094 | #define FLS2 0x4 /* Slave Select Enable 2 */ |
| 3982 | #define nFLS2 0x0 | ||
| 3983 | #define FLS3 0x8 /* Slave Select Enable 3 */ | 3095 | #define FLS3 0x8 /* Slave Select Enable 3 */ |
| 3984 | #define nFLS3 0x0 | ||
| 3985 | #define FLG1 0x200 /* Slave Select Value 1 */ | 3096 | #define FLG1 0x200 /* Slave Select Value 1 */ |
| 3986 | #define nFLG1 0x0 | ||
| 3987 | #define FLG2 0x400 /* Slave Select Value 2 */ | 3097 | #define FLG2 0x400 /* Slave Select Value 2 */ |
| 3988 | #define nFLG2 0x0 | ||
| 3989 | #define FLG3 0x800 /* Slave Select Value 3 */ | 3098 | #define FLG3 0x800 /* Slave Select Value 3 */ |
| 3990 | #define nFLG3 0x0 | ||
| 3991 | 3099 | ||
| 3992 | /* Bit masks for SPIx_STAT */ | 3100 | /* Bit masks for SPIx_STAT */ |
| 3993 | 3101 | ||
| 3994 | #define TXCOL 0x40 /* Transmit Collision Error */ | 3102 | #define TXCOL 0x40 /* Transmit Collision Error */ |
| 3995 | #define nTXCOL 0x0 | ||
| 3996 | #define RXS 0x20 /* RDBR Data Buffer Status */ | 3103 | #define RXS 0x20 /* RDBR Data Buffer Status */ |
| 3997 | #define nRXS 0x0 | ||
| 3998 | #define RBSY 0x10 /* Receive Error */ | 3104 | #define RBSY 0x10 /* Receive Error */ |
| 3999 | #define nRBSY 0x0 | ||
| 4000 | #define TXS 0x8 /* TDBR Data Buffer Status */ | 3105 | #define TXS 0x8 /* TDBR Data Buffer Status */ |
| 4001 | #define nTXS 0x0 | ||
| 4002 | #define TXE 0x4 /* Transmission Error */ | 3106 | #define TXE 0x4 /* Transmission Error */ |
| 4003 | #define nTXE 0x0 | ||
| 4004 | #define MODF 0x2 /* Mode Fault Error */ | 3107 | #define MODF 0x2 /* Mode Fault Error */ |
| 4005 | #define nMODF 0x0 | ||
| 4006 | #define SPIF 0x1 /* SPI Finished */ | 3108 | #define SPIF 0x1 /* SPI Finished */ |
| 4007 | #define nSPIF 0x0 | ||
| 4008 | 3109 | ||
| 4009 | /* Bit masks for SPIx_TDBR */ | 3110 | /* Bit masks for SPIx_TDBR */ |
| 4010 | 3111 | ||
| @@ -4028,9 +3129,7 @@ | |||
| 4028 | 3129 | ||
| 4029 | #define PRESCALE 0x7f /* Prescale Value */ | 3130 | #define PRESCALE 0x7f /* Prescale Value */ |
| 4030 | #define TWI_ENA 0x80 /* TWI Enable */ | 3131 | #define TWI_ENA 0x80 /* TWI Enable */ |
| 4031 | #define nTWI_ENA 0x0 | ||
| 4032 | #define SCCB 0x200 /* Serial Camera Control Bus */ | 3132 | #define SCCB 0x200 /* Serial Camera Control Bus */ |
| 4033 | #define nSCCB 0x0 | ||
| 4034 | 3133 | ||
| 4035 | /* Bit maskes for TWIx_CLKDIV */ | 3134 | /* Bit maskes for TWIx_CLKDIV */ |
| 4036 | 3135 | ||
| @@ -4040,13 +3139,9 @@ | |||
| 4040 | /* Bit maskes for TWIx_SLAVE_CTL */ | 3139 | /* Bit maskes for TWIx_SLAVE_CTL */ |
| 4041 | 3140 | ||
| 4042 | #define SEN 0x1 /* Slave Enable */ | 3141 | #define SEN 0x1 /* Slave Enable */ |
| 4043 | #define nSEN 0x0 | ||
| 4044 | #define STDVAL 0x4 /* Slave Transmit Data Valid */ | 3142 | #define STDVAL 0x4 /* Slave Transmit Data Valid */ |
| 4045 | #define nSTDVAL 0x0 | ||
| 4046 | #define NAK 0x8 /* Not Acknowledge */ | 3143 | #define NAK 0x8 /* Not Acknowledge */ |
| 4047 | #define nNAK 0x0 | ||
| 4048 | #define GEN 0x10 /* General Call Enable */ | 3144 | #define GEN 0x10 /* General Call Enable */ |
| 4049 | #define nGEN 0x0 | ||
| 4050 | 3145 | ||
| 4051 | /* Bit maskes for TWIx_SLAVE_ADDR */ | 3146 | /* Bit maskes for TWIx_SLAVE_ADDR */ |
| 4052 | 3147 | ||
| @@ -4055,27 +3150,18 @@ | |||
| 4055 | /* Bit maskes for TWIx_SLAVE_STAT */ | 3150 | /* Bit maskes for TWIx_SLAVE_STAT */ |
| 4056 | 3151 | ||
| 4057 | #define SDIR 0x1 /* Slave Transfer Direction */ | 3152 | #define SDIR 0x1 /* Slave Transfer Direction */ |
| 4058 | #define nSDIR 0x0 | ||
| 4059 | #define GCALL 0x2 /* General Call */ | 3153 | #define GCALL 0x2 /* General Call */ |
| 4060 | #define nGCALL 0x0 | ||
| 4061 | 3154 | ||
| 4062 | /* Bit maskes for TWIx_MASTER_CTL */ | 3155 | /* Bit maskes for TWIx_MASTER_CTL */ |
| 4063 | 3156 | ||
| 4064 | #define MEN 0x1 /* Master Mode Enable */ | 3157 | #define MEN 0x1 /* Master Mode Enable */ |
| 4065 | #define nMEN 0x0 | ||
| 4066 | #define MDIR 0x4 /* Master Transfer Direction */ | 3158 | #define MDIR 0x4 /* Master Transfer Direction */ |
| 4067 | #define nMDIR 0x0 | ||
| 4068 | #define FAST 0x8 /* Fast Mode */ | 3159 | #define FAST 0x8 /* Fast Mode */ |
| 4069 | #define nFAST 0x0 | ||
| 4070 | #define STOP 0x10 /* Issue Stop Condition */ | 3160 | #define STOP 0x10 /* Issue Stop Condition */ |
| 4071 | #define nSTOP 0x0 | ||
| 4072 | #define RSTART 0x20 /* Repeat Start */ | 3161 | #define RSTART 0x20 /* Repeat Start */ |
| 4073 | #define nRSTART 0x0 | ||
| 4074 | #define DCNT 0x3fc0 /* Data Transfer Count */ | 3162 | #define DCNT 0x3fc0 /* Data Transfer Count */ |
| 4075 | #define SDAOVR 0x4000 /* Serial Data Override */ | 3163 | #define SDAOVR 0x4000 /* Serial Data Override */ |
| 4076 | #define nSDAOVR 0x0 | ||
| 4077 | #define SCLOVR 0x8000 /* Serial Clock Override */ | 3164 | #define SCLOVR 0x8000 /* Serial Clock Override */ |
| 4078 | #define nSCLOVR 0x0 | ||
| 4079 | 3165 | ||
| 4080 | /* Bit maskes for TWIx_MASTER_ADDR */ | 3166 | /* Bit maskes for TWIx_MASTER_ADDR */ |
| 4081 | 3167 | ||
| @@ -4084,34 +3170,21 @@ | |||
| 4084 | /* Bit maskes for TWIx_MASTER_STAT */ | 3170 | /* Bit maskes for TWIx_MASTER_STAT */ |
| 4085 | 3171 | ||
| 4086 | #define MPROG 0x1 /* Master Transfer in Progress */ | 3172 | #define MPROG 0x1 /* Master Transfer in Progress */ |
| 4087 | #define nMPROG 0x0 | ||
| 4088 | #define LOSTARB 0x2 /* Lost Arbitration */ | 3173 | #define LOSTARB 0x2 /* Lost Arbitration */ |
| 4089 | #define nLOSTARB 0x0 | ||
| 4090 | #define ANAK 0x4 /* Address Not Acknowledged */ | 3174 | #define ANAK 0x4 /* Address Not Acknowledged */ |
| 4091 | #define nANAK 0x0 | ||
| 4092 | #define DNAK 0x8 /* Data Not Acknowledged */ | 3175 | #define DNAK 0x8 /* Data Not Acknowledged */ |
| 4093 | #define nDNAK 0x0 | ||
| 4094 | #define BUFRDERR 0x10 /* Buffer Read Error */ | 3176 | #define BUFRDERR 0x10 /* Buffer Read Error */ |
| 4095 | #define nBUFRDERR 0x0 | ||
| 4096 | #define BUFWRERR 0x20 /* Buffer Write Error */ | 3177 | #define BUFWRERR 0x20 /* Buffer Write Error */ |
| 4097 | #define nBUFWRERR 0x0 | ||
| 4098 | #define SDASEN 0x40 /* Serial Data Sense */ | 3178 | #define SDASEN 0x40 /* Serial Data Sense */ |
| 4099 | #define nSDASEN 0x0 | ||
| 4100 | #define SCLSEN 0x80 /* Serial Clock Sense */ | 3179 | #define SCLSEN 0x80 /* Serial Clock Sense */ |
| 4101 | #define nSCLSEN 0x0 | ||
| 4102 | #define BUSBUSY 0x100 /* Bus Busy */ | 3180 | #define BUSBUSY 0x100 /* Bus Busy */ |
| 4103 | #define nBUSBUSY 0x0 | ||
| 4104 | 3181 | ||
| 4105 | /* Bit maskes for TWIx_FIFO_CTL */ | 3182 | /* Bit maskes for TWIx_FIFO_CTL */ |
| 4106 | 3183 | ||
| 4107 | #define XMTFLUSH 0x1 /* Transmit Buffer Flush */ | 3184 | #define XMTFLUSH 0x1 /* Transmit Buffer Flush */ |
| 4108 | #define nXMTFLUSH 0x0 | ||
| 4109 | #define RCVFLUSH 0x2 /* Receive Buffer Flush */ | 3185 | #define RCVFLUSH 0x2 /* Receive Buffer Flush */ |
| 4110 | #define nRCVFLUSH 0x0 | ||
| 4111 | #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ | 3186 | #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ |
| 4112 | #define nXMTINTLEN 0x0 | ||
| 4113 | #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ | 3187 | #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ |
| 4114 | #define nRCVINTLEN 0x0 | ||
| 4115 | 3188 | ||
| 4116 | /* Bit maskes for TWIx_FIFO_STAT */ | 3189 | /* Bit maskes for TWIx_FIFO_STAT */ |
| 4117 | 3190 | ||
| @@ -4121,40 +3194,24 @@ | |||
| 4121 | /* Bit maskes for TWIx_INT_MASK */ | 3194 | /* Bit maskes for TWIx_INT_MASK */ |
| 4122 | 3195 | ||
| 4123 | #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ | 3196 | #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ |
| 4124 | #define nSINITM 0x0 | ||
| 4125 | #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ | 3197 | #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ |
| 4126 | #define nSCOMPM 0x0 | ||
| 4127 | #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ | 3198 | #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ |
| 4128 | #define nSERRM 0x0 | ||
| 4129 | #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ | 3199 | #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ |
| 4130 | #define nSOVFM 0x0 | ||
| 4131 | #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ | 3200 | #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ |
| 4132 | #define nMCOMPM 0x0 | ||
| 4133 | #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ | 3201 | #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ |
| 4134 | #define nMERRM 0x0 | ||
| 4135 | #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ | 3202 | #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ |
| 4136 | #define nXMTSERVM 0x0 | ||
| 4137 | #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ | 3203 | #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ |
| 4138 | #define nRCVSERVM 0x0 | ||
| 4139 | 3204 | ||
| 4140 | /* Bit maskes for TWIx_INT_STAT */ | 3205 | /* Bit maskes for TWIx_INT_STAT */ |
| 4141 | 3206 | ||
| 4142 | #define SINIT 0x1 /* Slave Transfer Initiated */ | 3207 | #define SINIT 0x1 /* Slave Transfer Initiated */ |
| 4143 | #define nSINIT 0x0 | ||
| 4144 | #define SCOMP 0x2 /* Slave Transfer Complete */ | 3208 | #define SCOMP 0x2 /* Slave Transfer Complete */ |
| 4145 | #define nSCOMP 0x0 | ||
| 4146 | #define SERR 0x4 /* Slave Transfer Error */ | 3209 | #define SERR 0x4 /* Slave Transfer Error */ |
| 4147 | #define nSERR 0x0 | ||
| 4148 | #define SOVF 0x8 /* Slave Overflow */ | 3210 | #define SOVF 0x8 /* Slave Overflow */ |
| 4149 | #define nSOVF 0x0 | ||
| 4150 | #define MCOMP 0x10 /* Master Transfer Complete */ | 3211 | #define MCOMP 0x10 /* Master Transfer Complete */ |
| 4151 | #define nMCOMP 0x0 | ||
| 4152 | #define MERR 0x20 /* Master Transfer Error */ | 3212 | #define MERR 0x20 /* Master Transfer Error */ |
| 4153 | #define nMERR 0x0 | ||
| 4154 | #define XMTSERV 0x40 /* Transmit FIFO Service */ | 3213 | #define XMTSERV 0x40 /* Transmit FIFO Service */ |
| 4155 | #define nXMTSERV 0x0 | ||
| 4156 | #define RCVSERV 0x80 /* Receive FIFO Service */ | 3214 | #define RCVSERV 0x80 /* Receive FIFO Service */ |
| 4157 | #define nRCVSERV 0x0 | ||
| 4158 | 3215 | ||
| 4159 | /* Bit maskes for TWIx_XMT_DATA8 */ | 3216 | /* Bit maskes for TWIx_XMT_DATA8 */ |
| 4160 | 3217 | ||
| @@ -4175,81 +3232,51 @@ | |||
| 4175 | /* Bit masks for SPORTx_TCR1 */ | 3232 | /* Bit masks for SPORTx_TCR1 */ |
| 4176 | 3233 | ||
| 4177 | #define TCKFE 0x4000 /* Clock Falling Edge Select */ | 3234 | #define TCKFE 0x4000 /* Clock Falling Edge Select */ |
| 4178 | #define nTCKFE 0x0 | ||
| 4179 | #define LATFS 0x2000 /* Late Transmit Frame Sync */ | 3235 | #define LATFS 0x2000 /* Late Transmit Frame Sync */ |
| 4180 | #define nLATFS 0x0 | ||
| 4181 | #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ | 3236 | #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ |
| 4182 | #define nLTFS 0x0 | ||
| 4183 | #define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ | 3237 | #define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ |
| 4184 | #define nDITFS 0x0 | ||
| 4185 | #define TFSR 0x400 /* Transmit Frame Sync Required Select */ | 3238 | #define TFSR 0x400 /* Transmit Frame Sync Required Select */ |
| 4186 | #define nTFSR 0x0 | ||
| 4187 | #define ITFS 0x200 /* Internal Transmit Frame Sync Select */ | 3239 | #define ITFS 0x200 /* Internal Transmit Frame Sync Select */ |
| 4188 | #define nITFS 0x0 | ||
| 4189 | #define TLSBIT 0x10 /* Transmit Bit Order */ | 3240 | #define TLSBIT 0x10 /* Transmit Bit Order */ |
| 4190 | #define nTLSBIT 0x0 | ||
| 4191 | #define TDTYPE 0xc /* Data Formatting Type Select */ | 3241 | #define TDTYPE 0xc /* Data Formatting Type Select */ |
| 4192 | #define ITCLK 0x2 /* Internal Transmit Clock Select */ | 3242 | #define ITCLK 0x2 /* Internal Transmit Clock Select */ |
| 4193 | #define nITCLK 0x0 | ||
| 4194 | #define TSPEN 0x1 /* Transmit Enable */ | 3243 | #define TSPEN 0x1 /* Transmit Enable */ |
| 4195 | #define nTSPEN 0x0 | ||
| 4196 | 3244 | ||
| 4197 | /* Bit masks for SPORTx_TCR2 */ | 3245 | /* Bit masks for SPORTx_TCR2 */ |
| 4198 | 3246 | ||
| 4199 | #define TRFST 0x400 /* Left/Right Order */ | 3247 | #define TRFST 0x400 /* Left/Right Order */ |
| 4200 | #define nTRFST 0x0 | ||
| 4201 | #define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ | 3248 | #define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ |
| 4202 | #define nTSFSE 0x0 | ||
| 4203 | #define TXSE 0x100 /* TxSEC Enable */ | 3249 | #define TXSE 0x100 /* TxSEC Enable */ |
| 4204 | #define nTXSE 0x0 | ||
| 4205 | #define SLEN_T 0x1f /* SPORT Word Length */ | 3250 | #define SLEN_T 0x1f /* SPORT Word Length */ |
| 4206 | 3251 | ||
| 4207 | /* Bit masks for SPORTx_RCR1 */ | 3252 | /* Bit masks for SPORTx_RCR1 */ |
| 4208 | 3253 | ||
| 4209 | #define RCKFE 0x4000 /* Clock Falling Edge Select */ | 3254 | #define RCKFE 0x4000 /* Clock Falling Edge Select */ |
| 4210 | #define nRCKFE 0x0 | ||
| 4211 | #define LARFS 0x2000 /* Late Receive Frame Sync */ | 3255 | #define LARFS 0x2000 /* Late Receive Frame Sync */ |
| 4212 | #define nLARFS 0x0 | ||
| 4213 | #define LRFS 0x1000 /* Low Receive Frame Sync Select */ | 3256 | #define LRFS 0x1000 /* Low Receive Frame Sync Select */ |
| 4214 | #define nLRFS 0x0 | ||
| 4215 | #define RFSR 0x400 /* Receive Frame Sync Required Select */ | 3257 | #define RFSR 0x400 /* Receive Frame Sync Required Select */ |
| 4216 | #define nRFSR 0x0 | ||
| 4217 | #define IRFS 0x200 /* Internal Receive Frame Sync Select */ | 3258 | #define IRFS 0x200 /* Internal Receive Frame Sync Select */ |
| 4218 | #define nIRFS 0x0 | ||
| 4219 | #define RLSBIT 0x10 /* Receive Bit Order */ | 3259 | #define RLSBIT 0x10 /* Receive Bit Order */ |
| 4220 | #define nRLSBIT 0x0 | ||
| 4221 | #define RDTYPE 0xc /* Data Formatting Type Select */ | 3260 | #define RDTYPE 0xc /* Data Formatting Type Select */ |
| 4222 | #define IRCLK 0x2 /* Internal Receive Clock Select */ | 3261 | #define IRCLK 0x2 /* Internal Receive Clock Select */ |
| 4223 | #define nIRCLK 0x0 | ||
| 4224 | #define RSPEN 0x1 /* Receive Enable */ | 3262 | #define RSPEN 0x1 /* Receive Enable */ |
| 4225 | #define nRSPEN 0x0 | ||
| 4226 | 3263 | ||
| 4227 | /* Bit masks for SPORTx_RCR2 */ | 3264 | /* Bit masks for SPORTx_RCR2 */ |
| 4228 | 3265 | ||
| 4229 | #define RRFST 0x400 /* Left/Right Order */ | 3266 | #define RRFST 0x400 /* Left/Right Order */ |
| 4230 | #define nRRFST 0x0 | ||
| 4231 | #define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ | 3267 | #define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ |
| 4232 | #define nRSFSE 0x0 | ||
| 4233 | #define RXSE 0x100 /* RxSEC Enable */ | 3268 | #define RXSE 0x100 /* RxSEC Enable */ |
| 4234 | #define nRXSE 0x0 | ||
| 4235 | #define SLEN_R 0x1f /* SPORT Word Length */ | 3269 | #define SLEN_R 0x1f /* SPORT Word Length */ |
| 4236 | 3270 | ||
| 4237 | /* Bit masks for SPORTx_STAT */ | 3271 | /* Bit masks for SPORTx_STAT */ |
| 4238 | 3272 | ||
| 4239 | #define TXHRE 0x40 /* Transmit Hold Register Empty */ | 3273 | #define TXHRE 0x40 /* Transmit Hold Register Empty */ |
| 4240 | #define nTXHRE 0x0 | ||
| 4241 | #define TOVF 0x20 /* Sticky Transmit Overflow Status */ | 3274 | #define TOVF 0x20 /* Sticky Transmit Overflow Status */ |
| 4242 | #define nTOVF 0x0 | ||
| 4243 | #define TUVF 0x10 /* Sticky Transmit Underflow Status */ | 3275 | #define TUVF 0x10 /* Sticky Transmit Underflow Status */ |
| 4244 | #define nTUVF 0x0 | ||
| 4245 | #define TXF 0x8 /* Transmit FIFO Full Status */ | 3276 | #define TXF 0x8 /* Transmit FIFO Full Status */ |
| 4246 | #define nTXF 0x0 | ||
| 4247 | #define ROVF 0x4 /* Sticky Receive Overflow Status */ | 3277 | #define ROVF 0x4 /* Sticky Receive Overflow Status */ |
| 4248 | #define nROVF 0x0 | ||
| 4249 | #define RUVF 0x2 /* Sticky Receive Underflow Status */ | 3278 | #define RUVF 0x2 /* Sticky Receive Underflow Status */ |
| 4250 | #define nRUVF 0x0 | ||
| 4251 | #define RXNE 0x1 /* Receive FIFO Not Empty Status */ | 3279 | #define RXNE 0x1 /* Receive FIFO Not Empty Status */ |
| 4252 | #define nRXNE 0x0 | ||
| 4253 | 3280 | ||
| 4254 | /* Bit masks for SPORTx_MCMC1 */ | 3281 | /* Bit masks for SPORTx_MCMC1 */ |
| 4255 | 3282 | ||
| @@ -4260,13 +3287,9 @@ | |||
| 4260 | 3287 | ||
| 4261 | #define MFD 0xf000 /* Multi channel Frame Delay */ | 3288 | #define MFD 0xf000 /* Multi channel Frame Delay */ |
| 4262 | #define FSDR 0x80 /* Frame Sync to Data Relationship */ | 3289 | #define FSDR 0x80 /* Frame Sync to Data Relationship */ |
| 4263 | #define nFSDR 0x0 | ||
| 4264 | #define MCMEM 0x10 /* Multi channel Frame Mode Enable */ | 3290 | #define MCMEM 0x10 /* Multi channel Frame Mode Enable */ |
| 4265 | #define nMCMEM 0x0 | ||
| 4266 | #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ | 3291 | #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ |
| 4267 | #define nMCDRXPE 0x0 | ||
| 4268 | #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ | 3292 | #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ |
| 4269 | #define nMCDTXPE 0x0 | ||
| 4270 | #define MCCRM 0x3 /* 2X Clock Recovery Mode */ | 3293 | #define MCCRM 0x3 /* 2X Clock Recovery Mode */ |
| 4271 | 3294 | ||
| 4272 | /* Bit masks for SPORTx_CHNL */ | 3295 | /* Bit masks for SPORTx_CHNL */ |
| @@ -4280,115 +3303,59 @@ | |||
| 4280 | #define WLS 0x3 /* Word Length Select */ | 3303 | #define WLS 0x3 /* Word Length Select */ |
| 4281 | #endif | 3304 | #endif |
| 4282 | #define STB 0x4 /* Stop Bits */ | 3305 | #define STB 0x4 /* Stop Bits */ |
| 4283 | #define nSTB 0x0 | ||
| 4284 | #define PEN 0x8 /* Parity Enable */ | 3306 | #define PEN 0x8 /* Parity Enable */ |
| 4285 | #define nPEN 0x0 | ||
| 4286 | #define EPS 0x10 /* Even Parity Select */ | 3307 | #define EPS 0x10 /* Even Parity Select */ |
| 4287 | #define nEPS 0x0 | ||
| 4288 | #define STP 0x20 /* Sticky Parity */ | 3308 | #define STP 0x20 /* Sticky Parity */ |
| 4289 | #define nSTP 0x0 | ||
| 4290 | #define SB 0x40 /* Set Break */ | 3309 | #define SB 0x40 /* Set Break */ |
| 4291 | #define nSB 0x0 | ||
| 4292 | 3310 | ||
| 4293 | /* Bit masks for UARTx_MCR */ | 3311 | /* Bit masks for UARTx_MCR */ |
| 4294 | 3312 | ||
| 4295 | #define XOFF 0x1 /* Transmitter Off */ | 3313 | #define XOFF 0x1 /* Transmitter Off */ |
| 4296 | #define nXOFF 0x0 | ||
| 4297 | #define MRTS 0x2 /* Manual Request To Send */ | 3314 | #define MRTS 0x2 /* Manual Request To Send */ |
| 4298 | #define nMRTS 0x0 | ||
| 4299 | #define RFIT 0x4 /* Receive FIFO IRQ Threshold */ | 3315 | #define RFIT 0x4 /* Receive FIFO IRQ Threshold */ |
| 4300 | #define nRFIT 0x0 | ||
| 4301 | #define RFRT 0x8 /* Receive FIFO RTS Threshold */ | 3316 | #define RFRT 0x8 /* Receive FIFO RTS Threshold */ |
| 4302 | #define nRFRT 0x0 | ||
| 4303 | #define LOOP_ENA 0x10 /* Loopback Mode Enable */ | 3317 | #define LOOP_ENA 0x10 /* Loopback Mode Enable */ |
| 4304 | #define nLOOP_ENA 0x0 | ||
| 4305 | #define FCPOL 0x20 /* Flow Control Pin Polarity */ | 3318 | #define FCPOL 0x20 /* Flow Control Pin Polarity */ |
| 4306 | #define nFCPOL 0x0 | ||
| 4307 | #define ARTS 0x40 /* Automatic Request To Send */ | 3319 | #define ARTS 0x40 /* Automatic Request To Send */ |
| 4308 | #define nARTS 0x0 | ||
| 4309 | #define ACTS 0x80 /* Automatic Clear To Send */ | 3320 | #define ACTS 0x80 /* Automatic Clear To Send */ |
| 4310 | #define nACTS 0x0 | ||
| 4311 | 3321 | ||
| 4312 | /* Bit masks for UARTx_LSR */ | 3322 | /* Bit masks for UARTx_LSR */ |
| 4313 | 3323 | ||
| 4314 | #define DR 0x1 /* Data Ready */ | 3324 | #define DR 0x1 /* Data Ready */ |
| 4315 | #define nDR 0x0 | ||
| 4316 | #define OE 0x2 /* Overrun Error */ | 3325 | #define OE 0x2 /* Overrun Error */ |
| 4317 | #define nOE 0x0 | ||
| 4318 | #define PE 0x4 /* Parity Error */ | 3326 | #define PE 0x4 /* Parity Error */ |
| 4319 | #define nPE 0x0 | ||
| 4320 | #define FE 0x8 /* Framing Error */ | 3327 | #define FE 0x8 /* Framing Error */ |
| 4321 | #define nFE 0x0 | ||
| 4322 | #define BI 0x10 /* Break Interrupt */ | 3328 | #define BI 0x10 /* Break Interrupt */ |
| 4323 | #define nBI 0x0 | ||
| 4324 | #define THRE 0x20 /* THR Empty */ | 3329 | #define THRE 0x20 /* THR Empty */ |
| 4325 | #define nTHRE 0x0 | ||
| 4326 | #define TEMT 0x40 /* Transmitter Empty */ | 3330 | #define TEMT 0x40 /* Transmitter Empty */ |
| 4327 | #define nTEMT 0x0 | ||
| 4328 | #define TFI 0x80 /* Transmission Finished Indicator */ | 3331 | #define TFI 0x80 /* Transmission Finished Indicator */ |
| 4329 | #define nTFI 0x0 | ||
| 4330 | 3332 | ||
| 4331 | /* Bit masks for UARTx_MSR */ | 3333 | /* Bit masks for UARTx_MSR */ |
| 4332 | 3334 | ||
| 4333 | #define SCTS 0x1 /* Sticky CTS */ | 3335 | #define SCTS 0x1 /* Sticky CTS */ |
| 4334 | #define nSCTS 0x0 | ||
| 4335 | #define CTS 0x10 /* Clear To Send */ | 3336 | #define CTS 0x10 /* Clear To Send */ |
| 4336 | #define nCTS 0x0 | ||
| 4337 | #define RFCS 0x20 /* Receive FIFO Count Status */ | 3337 | #define RFCS 0x20 /* Receive FIFO Count Status */ |
| 4338 | #define nRFCS 0x0 | 3338 | |
| 4339 | 3339 | /* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */ | |
| 4340 | /* Bit masks for UARTx_IER_SET */ | 3340 | |
| 4341 | 3341 | #define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */ | |
| 4342 | #define ERBFI_S 0x1 /* Enable Receive Buffer Full Interrupt */ | 3342 | #define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */ |
| 4343 | #define nERBFI_S 0x0 | 3343 | #define ELSI 0x4 /* Enable Receive Status Interrupt */ |
| 4344 | #define ETBEI_S 0x2 /* Enable Transmit Buffer Empty Interrupt */ | 3344 | #define EDSSI 0x8 /* Enable Modem Status Interrupt */ |
| 4345 | #define nETBEI_S 0x0 | 3345 | #define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ |
| 4346 | #define ELSI_S 0x4 /* Enable Receive Status Interrupt */ | 3346 | #define ETFI 0x20 /* Enable Transmission Finished Interrupt */ |
| 4347 | #define nELSI_S 0x0 | 3347 | #define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ |
| 4348 | #define EDSSI_S 0x8 /* Enable Modem Status Interrupt */ | ||
| 4349 | #define nEDSSI_S 0x0 | ||
| 4350 | #define EDTPTI_S 0x10 /* Enable DMA Transmit PIRQ Interrupt */ | ||
| 4351 | #define nEDTPTI_S 0x0 | ||
| 4352 | #define ETFI_S 0x20 /* Enable Transmission Finished Interrupt */ | ||
| 4353 | #define nETFI_S 0x0 | ||
| 4354 | #define ERFCI_S 0x40 /* Enable Receive FIFO Count Interrupt */ | ||
| 4355 | #define nERFCI_S 0x0 | ||
| 4356 | |||
| 4357 | /* Bit masks for UARTx_IER_CLEAR */ | ||
| 4358 | |||
| 4359 | #define ERBFI_C 0x1 /* Enable Receive Buffer Full Interrupt */ | ||
| 4360 | #define nERBFI_C 0x0 | ||
| 4361 | #define ETBEI_C 0x2 /* Enable Transmit Buffer Empty Interrupt */ | ||
| 4362 | #define nETBEI_C 0x0 | ||
| 4363 | #define ELSI_C 0x4 /* Enable Receive Status Interrupt */ | ||
| 4364 | #define nELSI_C 0x0 | ||
| 4365 | #define EDSSI_C 0x8 /* Enable Modem Status Interrupt */ | ||
| 4366 | #define nEDSSI_C 0x0 | ||
| 4367 | #define EDTPTI_C 0x10 /* Enable DMA Transmit PIRQ Interrupt */ | ||
| 4368 | #define nEDTPTI_C 0x0 | ||
| 4369 | #define ETFI_C 0x20 /* Enable Transmission Finished Interrupt */ | ||
| 4370 | #define nETFI_C 0x0 | ||
| 4371 | #define ERFCI_C 0x40 /* Enable Receive FIFO Count Interrupt */ | ||
| 4372 | #define nERFCI_C 0x0 | ||
| 4373 | 3348 | ||
| 4374 | /* Bit masks for UARTx_GCTL */ | 3349 | /* Bit masks for UARTx_GCTL */ |
| 4375 | 3350 | ||
| 4376 | #define UCEN 0x1 /* UART Enable */ | 3351 | #define UCEN 0x1 /* UART Enable */ |
| 4377 | #define nUCEN 0x0 | ||
| 4378 | #define IREN 0x2 /* IrDA Mode Enable */ | 3352 | #define IREN 0x2 /* IrDA Mode Enable */ |
| 4379 | #define nIREN 0x0 | ||
| 4380 | #define TPOLC 0x4 /* IrDA TX Polarity Change */ | 3353 | #define TPOLC 0x4 /* IrDA TX Polarity Change */ |
| 4381 | #define nTPOLC 0x0 | ||
| 4382 | #define RPOLC 0x8 /* IrDA RX Polarity Change */ | 3354 | #define RPOLC 0x8 /* IrDA RX Polarity Change */ |
| 4383 | #define nRPOLC 0x0 | ||
| 4384 | #define FPE 0x10 /* Force Parity Error */ | 3355 | #define FPE 0x10 /* Force Parity Error */ |
| 4385 | #define nFPE 0x0 | ||
| 4386 | #define FFE 0x20 /* Force Framing Error */ | 3356 | #define FFE 0x20 /* Force Framing Error */ |
| 4387 | #define nFFE 0x0 | ||
| 4388 | #define EDBO 0x40 /* Enable Divide-by-One */ | 3357 | #define EDBO 0x40 /* Enable Divide-by-One */ |
| 4389 | #define nEDBO 0x0 | ||
| 4390 | #define EGLSI 0x80 /* Enable Global LS Interrupt */ | 3358 | #define EGLSI 0x80 /* Enable Global LS Interrupt */ |
| 4391 | #define nEGLSI 0x0 | ||
| 4392 | 3359 | ||
| 4393 | 3360 | ||
| 4394 | /* ******************************************* */ | 3361 | /* ******************************************* */ |