diff options
| author | Roy Huang <roy.huang@analog.com> | 2007-07-12 10:41:45 -0400 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-07-12 10:41:45 -0400 |
| commit | 24a07a124198153540f8f43d9e91d16227aba66e (patch) | |
| tree | 917b2011e67e224515830833b1151e276b6c6137 /include/asm-blackfin/mach-bf548/defBF542.h | |
| parent | 088eec1192a0ae60fc218796027e622008af36c0 (diff) | |
Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia
applications where system performance and cost are essential ingredients. The
integration of multimedia, human interface, and connectivity peripherals combined
with increased system bandwidth and on-chip memory provides customers a platform to
design the most demanding applications.
Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers
such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will
be submitted later.
Please enjoy the show.
Signed-off-by: Roy Huang <roy.huang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf548/defBF542.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/defBF542.h | 281 |
1 files changed, 0 insertions, 281 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h index ac968fca5cc5..32d07130200c 100644 --- a/include/asm-blackfin/mach-bf548/defBF542.h +++ b/include/asm-blackfin/mach-bf548/defBF542.h | |||
| @@ -362,7 +362,6 @@ | |||
| 362 | /* Bit masks for KPAD_CTL */ | 362 | /* Bit masks for KPAD_CTL */ |
| 363 | 363 | ||
| 364 | #define KPAD_EN 0x1 /* Keypad Enable */ | 364 | #define KPAD_EN 0x1 /* Keypad Enable */ |
| 365 | #define nKPAD_EN 0x0 | ||
| 366 | #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ | 365 | #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ |
| 367 | #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ | 366 | #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ |
| 368 | #define KPAD_COLEN 0xe000 /* Column Enable Width */ | 367 | #define KPAD_COLEN 0xe000 /* Column Enable Width */ |
| @@ -384,29 +383,21 @@ | |||
| 384 | /* Bit masks for KPAD_STAT */ | 383 | /* Bit masks for KPAD_STAT */ |
| 385 | 384 | ||
| 386 | #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ | 385 | #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ |
| 387 | #define nKPAD_IRQ 0x0 | ||
| 388 | #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ | 386 | #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ |
| 389 | #define KPAD_PRESSED 0x8 /* Key press current status */ | 387 | #define KPAD_PRESSED 0x8 /* Key press current status */ |
| 390 | #define nKPAD_PRESSED 0x0 | ||
| 391 | 388 | ||
| 392 | /* Bit masks for KPAD_SOFTEVAL */ | 389 | /* Bit masks for KPAD_SOFTEVAL */ |
| 393 | 390 | ||
| 394 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ | 391 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ |
| 395 | #define nKPAD_SOFTEVAL_E 0x0 | ||
| 396 | 392 | ||
| 397 | /* Bit masks for SDH_COMMAND */ | 393 | /* Bit masks for SDH_COMMAND */ |
| 398 | 394 | ||
| 399 | #define CMD_IDX 0x3f /* Command Index */ | 395 | #define CMD_IDX 0x3f /* Command Index */ |
| 400 | #define CMD_RSP 0x40 /* Response */ | 396 | #define CMD_RSP 0x40 /* Response */ |
| 401 | #define nCMD_RSP 0x0 | ||
| 402 | #define CMD_L_RSP 0x80 /* Long Response */ | 397 | #define CMD_L_RSP 0x80 /* Long Response */ |
| 403 | #define nCMD_L_RSP 0x0 | ||
| 404 | #define CMD_INT_E 0x100 /* Command Interrupt */ | 398 | #define CMD_INT_E 0x100 /* Command Interrupt */ |
| 405 | #define nCMD_INT_E 0x0 | ||
| 406 | #define CMD_PEND_E 0x200 /* Command Pending */ | 399 | #define CMD_PEND_E 0x200 /* Command Pending */ |
| 407 | #define nCMD_PEND_E 0x0 | ||
| 408 | #define CMD_E 0x400 /* Command Enable */ | 400 | #define CMD_E 0x400 /* Command Enable */ |
| 409 | #define nCMD_E 0x0 | ||
| 410 | 401 | ||
| 411 | /* Bit masks for SDH_PWR_CTL */ | 402 | /* Bit masks for SDH_PWR_CTL */ |
| 412 | 403 | ||
| @@ -415,21 +406,15 @@ | |||
| 415 | #define TBD 0x3c /* TBD */ | 406 | #define TBD 0x3c /* TBD */ |
| 416 | #endif | 407 | #endif |
| 417 | #define SD_CMD_OD 0x40 /* Open Drain Output */ | 408 | #define SD_CMD_OD 0x40 /* Open Drain Output */ |
| 418 | #define nSD_CMD_OD 0x0 | ||
| 419 | #define ROD_CTL 0x80 /* Rod Control */ | 409 | #define ROD_CTL 0x80 /* Rod Control */ |
| 420 | #define nROD_CTL 0x0 | ||
| 421 | 410 | ||
| 422 | /* Bit masks for SDH_CLK_CTL */ | 411 | /* Bit masks for SDH_CLK_CTL */ |
| 423 | 412 | ||
| 424 | #define CLKDIV 0xff /* MC_CLK Divisor */ | 413 | #define CLKDIV 0xff /* MC_CLK Divisor */ |
| 425 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ | 414 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ |
| 426 | #define nCLK_E 0x0 | ||
| 427 | #define PWR_SV_E 0x200 /* Power Save Enable */ | 415 | #define PWR_SV_E 0x200 /* Power Save Enable */ |
| 428 | #define nPWR_SV_E 0x0 | ||
| 429 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ | 416 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ |
| 430 | #define nCLKDIV_BYPASS 0x0 | ||
| 431 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ | 417 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ |
| 432 | #define nWIDE_BUS 0x0 | ||
| 433 | 418 | ||
| 434 | /* Bit masks for SDH_RESP_CMD */ | 419 | /* Bit masks for SDH_RESP_CMD */ |
| 435 | 420 | ||
| @@ -438,133 +423,74 @@ | |||
| 438 | /* Bit masks for SDH_DATA_CTL */ | 423 | /* Bit masks for SDH_DATA_CTL */ |
| 439 | 424 | ||
| 440 | #define DTX_E 0x1 /* Data Transfer Enable */ | 425 | #define DTX_E 0x1 /* Data Transfer Enable */ |
| 441 | #define nDTX_E 0x0 | ||
| 442 | #define DTX_DIR 0x2 /* Data Transfer Direction */ | 426 | #define DTX_DIR 0x2 /* Data Transfer Direction */ |
| 443 | #define nDTX_DIR 0x0 | ||
| 444 | #define DTX_MODE 0x4 /* Data Transfer Mode */ | 427 | #define DTX_MODE 0x4 /* Data Transfer Mode */ |
| 445 | #define nDTX_MODE 0x0 | ||
| 446 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ | 428 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ |
| 447 | #define nDTX_DMA_E 0x0 | ||
| 448 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ | 429 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ |
| 449 | 430 | ||
| 450 | /* Bit masks for SDH_STATUS */ | 431 | /* Bit masks for SDH_STATUS */ |
| 451 | 432 | ||
| 452 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ | 433 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ |
| 453 | #define nCMD_CRC_FAIL 0x0 | ||
| 454 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ | 434 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ |
| 455 | #define nDAT_CRC_FAIL 0x0 | ||
| 456 | #define CMD_TIMEOUT 0x4 /* CMD Time Out */ | 435 | #define CMD_TIMEOUT 0x4 /* CMD Time Out */ |
| 457 | #define nCMD_TIMEOUT 0x0 | ||
| 458 | #define DAT_TIMEOUT 0x8 /* Data Time Out */ | 436 | #define DAT_TIMEOUT 0x8 /* Data Time Out */ |
| 459 | #define nDAT_TIMEOUT 0x0 | ||
| 460 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ | 437 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ |
| 461 | #define nTX_UNDERRUN 0x0 | ||
| 462 | #define RX_OVERRUN 0x20 /* Receive Overrun */ | 438 | #define RX_OVERRUN 0x20 /* Receive Overrun */ |
| 463 | #define nRX_OVERRUN 0x0 | ||
| 464 | #define CMD_RESP_END 0x40 /* CMD Response End */ | 439 | #define CMD_RESP_END 0x40 /* CMD Response End */ |
| 465 | #define nCMD_RESP_END 0x0 | ||
| 466 | #define CMD_SENT 0x80 /* CMD Sent */ | 440 | #define CMD_SENT 0x80 /* CMD Sent */ |
| 467 | #define nCMD_SENT 0x0 | ||
| 468 | #define DAT_END 0x100 /* Data End */ | 441 | #define DAT_END 0x100 /* Data End */ |
| 469 | #define nDAT_END 0x0 | ||
| 470 | #define START_BIT_ERR 0x200 /* Start Bit Error */ | 442 | #define START_BIT_ERR 0x200 /* Start Bit Error */ |
| 471 | #define nSTART_BIT_ERR 0x0 | ||
| 472 | #define DAT_BLK_END 0x400 /* Data Block End */ | 443 | #define DAT_BLK_END 0x400 /* Data Block End */ |
| 473 | #define nDAT_BLK_END 0x0 | ||
| 474 | #define CMD_ACT 0x800 /* CMD Active */ | 444 | #define CMD_ACT 0x800 /* CMD Active */ |
| 475 | #define nCMD_ACT 0x0 | ||
| 476 | #define TX_ACT 0x1000 /* Transmit Active */ | 445 | #define TX_ACT 0x1000 /* Transmit Active */ |
| 477 | #define nTX_ACT 0x0 | ||
| 478 | #define RX_ACT 0x2000 /* Receive Active */ | 446 | #define RX_ACT 0x2000 /* Receive Active */ |
| 479 | #define nRX_ACT 0x0 | ||
| 480 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ | 447 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ |
| 481 | #define nTX_FIFO_STAT 0x0 | ||
| 482 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ | 448 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ |
| 483 | #define nRX_FIFO_STAT 0x0 | ||
| 484 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ | 449 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ |
| 485 | #define nTX_FIFO_FULL 0x0 | ||
| 486 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ | 450 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ |
| 487 | #define nRX_FIFO_FULL 0x0 | ||
| 488 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ | 451 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ |
| 489 | #define nTX_FIFO_ZERO 0x0 | ||
| 490 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ | 452 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ |
| 491 | #define nRX_DAT_ZERO 0x0 | ||
| 492 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ | 453 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ |
| 493 | #define nTX_DAT_RDY 0x0 | ||
| 494 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ | 454 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ |
| 495 | #define nRX_FIFO_RDY 0x0 | ||
| 496 | 455 | ||
| 497 | /* Bit masks for SDH_STATUS_CLR */ | 456 | /* Bit masks for SDH_STATUS_CLR */ |
| 498 | 457 | ||
| 499 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ | 458 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ |
| 500 | #define nCMD_CRC_FAIL_STAT 0x0 | ||
| 501 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ | 459 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ |
| 502 | #define nDAT_CRC_FAIL_STAT 0x0 | ||
| 503 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ | 460 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ |
| 504 | #define nCMD_TIMEOUT_STAT 0x0 | ||
| 505 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ | 461 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ |
| 506 | #define nDAT_TIMEOUT_STAT 0x0 | ||
| 507 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ | 462 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ |
| 508 | #define nTX_UNDERRUN_STAT 0x0 | ||
| 509 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ | 463 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ |
| 510 | #define nRX_OVERRUN_STAT 0x0 | ||
| 511 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ | 464 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ |
| 512 | #define nCMD_RESP_END_STAT 0x0 | ||
| 513 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ | 465 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ |
| 514 | #define nCMD_SENT_STAT 0x0 | ||
| 515 | #define DAT_END_STAT 0x100 /* Data End Status */ | 466 | #define DAT_END_STAT 0x100 /* Data End Status */ |
| 516 | #define nDAT_END_STAT 0x0 | ||
| 517 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ | 467 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ |
| 518 | #define nSTART_BIT_ERR_STAT 0x0 | ||
| 519 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ | 468 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ |
| 520 | #define nDAT_BLK_END_STAT 0x0 | ||
| 521 | 469 | ||
| 522 | /* Bit masks for SDH_MASK0 */ | 470 | /* Bit masks for SDH_MASK0 */ |
| 523 | 471 | ||
| 524 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ | 472 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ |
| 525 | #define nCMD_CRC_FAIL_MASK 0x0 | ||
| 526 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ | 473 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ |
| 527 | #define nDAT_CRC_FAIL_MASK 0x0 | ||
| 528 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ | 474 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ |
| 529 | #define nCMD_TIMEOUT_MASK 0x0 | ||
| 530 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ | 475 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ |
| 531 | #define nDAT_TIMEOUT_MASK 0x0 | ||
| 532 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ | 476 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ |
| 533 | #define nTX_UNDERRUN_MASK 0x0 | ||
| 534 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ | 477 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ |
| 535 | #define nRX_OVERRUN_MASK 0x0 | ||
| 536 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ | 478 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ |
| 537 | #define nCMD_RESP_END_MASK 0x0 | ||
| 538 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ | 479 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ |
| 539 | #define nCMD_SENT_MASK 0x0 | ||
| 540 | #define DAT_END_MASK 0x100 /* Data End Mask */ | 480 | #define DAT_END_MASK 0x100 /* Data End Mask */ |
| 541 | #define nDAT_END_MASK 0x0 | ||
| 542 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ | 481 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ |
| 543 | #define nSTART_BIT_ERR_MASK 0x0 | ||
| 544 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ | 482 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ |
| 545 | #define nDAT_BLK_END_MASK 0x0 | ||
| 546 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ | 483 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ |
| 547 | #define nCMD_ACT_MASK 0x0 | ||
| 548 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ | 484 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ |
| 549 | #define nTX_ACT_MASK 0x0 | ||
| 550 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ | 485 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ |
| 551 | #define nRX_ACT_MASK 0x0 | ||
| 552 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ | 486 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ |
| 553 | #define nTX_FIFO_STAT_MASK 0x0 | ||
| 554 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ | 487 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ |
| 555 | #define nRX_FIFO_STAT_MASK 0x0 | ||
| 556 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ | 488 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ |
| 557 | #define nTX_FIFO_FULL_MASK 0x0 | ||
| 558 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ | 489 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ |
| 559 | #define nRX_FIFO_FULL_MASK 0x0 | ||
| 560 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ | 490 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ |
| 561 | #define nTX_FIFO_ZERO_MASK 0x0 | ||
| 562 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ | 491 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ |
| 563 | #define nRX_DAT_ZERO_MASK 0x0 | ||
| 564 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ | 492 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ |
| 565 | #define nTX_DAT_RDY_MASK 0x0 | ||
| 566 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ | 493 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ |
| 567 | #define nRX_FIFO_RDY_MASK 0x0 | ||
| 568 | 494 | ||
| 569 | /* Bit masks for SDH_FIFO_CNT */ | 495 | /* Bit masks for SDH_FIFO_CNT */ |
| 570 | 496 | ||
| @@ -573,73 +499,47 @@ | |||
| 573 | /* Bit masks for SDH_E_STATUS */ | 499 | /* Bit masks for SDH_E_STATUS */ |
| 574 | 500 | ||
| 575 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ | 501 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ |
| 576 | #define nSDIO_INT_DET 0x0 | ||
| 577 | #define SD_CARD_DET 0x10 /* SD Card Detect */ | 502 | #define SD_CARD_DET 0x10 /* SD Card Detect */ |
| 578 | #define nSD_CARD_DET 0x0 | ||
| 579 | 503 | ||
| 580 | /* Bit masks for SDH_E_MASK */ | 504 | /* Bit masks for SDH_E_MASK */ |
| 581 | 505 | ||
| 582 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ | 506 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ |
| 583 | #define nSDIO_MSK 0x0 | ||
| 584 | #define SCD_MSK 0x40 /* Mask Card Detect */ | 507 | #define SCD_MSK 0x40 /* Mask Card Detect */ |
| 585 | #define nSCD_MSK 0x0 | ||
| 586 | 508 | ||
| 587 | /* Bit masks for SDH_CFG */ | 509 | /* Bit masks for SDH_CFG */ |
| 588 | 510 | ||
| 589 | #define CLKS_EN 0x1 /* Clocks Enable */ | 511 | #define CLKS_EN 0x1 /* Clocks Enable */ |
| 590 | #define nCLKS_EN 0x0 | ||
| 591 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ | 512 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ |
| 592 | #define nSD4E 0x0 | ||
| 593 | #define MWE 0x8 /* Moving Window Enable */ | 513 | #define MWE 0x8 /* Moving Window Enable */ |
| 594 | #define nMWE 0x0 | ||
| 595 | #define SD_RST 0x10 /* SDMMC Reset */ | 514 | #define SD_RST 0x10 /* SDMMC Reset */ |
| 596 | #define nSD_RST 0x0 | ||
| 597 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ | 515 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ |
| 598 | #define nPUP_SDDAT 0x0 | ||
| 599 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ | 516 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ |
| 600 | #define nPUP_SDDAT3 0x0 | ||
| 601 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ | 517 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ |
| 602 | #define nPD_SDDAT3 0x0 | ||
| 603 | 518 | ||
| 604 | /* Bit masks for SDH_RD_WAIT_EN */ | 519 | /* Bit masks for SDH_RD_WAIT_EN */ |
| 605 | 520 | ||
| 606 | #define RWR 0x1 /* Read Wait Request */ | 521 | #define RWR 0x1 /* Read Wait Request */ |
| 607 | #define nRWR 0x0 | ||
| 608 | 522 | ||
| 609 | /* Bit masks for ATAPI_CONTROL */ | 523 | /* Bit masks for ATAPI_CONTROL */ |
| 610 | 524 | ||
| 611 | #define PIO_START 0x1 /* Start PIO/Reg Op */ | 525 | #define PIO_START 0x1 /* Start PIO/Reg Op */ |
| 612 | #define nPIO_START 0x0 | ||
| 613 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ | 526 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ |
| 614 | #define nMULTI_START 0x0 | ||
| 615 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ | 527 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ |
| 616 | #define nULTRA_START 0x0 | ||
| 617 | #define XFER_DIR 0x8 /* Transfer Direction */ | 528 | #define XFER_DIR 0x8 /* Transfer Direction */ |
| 618 | #define nXFER_DIR 0x0 | ||
| 619 | #define IORDY_EN 0x10 /* IORDY Enable */ | 529 | #define IORDY_EN 0x10 /* IORDY Enable */ |
| 620 | #define nIORDY_EN 0x0 | ||
| 621 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ | 530 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ |
| 622 | #define nFIFO_FLUSH 0x0 | ||
| 623 | #define SOFT_RST 0x40 /* Soft Reset */ | 531 | #define SOFT_RST 0x40 /* Soft Reset */ |
| 624 | #define nSOFT_RST 0x0 | ||
| 625 | #define DEV_RST 0x80 /* Device Reset */ | 532 | #define DEV_RST 0x80 /* Device Reset */ |
| 626 | #define nDEV_RST 0x0 | ||
| 627 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ | 533 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ |
| 628 | #define nTFRCNT_RST 0x0 | ||
| 629 | #define END_ON_TERM 0x200 /* End/Terminate Select */ | 534 | #define END_ON_TERM 0x200 /* End/Terminate Select */ |
| 630 | #define nEND_ON_TERM 0x0 | ||
| 631 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ | 535 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ |
| 632 | #define nPIO_USE_DMA 0x0 | ||
| 633 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ | 536 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ |
| 634 | 537 | ||
| 635 | /* Bit masks for ATAPI_STATUS */ | 538 | /* Bit masks for ATAPI_STATUS */ |
| 636 | 539 | ||
| 637 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ | 540 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ |
| 638 | #define nPIO_XFER_ON 0x0 | ||
| 639 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ | 541 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ |
| 640 | #define nMULTI_XFER_ON 0x0 | ||
| 641 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ | 542 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ |
| 642 | #define nULTRA_XFER_ON 0x0 | ||
| 643 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ | 543 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ |
| 644 | 544 | ||
| 645 | /* Bit masks for ATAPI_DEV_ADDR */ | 545 | /* Bit masks for ATAPI_DEV_ADDR */ |
| @@ -649,66 +549,39 @@ | |||
| 649 | /* Bit masks for ATAPI_INT_MASK */ | 549 | /* Bit masks for ATAPI_INT_MASK */ |
| 650 | 550 | ||
| 651 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ | 551 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ |
| 652 | #define nATAPI_DEV_INT_MASK 0x0 | ||
| 653 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ | 552 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ |
| 654 | #define nPIO_DONE_MASK 0x0 | ||
| 655 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ | 553 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ |
| 656 | #define nMULTI_DONE_MASK 0x0 | ||
| 657 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ | 554 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ |
| 658 | #define nUDMAIN_DONE_MASK 0x0 | ||
| 659 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ | 555 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ |
| 660 | #define nUDMAOUT_DONE_MASK 0x0 | ||
| 661 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ | 556 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ |
| 662 | #define nHOST_TERM_XFER_MASK 0x0 | ||
| 663 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ | 557 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ |
| 664 | #define nMULTI_TERM_MASK 0x0 | ||
| 665 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ | 558 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ |
| 666 | #define nUDMAIN_TERM_MASK 0x0 | ||
| 667 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ | 559 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ |
| 668 | #define nUDMAOUT_TERM_MASK 0x0 | ||
| 669 | 560 | ||
| 670 | /* Bit masks for ATAPI_INT_STATUS */ | 561 | /* Bit masks for ATAPI_INT_STATUS */ |
| 671 | 562 | ||
| 672 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ | 563 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ |
| 673 | #define nATAPI_DEV_INT 0x0 | ||
| 674 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ | 564 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ |
| 675 | #define nPIO_DONE_INT 0x0 | ||
| 676 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ | 565 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ |
| 677 | #define nMULTI_DONE_INT 0x0 | ||
| 678 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ | 566 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ |
| 679 | #define nUDMAIN_DONE_INT 0x0 | ||
| 680 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ | 567 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ |
| 681 | #define nUDMAOUT_DONE_INT 0x0 | ||
| 682 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ | 568 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ |
| 683 | #define nHOST_TERM_XFER_INT 0x0 | ||
| 684 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ | 569 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ |
| 685 | #define nMULTI_TERM_INT 0x0 | ||
| 686 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ | 570 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ |
| 687 | #define nUDMAIN_TERM_INT 0x0 | ||
| 688 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ | 571 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ |
| 689 | #define nUDMAOUT_TERM_INT 0x0 | ||
| 690 | 572 | ||
| 691 | /* Bit masks for ATAPI_LINE_STATUS */ | 573 | /* Bit masks for ATAPI_LINE_STATUS */ |
| 692 | 574 | ||
| 693 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ | 575 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ |
| 694 | #define nATAPI_INTR 0x0 | ||
| 695 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ | 576 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ |
| 696 | #define nATAPI_DASP 0x0 | ||
| 697 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ | 577 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ |
| 698 | #define nATAPI_CS0N 0x0 | ||
| 699 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ | 578 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ |
| 700 | #define nATAPI_CS1N 0x0 | ||
| 701 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ | 579 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ |
| 702 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ | 580 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ |
| 703 | #define nATAPI_DMAREQ 0x0 | ||
| 704 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ | 581 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ |
| 705 | #define nATAPI_DMAACKN 0x0 | ||
| 706 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ | 582 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ |
| 707 | #define nATAPI_DIOWN 0x0 | ||
| 708 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ | 583 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ |
| 709 | #define nATAPI_DIORN 0x0 | ||
| 710 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ | 584 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ |
| 711 | #define nATAPI_IORDY 0x0 | ||
| 712 | 585 | ||
| 713 | /* Bit masks for ATAPI_SM_STATE */ | 586 | /* Bit masks for ATAPI_SM_STATE */ |
| 714 | 587 | ||
| @@ -720,7 +593,6 @@ | |||
| 720 | /* Bit masks for ATAPI_TERMINATE */ | 593 | /* Bit masks for ATAPI_TERMINATE */ |
| 721 | 594 | ||
| 722 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ | 595 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ |
| 723 | #define nATAPI_HOST_TERM 0x0 | ||
| 724 | 596 | ||
| 725 | /* Bit masks for ATAPI_REG_TIM_0 */ | 597 | /* Bit masks for ATAPI_REG_TIM_0 */ |
| 726 | 598 | ||
| @@ -779,131 +651,77 @@ | |||
| 779 | /* Bit masks for USB_POWER */ | 651 | /* Bit masks for USB_POWER */ |
| 780 | 652 | ||
| 781 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | 653 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ |
| 782 | #define nENABLE_SUSPENDM 0x0 | ||
| 783 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | 654 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ |
| 784 | #define nSUSPEND_MODE 0x0 | ||
| 785 | #define RESUME_MODE 0x4 /* DMA Mode */ | 655 | #define RESUME_MODE 0x4 /* DMA Mode */ |
| 786 | #define nRESUME_MODE 0x0 | ||
| 787 | #define RESET 0x8 /* Reset indicator */ | 656 | #define RESET 0x8 /* Reset indicator */ |
| 788 | #define nRESET 0x0 | ||
| 789 | #define HS_MODE 0x10 /* High Speed mode indicator */ | 657 | #define HS_MODE 0x10 /* High Speed mode indicator */ |
| 790 | #define nHS_MODE 0x0 | ||
| 791 | #define HS_ENABLE 0x20 /* high Speed Enable */ | 658 | #define HS_ENABLE 0x20 /* high Speed Enable */ |
| 792 | #define nHS_ENABLE 0x0 | ||
| 793 | #define SOFT_CONN 0x40 /* Soft connect */ | 659 | #define SOFT_CONN 0x40 /* Soft connect */ |
| 794 | #define nSOFT_CONN 0x0 | ||
| 795 | #define ISO_UPDATE 0x80 /* Isochronous update */ | 660 | #define ISO_UPDATE 0x80 /* Isochronous update */ |
| 796 | #define nISO_UPDATE 0x0 | ||
| 797 | 661 | ||
| 798 | /* Bit masks for USB_INTRTX */ | 662 | /* Bit masks for USB_INTRTX */ |
| 799 | 663 | ||
| 800 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | 664 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ |
| 801 | #define nEP0_TX 0x0 | ||
| 802 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | 665 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ |
| 803 | #define nEP1_TX 0x0 | ||
| 804 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | 666 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ |
| 805 | #define nEP2_TX 0x0 | ||
| 806 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | 667 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ |
| 807 | #define nEP3_TX 0x0 | ||
| 808 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | 668 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ |
| 809 | #define nEP4_TX 0x0 | ||
| 810 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | 669 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ |
| 811 | #define nEP5_TX 0x0 | ||
| 812 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | 670 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ |
| 813 | #define nEP6_TX 0x0 | ||
| 814 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | 671 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ |
| 815 | #define nEP7_TX 0x0 | ||
| 816 | 672 | ||
| 817 | /* Bit masks for USB_INTRRX */ | 673 | /* Bit masks for USB_INTRRX */ |
| 818 | 674 | ||
| 819 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | 675 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ |
| 820 | #define nEP1_RX 0x0 | ||
| 821 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | 676 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ |
| 822 | #define nEP2_RX 0x0 | ||
| 823 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | 677 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ |
| 824 | #define nEP3_RX 0x0 | ||
| 825 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | 678 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ |
| 826 | #define nEP4_RX 0x0 | ||
| 827 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | 679 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ |
| 828 | #define nEP5_RX 0x0 | ||
| 829 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | 680 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ |
| 830 | #define nEP6_RX 0x0 | ||
| 831 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | 681 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ |
| 832 | #define nEP7_RX 0x0 | ||
| 833 | 682 | ||
| 834 | /* Bit masks for USB_INTRTXE */ | 683 | /* Bit masks for USB_INTRTXE */ |
| 835 | 684 | ||
| 836 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | 685 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ |
| 837 | #define nEP0_TX_E 0x0 | ||
| 838 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | 686 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ |
| 839 | #define nEP1_TX_E 0x0 | ||
| 840 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | 687 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ |
| 841 | #define nEP2_TX_E 0x0 | ||
| 842 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | 688 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ |
| 843 | #define nEP3_TX_E 0x0 | ||
| 844 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | 689 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ |
| 845 | #define nEP4_TX_E 0x0 | ||
| 846 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | 690 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ |
| 847 | #define nEP5_TX_E 0x0 | ||
| 848 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | 691 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ |
| 849 | #define nEP6_TX_E 0x0 | ||
| 850 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | 692 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ |
| 851 | #define nEP7_TX_E 0x0 | ||
| 852 | 693 | ||
| 853 | /* Bit masks for USB_INTRRXE */ | 694 | /* Bit masks for USB_INTRRXE */ |
| 854 | 695 | ||
| 855 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | 696 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ |
| 856 | #define nEP1_RX_E 0x0 | ||
| 857 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | 697 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ |
| 858 | #define nEP2_RX_E 0x0 | ||
| 859 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | 698 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ |
| 860 | #define nEP3_RX_E 0x0 | ||
| 861 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | 699 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ |
| 862 | #define nEP4_RX_E 0x0 | ||
| 863 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | 700 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ |
| 864 | #define nEP5_RX_E 0x0 | ||
| 865 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | 701 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ |
| 866 | #define nEP6_RX_E 0x0 | ||
| 867 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | 702 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ |
| 868 | #define nEP7_RX_E 0x0 | ||
| 869 | 703 | ||
| 870 | /* Bit masks for USB_INTRUSB */ | 704 | /* Bit masks for USB_INTRUSB */ |
| 871 | 705 | ||
| 872 | #define SUSPEND_B 0x1 /* Suspend indicator */ | 706 | #define SUSPEND_B 0x1 /* Suspend indicator */ |
| 873 | #define nSUSPEND_B 0x0 | ||
| 874 | #define RESUME_B 0x2 /* Resume indicator */ | 707 | #define RESUME_B 0x2 /* Resume indicator */ |
| 875 | #define nRESUME_B 0x0 | ||
| 876 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | 708 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ |
| 877 | #define nRESET_OR_BABLE_B 0x0 | ||
| 878 | #define SOF_B 0x8 /* Start of frame */ | 709 | #define SOF_B 0x8 /* Start of frame */ |
| 879 | #define nSOF_B 0x0 | ||
| 880 | #define CONN_B 0x10 /* Connection indicator */ | 710 | #define CONN_B 0x10 /* Connection indicator */ |
| 881 | #define nCONN_B 0x0 | ||
| 882 | #define DISCON_B 0x20 /* Disconnect indicator */ | 711 | #define DISCON_B 0x20 /* Disconnect indicator */ |
| 883 | #define nDISCON_B 0x0 | ||
| 884 | #define SESSION_REQ_B 0x40 /* Session Request */ | 712 | #define SESSION_REQ_B 0x40 /* Session Request */ |
| 885 | #define nSESSION_REQ_B 0x0 | ||
| 886 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | 713 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ |
| 887 | #define nVBUS_ERROR_B 0x0 | ||
| 888 | 714 | ||
| 889 | /* Bit masks for USB_INTRUSBE */ | 715 | /* Bit masks for USB_INTRUSBE */ |
| 890 | 716 | ||
| 891 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | 717 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ |
| 892 | #define nSUSPEND_BE 0x0 | ||
| 893 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | 718 | #define RESUME_BE 0x2 /* Resume indicator int enable */ |
| 894 | #define nRESUME_BE 0x0 | ||
| 895 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | 719 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ |
| 896 | #define nRESET_OR_BABLE_BE 0x0 | ||
| 897 | #define SOF_BE 0x8 /* Start of frame int enable */ | 720 | #define SOF_BE 0x8 /* Start of frame int enable */ |
| 898 | #define nSOF_BE 0x0 | ||
| 899 | #define CONN_BE 0x10 /* Connection indicator int enable */ | 721 | #define CONN_BE 0x10 /* Connection indicator int enable */ |
| 900 | #define nCONN_BE 0x0 | ||
| 901 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | 722 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ |
| 902 | #define nDISCON_BE 0x0 | ||
| 903 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | 723 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ |
| 904 | #define nSESSION_REQ_BE 0x0 | ||
| 905 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | 724 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ |
| 906 | #define nVBUS_ERROR_BE 0x0 | ||
| 907 | 725 | ||
| 908 | /* Bit masks for USB_FRAME */ | 726 | /* Bit masks for USB_FRAME */ |
| 909 | 727 | ||
| @@ -916,117 +734,67 @@ | |||
| 916 | /* Bit masks for USB_GLOBAL_CTL */ | 734 | /* Bit masks for USB_GLOBAL_CTL */ |
| 917 | 735 | ||
| 918 | #define GLOBAL_ENA 0x1 /* enables USB module */ | 736 | #define GLOBAL_ENA 0x1 /* enables USB module */ |
| 919 | #define nGLOBAL_ENA 0x0 | ||
| 920 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | 737 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ |
| 921 | #define nEP1_TX_ENA 0x0 | ||
| 922 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | 738 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ |
| 923 | #define nEP2_TX_ENA 0x0 | ||
| 924 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | 739 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ |
| 925 | #define nEP3_TX_ENA 0x0 | ||
| 926 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | 740 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ |
| 927 | #define nEP4_TX_ENA 0x0 | ||
| 928 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | 741 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ |
| 929 | #define nEP5_TX_ENA 0x0 | ||
| 930 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | 742 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ |
| 931 | #define nEP6_TX_ENA 0x0 | ||
| 932 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | 743 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ |
| 933 | #define nEP7_TX_ENA 0x0 | ||
| 934 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | 744 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ |
| 935 | #define nEP1_RX_ENA 0x0 | ||
| 936 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | 745 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ |
| 937 | #define nEP2_RX_ENA 0x0 | ||
| 938 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | 746 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ |
| 939 | #define nEP3_RX_ENA 0x0 | ||
| 940 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | 747 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ |
| 941 | #define nEP4_RX_ENA 0x0 | ||
| 942 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | 748 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ |
| 943 | #define nEP5_RX_ENA 0x0 | ||
| 944 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | 749 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ |
| 945 | #define nEP6_RX_ENA 0x0 | ||
| 946 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | 750 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ |
| 947 | #define nEP7_RX_ENA 0x0 | ||
| 948 | 751 | ||
| 949 | /* Bit masks for USB_OTG_DEV_CTL */ | 752 | /* Bit masks for USB_OTG_DEV_CTL */ |
| 950 | 753 | ||
| 951 | #define SESSION 0x1 /* session indicator */ | 754 | #define SESSION 0x1 /* session indicator */ |
| 952 | #define nSESSION 0x0 | ||
| 953 | #define HOST_REQ 0x2 /* Host negotiation request */ | 755 | #define HOST_REQ 0x2 /* Host negotiation request */ |
| 954 | #define nHOST_REQ 0x0 | ||
| 955 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | 756 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ |
| 956 | #define nHOST_MODE 0x0 | ||
| 957 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | 757 | #define VBUS0 0x8 /* Vbus level indicator[0] */ |
| 958 | #define nVBUS0 0x0 | ||
| 959 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | 758 | #define VBUS1 0x10 /* Vbus level indicator[1] */ |
| 960 | #define nVBUS1 0x0 | ||
| 961 | #define LSDEV 0x20 /* Low-speed indicator */ | 759 | #define LSDEV 0x20 /* Low-speed indicator */ |
| 962 | #define nLSDEV 0x0 | ||
| 963 | #define FSDEV 0x40 /* Full or High-speed indicator */ | 760 | #define FSDEV 0x40 /* Full or High-speed indicator */ |
| 964 | #define nFSDEV 0x0 | ||
| 965 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | 761 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ |
| 966 | #define nB_DEVICE 0x0 | ||
| 967 | 762 | ||
| 968 | /* Bit masks for USB_OTG_VBUS_IRQ */ | 763 | /* Bit masks for USB_OTG_VBUS_IRQ */ |
| 969 | 764 | ||
| 970 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | 765 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ |
| 971 | #define nDRIVE_VBUS_ON 0x0 | ||
| 972 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | 766 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ |
| 973 | #define nDRIVE_VBUS_OFF 0x0 | ||
| 974 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | 767 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ |
| 975 | #define nCHRG_VBUS_START 0x0 | ||
| 976 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | 768 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ |
| 977 | #define nCHRG_VBUS_END 0x0 | ||
| 978 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | 769 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ |
| 979 | #define nDISCHRG_VBUS_START 0x0 | ||
| 980 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | 770 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ |
| 981 | #define nDISCHRG_VBUS_END 0x0 | ||
| 982 | 771 | ||
| 983 | /* Bit masks for USB_OTG_VBUS_MASK */ | 772 | /* Bit masks for USB_OTG_VBUS_MASK */ |
| 984 | 773 | ||
| 985 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | 774 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ |
| 986 | #define nDRIVE_VBUS_ON_ENA 0x0 | ||
| 987 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | 775 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ |
| 988 | #define nDRIVE_VBUS_OFF_ENA 0x0 | ||
| 989 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | 776 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ |
| 990 | #define nCHRG_VBUS_START_ENA 0x0 | ||
| 991 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | 777 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ |
| 992 | #define nCHRG_VBUS_END_ENA 0x0 | ||
| 993 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | 778 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ |
| 994 | #define nDISCHRG_VBUS_START_ENA 0x0 | ||
| 995 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | 779 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ |
| 996 | #define nDISCHRG_VBUS_END_ENA 0x0 | ||
| 997 | 780 | ||
| 998 | /* Bit masks for USB_CSR0 */ | 781 | /* Bit masks for USB_CSR0 */ |
| 999 | 782 | ||
| 1000 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | 783 | #define RXPKTRDY 0x1 /* data packet receive indicator */ |
| 1001 | #define nRXPKTRDY 0x0 | ||
| 1002 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | 784 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ |
| 1003 | #define nTXPKTRDY 0x0 | ||
| 1004 | #define STALL_SENT 0x4 /* STALL handshake sent */ | 785 | #define STALL_SENT 0x4 /* STALL handshake sent */ |
| 1005 | #define nSTALL_SENT 0x0 | ||
| 1006 | #define DATAEND 0x8 /* Data end indicator */ | 786 | #define DATAEND 0x8 /* Data end indicator */ |
| 1007 | #define nDATAEND 0x0 | ||
| 1008 | #define SETUPEND 0x10 /* Setup end */ | 787 | #define SETUPEND 0x10 /* Setup end */ |
| 1009 | #define nSETUPEND 0x0 | ||
| 1010 | #define SENDSTALL 0x20 /* Send STALL handshake */ | 788 | #define SENDSTALL 0x20 /* Send STALL handshake */ |
| 1011 | #define nSENDSTALL 0x0 | ||
| 1012 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | 789 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ |
| 1013 | #define nSERVICED_RXPKTRDY 0x0 | ||
| 1014 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | 790 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ |
| 1015 | #define nSERVICED_SETUPEND 0x0 | ||
| 1016 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | 791 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ |
| 1017 | #define nFLUSHFIFO 0x0 | ||
| 1018 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | 792 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ |
| 1019 | #define nSTALL_RECEIVED_H 0x0 | ||
| 1020 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | 793 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ |
| 1021 | #define nSETUPPKT_H 0x0 | ||
| 1022 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | 794 | #define ERROR_H 0x10 /* timeout error indicator host mode */ |
| 1023 | #define nERROR_H 0x0 | ||
| 1024 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | 795 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ |
| 1025 | #define nREQPKT_H 0x0 | ||
| 1026 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | 796 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ |
| 1027 | #define nSTATUSPKT_H 0x0 | ||
| 1028 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | 797 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ |
| 1029 | #define nNAK_TIMEOUT_H 0x0 | ||
| 1030 | 798 | ||
| 1031 | /* Bit masks for USB_COUNT0 */ | 799 | /* Bit masks for USB_COUNT0 */ |
| 1032 | 800 | ||
| @@ -1047,37 +815,21 @@ | |||
| 1047 | /* Bit masks for USB_TXCSR */ | 815 | /* Bit masks for USB_TXCSR */ |
| 1048 | 816 | ||
| 1049 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | 817 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ |
| 1050 | #define nTXPKTRDY_T 0x0 | ||
| 1051 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | 818 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ |
| 1052 | #define nFIFO_NOT_EMPTY_T 0x0 | ||
| 1053 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | 819 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ |
| 1054 | #define nUNDERRUN_T 0x0 | ||
| 1055 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | 820 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ |
| 1056 | #define nFLUSHFIFO_T 0x0 | ||
| 1057 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | 821 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ |
| 1058 | #define nSTALL_SEND_T 0x0 | ||
| 1059 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | 822 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ |
| 1060 | #define nSTALL_SENT_T 0x0 | ||
| 1061 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | 823 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ |
| 1062 | #define nCLEAR_DATATOGGLE_T 0x0 | ||
| 1063 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | 824 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ |
| 1064 | #define nINCOMPTX_T 0x0 | ||
| 1065 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | 825 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ |
| 1066 | #define nDMAREQMODE_T 0x0 | ||
| 1067 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | 826 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ |
| 1068 | #define nFORCE_DATATOGGLE_T 0x0 | ||
| 1069 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | 827 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ |
| 1070 | #define nDMAREQ_ENA_T 0x0 | ||
| 1071 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | 828 | #define ISO_T 0x4000 /* enable Isochronous transfers */ |
| 1072 | #define nISO_T 0x0 | ||
| 1073 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | 829 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ |
| 1074 | #define nAUTOSET_T 0x0 | ||
| 1075 | #define ERROR_TH 0x4 /* error condition host mode */ | 830 | #define ERROR_TH 0x4 /* error condition host mode */ |
| 1076 | #define nERROR_TH 0x0 | ||
| 1077 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | 831 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ |
| 1078 | #define nSTALL_RECEIVED_TH 0x0 | ||
| 1079 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | 832 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ |
| 1080 | #define nNAK_TIMEOUT_TH 0x0 | ||
| 1081 | 833 | ||
| 1082 | /* Bit masks for USB_TXCOUNT */ | 834 | /* Bit masks for USB_TXCOUNT */ |
| 1083 | 835 | ||
| @@ -1086,45 +838,25 @@ | |||
| 1086 | /* Bit masks for USB_RXCSR */ | 838 | /* Bit masks for USB_RXCSR */ |
| 1087 | 839 | ||
| 1088 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | 840 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ |
| 1089 | #define nRXPKTRDY_R 0x0 | ||
| 1090 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | 841 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ |
| 1091 | #define nFIFO_FULL_R 0x0 | ||
| 1092 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | 842 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ |
| 1093 | #define nOVERRUN_R 0x0 | ||
| 1094 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | 843 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ |
| 1095 | #define nDATAERROR_R 0x0 | ||
| 1096 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | 844 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ |
| 1097 | #define nFLUSHFIFO_R 0x0 | ||
| 1098 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | 845 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ |
| 1099 | #define nSTALL_SEND_R 0x0 | ||
| 1100 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | 846 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ |
| 1101 | #define nSTALL_SENT_R 0x0 | ||
| 1102 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | 847 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ |
| 1103 | #define nCLEAR_DATATOGGLE_R 0x0 | ||
| 1104 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | 848 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ |
| 1105 | #define nINCOMPRX_R 0x0 | ||
| 1106 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | 849 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ |
| 1107 | #define nDMAREQMODE_R 0x0 | ||
| 1108 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | 850 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ |
| 1109 | #define nDISNYET_R 0x0 | ||
| 1110 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | 851 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ |
| 1111 | #define nDMAREQ_ENA_R 0x0 | ||
| 1112 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | 852 | #define ISO_R 0x4000 /* enable Isochronous transfers */ |
| 1113 | #define nISO_R 0x0 | ||
| 1114 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | 853 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ |
| 1115 | #define nAUTOCLEAR_R 0x0 | ||
| 1116 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | 854 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ |
| 1117 | #define nERROR_RH 0x0 | ||
| 1118 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | 855 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ |
| 1119 | #define nREQPKT_RH 0x0 | ||
| 1120 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | 856 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ |
| 1121 | #define nSTALL_RECEIVED_RH 0x0 | ||
| 1122 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | 857 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ |
| 1123 | #define nINCOMPRX_RH 0x0 | ||
| 1124 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | 858 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ |
| 1125 | #define nDMAREQMODE_RH 0x0 | ||
| 1126 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | 859 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ |
| 1127 | #define nAUTOREQ_RH 0x0 | ||
| 1128 | 860 | ||
| 1129 | /* Bit masks for USB_RXCOUNT */ | 861 | /* Bit masks for USB_RXCOUNT */ |
| 1130 | 862 | ||
| @@ -1151,35 +883,22 @@ | |||
| 1151 | /* Bit masks for USB_DMA_INTERRUPT */ | 883 | /* Bit masks for USB_DMA_INTERRUPT */ |
| 1152 | 884 | ||
| 1153 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | 885 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ |
| 1154 | #define nDMA0_INT 0x0 | ||
| 1155 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | 886 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ |
| 1156 | #define nDMA1_INT 0x0 | ||
| 1157 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | 887 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ |
| 1158 | #define nDMA2_INT 0x0 | ||
| 1159 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | 888 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ |
| 1160 | #define nDMA3_INT 0x0 | ||
| 1161 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | 889 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ |
| 1162 | #define nDMA4_INT 0x0 | ||
| 1163 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | 890 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ |
| 1164 | #define nDMA5_INT 0x0 | ||
| 1165 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | 891 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ |
| 1166 | #define nDMA6_INT 0x0 | ||
| 1167 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | 892 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ |
| 1168 | #define nDMA7_INT 0x0 | ||
| 1169 | 893 | ||
| 1170 | /* Bit masks for USB_DMAxCONTROL */ | 894 | /* Bit masks for USB_DMAxCONTROL */ |
| 1171 | 895 | ||
| 1172 | #define DMA_ENA 0x1 /* DMA enable */ | 896 | #define DMA_ENA 0x1 /* DMA enable */ |
| 1173 | #define nDMA_ENA 0x0 | ||
| 1174 | #define DIRECTION 0x2 /* direction of DMA transfer */ | 897 | #define DIRECTION 0x2 /* direction of DMA transfer */ |
| 1175 | #define nDIRECTION 0x0 | ||
| 1176 | #define MODE 0x4 /* DMA Bus error */ | 898 | #define MODE 0x4 /* DMA Bus error */ |
| 1177 | #define nMODE 0x0 | ||
| 1178 | #define INT_ENA 0x8 /* Interrupt enable */ | 899 | #define INT_ENA 0x8 /* Interrupt enable */ |
| 1179 | #define nINT_ENA 0x0 | ||
| 1180 | #define EPNUM 0xf0 /* EP number */ | 900 | #define EPNUM 0xf0 /* EP number */ |
| 1181 | #define BUSERROR 0x100 /* DMA Bus error */ | 901 | #define BUSERROR 0x100 /* DMA Bus error */ |
| 1182 | #define nBUSERROR 0x0 | ||
| 1183 | 902 | ||
| 1184 | /* Bit masks for USB_DMAxADDRHIGH */ | 903 | /* Bit masks for USB_DMAxADDRHIGH */ |
| 1185 | 904 | ||