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authorRoy Huang <roy.huang@analog.com>2007-07-12 10:41:45 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-12 10:41:45 -0400
commit24a07a124198153540f8f43d9e91d16227aba66e (patch)
tree917b2011e67e224515830833b1151e276b6c6137 /include/asm-blackfin/mach-bf548/anomaly.h
parent088eec1192a0ae60fc218796027e622008af36c0 (diff)
Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will be submitted later. Please enjoy the show. Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf548/anomaly.h')
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index ddc150e6fb0f..aca1d4ba145c 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -47,6 +47,8 @@
47 SPORT external receive and transmit clocks. */ 47 SPORT external receive and transmit clocks. */
48#define ANOMALY_05000272 /* Certain data cache write through modes fail for 48#define ANOMALY_05000272 /* Certain data cache write through modes fail for
49 VDDint <=0.9V */ 49 VDDint <=0.9V */
50#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
51 not restored */
50#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the 52#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
51 Boundary of Reserved Memory */ 53 Boundary of Reserved Memory */
52#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and 54#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and