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authorBryan Wu <bryan.wu@analog.com>2007-05-06 17:50:22 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-07 15:12:58 -0400
commit1394f03221790a988afc3e4b3cb79f2e477246a9 (patch)
tree2c1963c9a4f2d84a5e021307fde240c5d567cf70 /include/asm-blackfin/mach-bf537
parent73243284463a761e04d69d22c7516b2be7de096c (diff)
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf537')
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h120
-rw-r--r--include/asm-blackfin/mach-bf537/bf537.h287
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h147
-rw-r--r--include/asm-blackfin/mach-bf537/blackfin.h430
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF534.h1823
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF537.h209
-rw-r--r--include/asm-blackfin/mach-bf537/defBF534.h2501
-rw-r--r--include/asm-blackfin/mach-bf537/defBF537.h404
-rw-r--r--include/asm-blackfin/mach-bf537/dma.h55
-rw-r--r--include/asm-blackfin/mach-bf537/irq.h219
-rw-r--r--include/asm-blackfin/mach-bf537/mem_init.h330
-rw-r--r--include/asm-blackfin/mach-bf537/mem_map.h175
12 files changed, 6700 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
new file mode 100644
index 000000000000..7f040f5ba018
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -0,0 +1,120 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf537/anomaly.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING.
29 * If not, write to the Free Software Foundation,
30 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 */
32
33/* This file shoule be up to date with:
34 * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
35 * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
36 * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
37 */
38
39#ifndef _MACH_ANOMALY_H_
40#define _MACH_ANOMALY_H_
41
42/* We do not support 0.1 silicon - sorry */
43#if (defined(CONFIG_BF_REV_0_1))
44#error Kernel will not work on BF537/6/4 Version 0.1
45#endif
46
47#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
48#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
49 slot1 and store of a P register in slot 2 is not
50 supported */
51#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
52 Channel DMA stops */
53#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
54 registers. */
55#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
56 upper bits*/
57#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
58 syncs */
59#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
60#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
61 Changed */
62#endif
63#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
64 SPORT external receive and transmit clocks. */
65#define ANOMALY_05000272 /* Certain data cache write through modes fail for
66 VDDint <=0.9V */
67#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
68#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
69 an edge is detected may clear interrupt */
70#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
71 not restored */
72#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
73 control */
74#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
75 killed in a particular stage*/
76#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
77 registers are interrupted */
78#endif
79
80#if defined(CONFIG_BF_REV_0_2)
81#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
82 IDLE around a Change of Control causes
83 unpredictable results */
84#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
85 (TDM) */
86#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
87#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
88#endif
89#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
90#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
91 interrupt not functional */
92#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
93#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
94#endif
95#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
96 loops may cause the instruction fetch unit to
97 malfunction */
98#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
99 the ICPLB Data registers differ */
100#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
101#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
102#define ANOMALY_05000262 /* Stores to data cache may be lost */
103#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
104#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
105 instruction will cause an infinite stall in the
106 second to last instruction in a hardware loop */
107#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
108 and non-zero DEB_TRAFFIC_PERIOD value */
109#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
110 internal voltage regulator (VDDint) to decrease */
111#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
112 an edge is detected may clear interrupt */
113#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
114 DMA system instability */
115#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
116 Atmel Dataflash devices */
117
118#endif /* CONFIG_BF_REV_0_2 */
119
120#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
new file mode 100644
index 000000000000..b8924cd7730c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/bf537.h
@@ -0,0 +1,287 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/bf537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF537_H__
31#define __MACH_BF537_H__
32
33#define SUPPORTED_REVID 2
34
35/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
36
37#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
38#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
39#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
42#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
43#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
44
45#define OFFSET_(x) ((x) & 0x0000FFFF)
46
47/*some misc defines*/
48#define IMASK_IVG15 0x8000
49#define IMASK_IVG14 0x4000
50#define IMASK_IVG13 0x2000
51#define IMASK_IVG12 0x1000
52
53#define IMASK_IVG11 0x0800
54#define IMASK_IVG10 0x0400
55#define IMASK_IVG9 0x0200
56#define IMASK_IVG8 0x0100
57
58#define IMASK_IVG7 0x0080
59#define IMASK_IVGTMR 0x0040
60#define IMASK_IVGHW 0x0020
61
62/***************************/
63
64
65#define BLKFIN_DSUBBANKS 4
66#define BLKFIN_DWAYS 2
67#define BLKFIN_DLINES 64
68#define BLKFIN_ISUBBANKS 4
69#define BLKFIN_IWAYS 4
70#define BLKFIN_ILINES 32
71
72#define WAY0_L 0x1
73#define WAY1_L 0x2
74#define WAY01_L 0x3
75#define WAY2_L 0x4
76#define WAY02_L 0x5
77#define WAY12_L 0x6
78#define WAY012_L 0x7
79
80#define WAY3_L 0x8
81#define WAY03_L 0x9
82#define WAY13_L 0xA
83#define WAY013_L 0xB
84
85#define WAY32_L 0xC
86#define WAY320_L 0xD
87#define WAY321_L 0xE
88#define WAYALL_L 0xF
89
90#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
91
92/********************************* EBIU Settings ************************************/
93#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
94#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
95
96#ifdef CONFIG_C_AMBEN_ALL
97#define V_AMBEN AMBEN_ALL
98#endif
99#ifdef CONFIG_C_AMBEN
100#define V_AMBEN 0x0
101#endif
102#ifdef CONFIG_C_AMBEN_B0
103#define V_AMBEN AMBEN_B0
104#endif
105#ifdef CONFIG_C_AMBEN_B0_B1
106#define V_AMBEN AMBEN_B0_B1
107#endif
108#ifdef CONFIG_C_AMBEN_B0_B1_B2
109#define V_AMBEN AMBEN_B0_B1_B2
110#endif
111#ifdef CONFIG_C_AMCKEN
112#define V_AMCKEN AMCKEN
113#else
114#define V_AMCKEN 0x0
115#endif
116#ifdef CONFIG_C_CDPRIO
117#define V_CDPRIO 0x100
118#else
119#define V_CDPRIO 0x0
120#endif
121
122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
123
124#define MAX_VC 650000000
125#define MIN_VC 50000000
126
127/********************************PLL Settings **************************************/
128#ifdef CONFIG_BFIN_KERNEL_CLOCK
129#if (CONFIG_VCO_MULT < 0)
130#error "VCO Multiplier is less than 0. Please select a different value"
131#endif
132
133#if (CONFIG_VCO_MULT == 0)
134#error "VCO Multiplier should be greater than 0. Please select a different value"
135#endif
136
137#if (CONFIG_VCO_MULT > 64)
138#error "VCO Multiplier is more than 64. Please select a different value"
139#endif
140
141#ifndef CONFIG_CLKIN_HALF
142#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
143#else
144#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
145#endif
146
147#ifndef CONFIG_PLL_BYPASS
148#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
149#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
150#else
151#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
152#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
153#endif
154
155#if (CONFIG_SCLK_DIV < 1)
156#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
157#endif
158
159#if (CONFIG_SCLK_DIV > 15)
160#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
161#endif
162
163#if (CONFIG_CCLK_DIV != 1)
164#if (CONFIG_CCLK_DIV != 2)
165#if (CONFIG_CCLK_DIV != 4)
166#if (CONFIG_CCLK_DIV != 8)
167#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
168#endif
169#endif
170#endif
171#endif
172
173#if (CONFIG_VCO_HZ > MAX_VC)
174#error "VCO selected is more than maximum value. Please change the VCO multipler"
175#endif
176
177#if (CONFIG_SCLK_HZ > 133000000)
178#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
179#endif
180
181#if (CONFIG_SCLK_HZ < 27000000)
182#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
183#endif
184
185#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
186#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
187#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
188#error "Please select sclk less than cclk"
189#endif
190#endif
191#endif
192
193#if (CONFIG_CCLK_DIV == 1)
194#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
195#endif
196#if (CONFIG_CCLK_DIV == 2)
197#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
198#endif
199#if (CONFIG_CCLK_DIV == 4)
200#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
201#endif
202#if (CONFIG_CCLK_DIV == 8)
203#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
204#endif
205#ifndef CONFIG_CCLK_ACT_DIV
206#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
207#endif
208
209#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
210#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
211#endif
212
213#endif /* CONFIG_BFIN_KERNEL_CLOCK */
214
215#ifdef CONFIG_BF537
216#define CPU "BF537"
217#define CPUID 0x027c8000
218#endif
219#ifdef CONFIG_BF536
220#define CPU "BF536"
221#define CPUID 0x027c8000
222#endif
223#ifdef CONFIG_BF534
224#define CPU "BF534"
225#define CPUID 0x027c6000
226#endif
227#ifndef CPU
228#define CPU "UNKNOWN"
229#define CPUID 0x0
230#endif
231
232#if (CONFIG_MEM_SIZE % 4)
233#error "SDRAM mem size must be multible of 4MB"
234#endif
235
236#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
237#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
238#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
239#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
240
241/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
242
243#define ANOMALY_05000158_WORKAROUND 0x200
244#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
245#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
246 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
247#else /*Write Through */
248#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
249 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
250#endif
251
252
253#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
254#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
255#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
256#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
257
258#define SIZE_1K 0x00000400 /* 1K */
259#define SIZE_4K 0x00001000 /* 4K */
260#define SIZE_1M 0x00100000 /* 1M */
261#define SIZE_4M 0x00400000 /* 4M */
262
263#define MAX_CPLBS (16 * 2)
264
265/*
266* Number of required data CPLB switchtable entries
267* MEMSIZE / 4 (we mostly install 4M page size CPLBs
268* approx 16 for smaller 1MB page size CPLBs for allignment purposes
269* 1 for L1 Data Memory
270* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
271* 1 for ASYNC Memory
272*/
273
274
275#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
276
277/*
278* Number of required instruction CPLB switchtable entries
279* MEMSIZE / 4 (we mostly install 4M page size CPLBs
280* approx 12 for smaller 1MB page size CPLBs for allignment purposes
281* 1 for L1 Instruction Memory
282* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
283*/
284
285#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
286
287#endif /* __MACH_BF537_H__ */
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
new file mode 100644
index 000000000000..8f5d9c4d8d5b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -0,0 +1,147 @@
1#include <linux/serial.h>
2#include <asm/dma.h>
3
4#define NR_PORTS 2
5
6#define OFFSET_THR 0x00 /* Transmit Holding register */
7#define OFFSET_RBR 0x00 /* Receive Buffer register */
8#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
9#define OFFSET_IER 0x04 /* Interrupt Enable Register */
10#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
11#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
12#define OFFSET_LCR 0x0C /* Line Control Register */
13#define OFFSET_MCR 0x10 /* Modem Control Register */
14#define OFFSET_LSR 0x14 /* Line Status Register */
15#define OFFSET_MSR 0x18 /* Modem Status Register */
16#define OFFSET_SCR 0x1C /* SCR Scratch Register */
17#define OFFSET_GCTL 0x24 /* Global Control Register */
18
19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
27
28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
30#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
32#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
33#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
34
35#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
36# define CONFIG_SERIAL_BFIN_CTSRTS
37
38# ifndef CONFIG_UART0_CTS_PIN
39# define CONFIG_UART0_CTS_PIN -1
40# endif
41
42# ifndef CONFIG_UART0_RTS_PIN
43# define CONFIG_UART0_RTS_PIN -1
44# endif
45
46# ifndef CONFIG_UART1_CTS_PIN
47# define CONFIG_UART1_CTS_PIN -1
48# endif
49
50# ifndef CONFIG_UART1_RTS_PIN
51# define CONFIG_UART1_RTS_PIN -1
52# endif
53#endif
54/*
55 * The pin configuration is different from schematic
56 */
57struct bfin_serial_port {
58 struct uart_port port;
59 unsigned int old_status;
60#ifdef CONFIG_SERIAL_BFIN_DMA
61 int tx_done;
62 int tx_count;
63 struct circ_buf rx_dma_buf;
64 struct timer_list rx_dma_timer;
65 int rx_dma_nrows;
66 unsigned int tx_dma_channel;
67 unsigned int rx_dma_channel;
68 struct work_struct tx_dma_workqueue;
69#else
70 struct work_struct cts_workqueue;
71#endif
72#ifdef CONFIG_SERIAL_BFIN_CTSRTS
73 int cts_pin;
74 int rts_pin;
75#endif
76};
77
78struct bfin_serial_port bfin_serial_ports[NR_PORTS];
79struct bfin_serial_res {
80 unsigned long uart_base_addr;
81 int uart_irq;
82#ifdef CONFIG_SERIAL_BFIN_DMA
83 unsigned int uart_tx_dma_channel;
84 unsigned int uart_rx_dma_channel;
85#endif
86#ifdef CONFIG_SERIAL_BFIN_CTSRTS
87 int uart_cts_pin;
88 int uart_rts_pin;
89#endif
90};
91
92struct bfin_serial_res bfin_serial_resource[] = {
93#ifdef CONFIG_SERIAL_BFIN_UART0
94 {
95 0xFFC00400,
96 IRQ_UART0_RX,
97#ifdef CONFIG_SERIAL_BFIN_DMA
98 CH_UART0_TX,
99 CH_UART0_RX,
100#endif
101#ifdef CONFIG_BFIN_UART0_CTSRTS
102 CONFIG_UART0_CTS_PIN,
103 CONFIG_UART0_RTS_PIN,
104#endif
105 },
106#endif
107#ifdef CONFIG_SERIAL_BFIN_UART1
108 {
109 0xFFC02000,
110 IRQ_UART1_RX,
111#ifdef CONFIG_SERIAL_BFIN_DMA
112 CH_UART1_TX,
113 CH_UART1_RX,
114#endif
115#ifdef CONFIG_BFIN_UART1_CTSRTS
116 CONFIG_UART1_CTS_PIN,
117 CONFIG_UART1_RTS_PIN,
118#endif
119 },
120#endif
121};
122
123int nr_ports = ARRAY_SIZE(bfin_serial_resource);
124
125static void bfin_serial_hw_init(struct bfin_serial_port *uart)
126{
127 unsigned short val;
128 val = bfin_read16(BFIN_PORT_MUX);
129 val &= ~(PFDE | PFTE);
130 bfin_write16(BFIN_PORT_MUX, val);
131
132 val = bfin_read16(PORTF_FER);
133 val |= 0xF;
134 bfin_write16(PORTF_FER, val);
135
136#ifdef CONFIG_SERIAL_BFIN_CTSRTS
137 if (uart->cts_pin >= 0) {
138 gpio_request(uart->cts_pin, NULL);
139 gpio_direction_input(uart->cts_pin);
140 }
141
142 if (uart->rts_pin >= 0) {
143 gpio_request(uart->rts_pin, NULL);
144 gpio_direction_output(uart->rts_pin);
145 }
146#endif
147}
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
new file mode 100644
index 000000000000..bbd97051ec9c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -0,0 +1,430 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF537_FAMILY
36
37#include "bf537.h"
38#include "mem_map.h"
39#include "defBF534.h"
40#include "anomaly.h"
41
42#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
43#include "defBF537.h"
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
47#include "cdefBF534.h"
48
49/* UART 0*/
50#define bfin_read_UART_THR() bfin_read_UART0_THR()
51#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
52#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
53#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
54#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
55#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
56#define bfin_read_UART_IER() bfin_read_UART0_IER()
57#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
58#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
59#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
60#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
61#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
62#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
63#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
64#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
65#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
66#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
67#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
68#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
69#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
70#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
71#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
72
73#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
74#include "cdefBF537.h"
75#endif
76#endif
77
78/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */
79
80/* UART_IIR Register */
81#define STATUS(x) ((x << 1) & 0x06)
82#define STATUS_P1 0x02
83#define STATUS_P0 0x01
84
85/* UART 0*/
86
87/* DMA Channnel */
88#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
89#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
90#define CH_UART_RX CH_UART0_RX
91#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX()
92#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val)
93#define CH_UART_TX CH_UART0_TX
94
95/* System Interrupt Controller */
96#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX()
97#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val)
98#define IRQ_UART_RX IRQ_UART0_RX
99#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX()
100#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val)
101#define IRQ_UART_TX IRQ_UART0_TX
102#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR()
103#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val)
104#define IRQ_UART_ERROR IRQ_UART0_ERROR
105
106/* MMR Registers*/
107#define bfin_read_UART_THR() bfin_read_UART0_THR()
108#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
109#define UART_THR UART0_THR
110#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
111#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
112#define UART_RBR UART0_RBR
113#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
114#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
115#define UART_DLL UART0_DLL
116#define bfin_read_UART_IER() bfin_read_UART0_IER()
117#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
118#define UART_IER UART0_IER
119#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
120#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
121#define UART_DLH UART0_DLH
122#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
123#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
124#define UART_IIR UART0_IIR
125#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
126#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
127#define UART_LCR UART0_LCR
128#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
129#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
130#define UART_MCR UART0_MCR
131#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
132#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
133#define UART_LSR UART0_LSR
134#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
135#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
136#define UART_SCR UART0_SCR
137#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
138#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
139#define UART_GCTL UART0_GCTL
140
141/* DPMC*/
142#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
143#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
144#define STOPCK_OFF STOPCK
145
146/* FIO USE PORT F*/
147#ifdef CONFIG_BF537_PORT_F
148#define bfin_read_PORT_FER() bfin_read_PORTF_FER()
149#define bfin_write_PORT_FER(val) bfin_write_PORTF_FER(val)
150#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
151#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
152#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
153#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
154#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
155#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
156#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
157#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
158#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
159#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
160#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
161#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
162#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
163#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
164#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
165#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
166#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
167#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
168#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
169#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
170#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
171#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
172#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
173#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
174#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
175#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
176#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
177#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
178#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
179#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
180#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
181#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
182#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
183#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
184
185#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
186#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
187#define FIO_FLAG_D PORTFIO
188#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
189#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
190#define FIO_FLAG_C PORTFIO_CLEAR
191#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
192#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
193#define FIO_FLAG_S PORTFIO_SET
194#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
195#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
196#define FIO_FLAG_T PORTFIO_TOGGLE
197#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
198#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
199#define FIO_MASKA_D PORTFIO_MASKA
200#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
201#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
202#define FIO_MASKA_C PORTFIO_MASKA_CLEAR
203#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
204#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
205#define FIO_MASKA_S PORTFIO_MASKA_SET
206#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
207#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
208#define FIO_MASKA_T PORTFIO_MASKA_TOGGLE
209#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
210#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
211#define FIO_MASKB_D PORTFIO_MASKB
212#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
213#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
214#define FIO_MASKB_C PORTFIO_MASKB_CLEAR
215#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
216#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
217#define FIO_MASKB_S PORTFIO_MASKB_SET
218#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
219#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
220#define FIO_MASKB_T PORTFIO_MASKB_TOGGLE
221#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
222#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
223#define FIO_DIR PORTFIO_DIR
224#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
225#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
226#define FIO_POLAR PORTFIO_POLAR
227#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
228#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
229#define FIO_EDGE PORTFIO_EDGE
230#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
231#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
232#define FIO_BOTH PORTFIO_BOTH
233#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
234#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
235#define FIO_INEN PORTFIO_INEN
236#endif
237
238/* FIO USE PORT G*/
239#ifdef CONFIG_BF537_PORT_G
240#define bfin_read_PORT_FER() bfin_read_PORTG_FER()
241#define bfin_write_PORT_FER(val) bfin_write_PORTG_FER(val)
242#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
243#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
244#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
245#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
246#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
247#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
248#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
249#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
250#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
251#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
252#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
253#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
254#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
255#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
256#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
257#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
258#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
259#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
260#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
261#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
262#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
263#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
264#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
265#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
266#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
267#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
268#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
269#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
270#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
271#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
272#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
273#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
274#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
275#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
276
277#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
278#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
279#define FIO_FLAG_D PORTGIO
280#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
281#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
282#define FIO_FLAG_C PORTGIO_CLEAR
283#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
284#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
285#define FIO_FLAG_S PORTGIO_SET
286#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
287#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
288#define FIO_FLAG_T PORTGIO_TOGGLE
289#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
290#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
291#define FIO_MASKA_D PORTGIO_MASKA
292#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
293#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
294#define FIO_MASKA_C PORTGIO_MASKA_CLEAR
295#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
296#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
297#define FIO_MASKA_S PORTGIO_MASKA_SET
298#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
299#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
300#define FIO_MASKA_T PORTGIO_MASKA_TOGGLE
301#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
302#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
303#define FIO_MASKB_D PORTGIO_MASKB
304#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
305#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
306#define FIO_MASKB_C PORTGIO_MASKB_CLEAR
307#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
308#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
309#define FIO_MASKB_S PORTGIO_MASKB_SET
310#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
311#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
312#define FIO_MASKB_T PORTGIO_MASKB_TOGGLE
313#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
314#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
315#define FIO_DIR PORTGIO_DIR
316#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
317#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
318#define FIO_POLAR PORTGIO_POLAR
319#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
320#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
321#define FIO_EDGE PORTGIO_EDGE
322#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
323#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
324#define FIO_BOTH PORTGIO_BOTH
325#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
326#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
327#define FIO_INEN PORTGIO_INEN
328
329#endif
330
331/* FIO USE PORT H*/
332#ifdef CONFIG_BF537_PORT_H
333#define bfin_read_PORT_FER() bfin_read_PORTH_FER()
334#define bfin_write_PORT_FER(val) bfin_write_PORTH_FER(val)
335#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
336#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
337#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
338#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
339#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
340#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
341#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
342#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
343#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
344#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
345#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
346#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
347#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
348#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
349#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
350#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
351#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
352#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
353#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
354#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
355#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
356#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
357#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
358#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
359#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
360#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
361#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
362#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
363#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
364#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
365#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
366#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
367#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
368#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
369
370#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
371#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
372#define FIO_FLAG_D PORTHIO
373#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
374#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
375#define FIO_FLAG_C PORTHIO_CLEAR
376#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
377#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
378#define FIO_FLAG_S PORTHIO_SET
379#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
380#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
381#define FIO_FLAG_T PORTHIO_TOGGLE
382#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
383#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
384#define FIO_MASKA_D PORTHIO_MASKA
385#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
386#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
387#define FIO_MASKA_C PORTHIO_MASKA_CLEAR
388#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
389#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
390#define FIO_MASKA_S PORTHIO_MASKA_SET
391#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
392#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
393#define FIO_MASKA_T PORTHIO_MASKA_TOGGLE
394#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
395#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
396#define FIO_MASKB_D PORTHIO_MASKB
397#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
398#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
399#define FIO_MASKB_C PORTHIO_MASKB_CLEAR
400#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
401#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
402#define FIO_MASKB_S PORTHIO_MASKB_SET
403#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
404#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
405#define FIO_MASKB_T PORTHIO_MASKB_TOGGLE
406#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
407#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
408#define FIO_DIR PORTHIO_DIR
409#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
410#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
411#define FIO_POLAR PORTHIO_POLAR
412#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
413#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
414#define FIO_EDGE PORTHIO_EDGE
415#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
416#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
417#define FIO_BOTH PORTHIO_BOTH
418#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
419#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
420#define FIO_INEN PORTHIO_INEN
421
422#endif
423
424/* PLL_DIV Masks */
425#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
426#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
427#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
428#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
429
430#endif
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
new file mode 100644
index 000000000000..7b658c175f85
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -0,0 +1,1823 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefbf534.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF534_H
33#define _CDEF_BF534_H
34
35/* Include all Core registers and bit definitions */
36#include "defBF534.h"
37
38/* Include core specific register pointer definitions */
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41#include <asm/system.h>
42
43/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
44#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
45#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
46#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
47#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
48#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
49/* Writing to VR_CTL initiates a PLL relock sequence. */
50static __inline__ void bfin_write_VR_CTL(unsigned int val)
51{
52 unsigned long flags, iwr;
53
54 bfin_write16(VR_CTL, val);
55 __builtin_bfin_ssync();
56 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr = bfin_read32(SIC_IWR);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR, IWR_ENABLE(0));
60 local_irq_save(flags);
61 asm("IDLE;");
62 local_irq_restore(flags);
63 bfin_write32(SIC_IWR, iwr);
64}
65#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
66#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
67#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
68#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
69#define bfin_read_CHIPID() bfin_read32(CHIPID)
70
71/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
72#define bfin_read_SWRST() bfin_read16(SWRST)
73#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
74#define bfin_read_SYSCR() bfin_read16(SYSCR)
75#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
76#define pSIC_RVECT ((void * volatile *)SIC_RVECT)
77#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
78#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
79#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
80#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
81#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
82#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
83#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
84#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
85#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
86#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
87#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
88#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
89#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
90#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
91#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
92#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
93
94/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
95#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
96#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
97#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
98#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
99#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
100#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
101
102/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
103#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
104#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
105#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
106#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
107#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
108#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
109#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
110#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
111#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
112#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
113#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
114#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
115#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
116#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
117
118/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
119#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
120#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
121#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
122#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
123#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
124#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
125#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
126#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
127#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
128#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
129#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
130#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
131#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
132#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
133#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
134#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
135#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
136#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
137#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
138#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
139#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
140#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
141#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
142#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
143
144/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
145#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
146#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
147#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
148#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
149#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
150#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
151#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
152#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
153#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
154#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
155#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
156#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
157#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
158#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
159
160/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
161#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
162#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
163#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
164#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
165#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
166#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
167#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
168#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
169
170#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
171#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
172#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
173#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
174#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
175#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
176#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
177#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
178
179#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
180#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
181#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
182#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
183#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
184#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
185#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
186#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
187
188#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
189#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
190#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
191#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
192#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
193#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
194#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
195#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
196
197#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
198#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
199#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
200#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
201#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
202#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
203#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
204#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
205
206#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
207#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
208#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
209#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
210#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
211#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
212#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
213#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
214
215#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
216#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
217#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
218#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
219#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
220#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
221#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
222#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
223
224#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
225#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
226#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
227#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
228#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
229#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
230#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
231#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
232
233#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
234#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
235#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
236#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
237#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
238#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val)
239
240/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
241#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
242#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val)
243#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
244#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val)
245#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
246#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val)
247#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
248#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val)
249#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
250#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val)
251#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
252#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val)
253#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
254#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val)
255#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
256#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
257#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
258#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val)
259#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
260#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val)
261#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
262#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val)
263#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
264#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
265#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
266#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val)
267#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
268#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val)
269#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
270#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val)
271#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
272#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val)
273#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
274#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val)
275
276/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
277#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
278#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
279#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
280#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
281#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
282#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
283#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
284#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
285#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
286#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
287#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
288#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
289#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
290#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
291#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
292#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
293#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
294#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
295#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
296#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
297#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
298#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
299#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
300#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
301#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
302#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
303#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
304#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
305#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
306#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
307#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
308#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
309#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
310#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
311#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
312#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
313#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
314#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
315#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
316#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
317#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
318#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
319#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
320#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
321#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
322#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
323#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
324#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
325#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
326#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
327#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
328#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
329
330/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
331#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
332#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
333#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
334#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
335#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
336#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
337#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
338#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
339#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
340#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
341#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
342#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
343#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
344#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
345#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
346#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
347#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
348#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
349#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
350#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
351#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
352#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
353#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
354#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
355#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
356#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
357#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
358#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
359#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
360#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
361#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
362#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
363#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
364#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
365#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
366#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
367#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
368#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
369#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
370#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
371#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
372#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
373#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
374#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
375#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
376#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
377#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
378#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
379#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
380#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
381#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
382#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
383
384/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
385#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
386#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
387#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
388#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
389#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
390#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
391#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
392#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
393#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
394#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
395#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
396#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
397#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
398#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
399
400/* DMA Traffic Control Registers */
401#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
402#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
403#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
404#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
405#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
406#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
407
408/* DMA Controller */
409#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
410#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
411#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
412#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
413#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
414#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
415#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
416#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
417#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
418#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
419#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
420#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
421#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
422#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
423#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
424#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
425#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
426#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
427#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
428#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
429#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
430#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
431#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
432#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
433#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
434#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
435
436#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
437#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
438#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
439#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
440#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
441#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
442#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
443#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
444#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
445#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
446#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
447#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
448#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
449#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
450#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
451#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
452#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
453#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
454#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
455#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
456#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
457#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
458#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
459#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
460#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
461#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
462
463#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
464#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
465#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
466#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
467#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
468#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
469#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
470#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
471#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
472#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
473#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
474#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
475#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
476#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
477#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
478#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
479#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
480#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
481#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
482#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
483#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
484#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
485#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
486#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
487#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
488#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
489
490#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
491#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
492#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
493#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
494#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
495#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
496#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
497#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
498#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
499#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
500#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
501#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
502#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
503#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
504#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
505#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
506#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
507#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
508#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
509#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
510#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
511#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
512#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
513#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
514#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
515#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
516
517#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
518#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
519#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
520#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
521#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
522#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
523#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
524#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
525#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
526#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
527#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
528#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
529#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
530#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
531#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
532#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
533#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
534#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
535#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
536#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
537#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
538#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
539#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
540#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
541#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
542#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
543
544#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
545#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
546#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
547#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
548#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
549#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
550#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
551#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
552#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
553#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
554#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
555#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
556#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
557#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
558#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
559#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
560#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
561#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
562#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
563#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
564#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
565#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
566#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
567#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
568#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
569#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
570
571#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
572#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
573#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
574#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
575#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
576#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
577#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
578#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
579#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
580#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
581#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
582#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
583#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
584#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
585#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
586#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
587#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
588#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
589#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
590#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
591#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
592#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
593#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
594#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
595#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
596#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
597
598#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
599#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
600#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
601#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
602#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
603#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
604#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
605#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
606#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
607#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
608#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
609#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
610#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
611#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
612#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
613#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
614#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
615#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
616#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
617#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
618#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
619#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
620#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
621#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
622#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
623#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
624
625#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
626#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
627#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
628#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
629#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
630#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
631#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
632#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
633#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
634#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
635#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
636#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
637#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
638#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
639#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
640#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
641#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
642#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
643#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
644#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
645#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
646#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
647#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
648#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
649#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
650#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
651
652#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
653#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
654#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
655#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
656#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
657#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
658#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
659#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
660#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
661#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
662#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
663#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
664#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
665#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
666#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
667#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val)
668#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
669#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val)
670#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
671#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val)
672#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
673#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val)
674#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
675#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val)
676#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
677#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val)
678
679#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
680#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val)
681#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
682#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val)
683#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
684#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val)
685#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
686#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val)
687#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
688#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val)
689#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
690#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val)
691#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
692#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val)
693#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
694#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val)
695#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
696#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val)
697#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
698#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val)
699#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
700#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val)
701#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
702#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
703#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
704#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
705
706#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
707#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val)
708#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
709#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val)
710#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
711#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val)
712#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
713#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val)
714#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
715#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val)
716#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
717#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val)
718#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
719#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val)
720#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
721#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val)
722#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
723#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val)
724#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
725#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val)
726#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
727#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val)
728#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
729#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val)
730#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
731#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
732
733#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
734#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
735#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
736#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
737#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
738#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
739#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
740#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
741#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
742#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
743#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
744#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
745#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
746#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
747#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
748#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
749#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
750#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
751#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
752#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
753#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
754#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
755#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
756#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
757#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
758#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
759
760#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
761#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
762#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
763#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
764#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
765#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
766#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
767#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
768#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
769#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
770#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
771#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
772#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
773#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
774#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
775#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
776#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
777#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
778#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
779#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
780#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
781#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
782#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
783#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
784#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
785#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
786
787#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
788#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
789#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
790#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
791#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
792#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
793#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
794#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
795#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
796#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
797#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
798#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
799#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
800#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
801#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
802#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
803#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
804#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
805#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
806#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
807#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
808#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
809#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
810#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
811#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
812#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
813
814#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
815#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
816#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
817#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
818#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
819#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
820#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
821#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
822#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
823#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
824#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
825#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
826#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
827#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
828#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
829#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
830#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
831#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
832#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
833#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
834#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
835#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
836#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
837#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
838#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
839#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
840
841/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
842#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
843#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
844#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
845#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
846#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
847#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
848#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
849#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
850#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
851#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
852#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
853
854/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
855#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
856#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
857#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
858#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
859#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
860#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
861#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
862#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
863#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
864#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
865#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
866#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
867#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
868#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
869#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
870#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
871#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
872#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
873#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
874#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
875#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
876#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
877#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
878#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
879#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
880#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
881#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
882#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
883#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
884#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
885#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
886#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
887
888/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
889#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
890#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val)
891#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
892#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val)
893#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
894#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val)
895#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
896#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val)
897#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
898#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val)
899#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
900#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val)
901#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
902#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val)
903#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
904#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
905#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
906#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val)
907#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
908#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val)
909#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
910#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val)
911#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
912#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
913#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
914#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val)
915#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
916#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val)
917#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
918#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val)
919#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
920#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val)
921#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
922#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val)
923
924/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
925#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
926#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val)
927#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
928#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val)
929#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
930#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val)
931#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
932#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val)
933#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
934#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val)
935#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
936#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val)
937#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
938#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val)
939#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
940#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
941#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
942#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val)
943#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
944#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val)
945#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
946#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val)
947#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
948#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
949#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
950#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val)
951#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
952#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val)
953#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
954#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val)
955#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
956#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val)
957#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
958#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val)
959
960/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
961#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
962#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
963#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
964#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val)
965#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
966#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val)
967#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
968#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val)
969#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
970#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val)
971#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
972#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val)
973#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
974#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val)
975#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
976#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val)
977#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
978#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val)
979#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
980#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val)
981#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
982#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val)
983#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
984#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val)
985
986/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
987/* For Mailboxes 0-15 */
988#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
989#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val)
990#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
991#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val)
992#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
993#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val)
994#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
995#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val)
996#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
997#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val)
998#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
999#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val)
1000#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
1001#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val)
1002#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
1003#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val)
1004#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
1005#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val)
1006#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
1007#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val)
1008#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
1009#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val)
1010#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
1011#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val)
1012#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
1013#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val)
1014
1015/* For Mailboxes 16-31 */
1016#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
1017#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val)
1018#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
1019#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val)
1020#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
1021#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val)
1022#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
1023#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val)
1024#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
1025#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val)
1026#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
1027#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val)
1028#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
1029#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val)
1030#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
1031#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val)
1032#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
1033#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val)
1034#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
1035#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val)
1036#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
1037#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val)
1038#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
1039#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val)
1040#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
1041#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val)
1042
1043#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
1044#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val)
1045#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
1046#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val)
1047#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
1048#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val)
1049#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
1050#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val)
1051#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
1052#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val)
1053#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
1054#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val)
1055#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
1056#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val)
1057#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
1058#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val)
1059#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
1060#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val)
1061#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
1062#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val)
1063#define bfin_read_CAN_SFCMVER() bfin_read16(CAN_SFCMVER)
1064#define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val)
1065#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
1066#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val)
1067#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
1068#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val)
1069#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
1070#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val)
1071#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
1072#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val)
1073#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
1074#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val)
1075#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
1076#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
1077#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
1078#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
1079#define bfin_read_CAN_SFCMVER2() bfin_read16(CAN_SFCMVER2)
1080#define bfin_write_CAN_SFCMVER2(val) bfin_write16(CAN_SFCMVER2,val)
1081
1082/* Mailbox Acceptance Masks */
1083#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
1084#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val)
1085#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
1086#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val)
1087#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
1088#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val)
1089#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
1090#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val)
1091#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
1092#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val)
1093#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
1094#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val)
1095#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
1096#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val)
1097#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
1098#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val)
1099#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
1100#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val)
1101#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
1102#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val)
1103#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
1104#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val)
1105#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
1106#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val)
1107#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
1108#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val)
1109#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
1110#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val)
1111#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
1112#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val)
1113#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
1114#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val)
1115#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
1116#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val)
1117#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
1118#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val)
1119#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
1120#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val)
1121#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
1122#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val)
1123#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
1124#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val)
1125#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
1126#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val)
1127#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
1128#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val)
1129#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
1130#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val)
1131#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
1132#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val)
1133#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
1134#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val)
1135#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
1136#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val)
1137#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
1138#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val)
1139#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
1140#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val)
1141#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
1142#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val)
1143#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
1144#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val)
1145#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
1146#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val)
1147
1148#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
1149#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val)
1150#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
1151#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val)
1152#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
1153#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val)
1154#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
1155#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val)
1156#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
1157#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val)
1158#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
1159#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val)
1160#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
1161#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val)
1162#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
1163#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val)
1164#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
1165#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val)
1166#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
1167#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val)
1168#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
1169#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val)
1170#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
1171#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val)
1172#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
1173#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val)
1174#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
1175#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val)
1176#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
1177#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val)
1178#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
1179#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val)
1180#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
1181#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val)
1182#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
1183#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val)
1184#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
1185#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val)
1186#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
1187#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val)
1188#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
1189#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val)
1190#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
1191#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val)
1192#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
1193#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val)
1194#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
1195#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val)
1196#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
1197#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val)
1198#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
1199#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val)
1200#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
1201#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val)
1202#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
1203#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val)
1204#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
1205#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val)
1206#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
1207#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val)
1208#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
1209#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val)
1210#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
1211#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val)
1212
1213/* CAN Acceptance Mask Area Macros */
1214#define bfin_read_CAN_AM_L(x)() bfin_read16(CAN_AM_L(x))
1215#define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val)
1216#define bfin_read_CAN_AM_H(x)() bfin_read16(CAN_AM_H(x))
1217#define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val)
1218
1219/* Mailbox Registers */
1220#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
1221#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val)
1222#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
1223#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val)
1224#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
1225#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val)
1226#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
1227#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val)
1228#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
1229#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val)
1230#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
1231#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val)
1232#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
1233#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val)
1234#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
1235#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val)
1236
1237#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
1238#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val)
1239#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
1240#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val)
1241#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
1242#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val)
1243#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
1244#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val)
1245#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
1246#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val)
1247#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
1248#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val)
1249#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
1250#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val)
1251#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
1252#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val)
1253
1254#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
1255#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val)
1256#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
1257#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val)
1258#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
1259#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val)
1260#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
1261#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val)
1262#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
1263#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val)
1264#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
1265#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val)
1266#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
1267#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val)
1268#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
1269#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val)
1270
1271#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
1272#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val)
1273#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
1274#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val)
1275#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
1276#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val)
1277#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
1278#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val)
1279#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
1280#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val)
1281#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
1282#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val)
1283#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
1284#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val)
1285#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
1286#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val)
1287
1288#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
1289#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val)
1290#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
1291#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val)
1292#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
1293#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val)
1294#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
1295#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val)
1296#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
1297#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val)
1298#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
1299#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val)
1300#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
1301#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val)
1302#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
1303#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val)
1304
1305#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
1306#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val)
1307#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
1308#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val)
1309#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
1310#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val)
1311#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
1312#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val)
1313#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
1314#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val)
1315#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
1316#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val)
1317#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
1318#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val)
1319#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
1320#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val)
1321
1322#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
1323#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val)
1324#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
1325#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val)
1326#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
1327#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val)
1328#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
1329#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val)
1330#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
1331#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val)
1332#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
1333#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val)
1334#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
1335#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val)
1336#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
1337#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val)
1338
1339#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
1340#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val)
1341#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
1342#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val)
1343#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
1344#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val)
1345#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
1346#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val)
1347#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
1348#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val)
1349#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
1350#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val)
1351#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
1352#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val)
1353#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
1354#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val)
1355
1356#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
1357#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val)
1358#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
1359#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val)
1360#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
1361#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val)
1362#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
1363#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val)
1364#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
1365#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val)
1366#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
1367#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val)
1368#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
1369#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val)
1370#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
1371#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val)
1372
1373#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
1374#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val)
1375#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
1376#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val)
1377#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
1378#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val)
1379#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
1380#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val)
1381#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
1382#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val)
1383#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
1384#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val)
1385#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
1386#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val)
1387#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
1388#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val)
1389
1390#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
1391#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val)
1392#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
1393#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val)
1394#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
1395#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val)
1396#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
1397#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val)
1398#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
1399#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val)
1400#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
1401#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val)
1402#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
1403#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val)
1404#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
1405#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val)
1406
1407#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
1408#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val)
1409#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
1410#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val)
1411#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
1412#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val)
1413#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
1414#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val)
1415#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
1416#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val)
1417#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
1418#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val)
1419#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
1420#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val)
1421#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
1422#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val)
1423
1424#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
1425#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val)
1426#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
1427#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val)
1428#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
1429#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val)
1430#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
1431#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val)
1432#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
1433#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val)
1434#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
1435#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val)
1436#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
1437#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val)
1438#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
1439#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val)
1440
1441#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
1442#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val)
1443#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
1444#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val)
1445#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
1446#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val)
1447#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
1448#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val)
1449#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
1450#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val)
1451#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
1452#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val)
1453#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
1454#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val)
1455#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
1456#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val)
1457
1458#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
1459#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val)
1460#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
1461#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val)
1462#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
1463#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val)
1464#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
1465#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val)
1466#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
1467#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val)
1468#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
1469#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val)
1470#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
1471#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val)
1472#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
1473#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val)
1474
1475#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
1476#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val)
1477#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
1478#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val)
1479#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
1480#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val)
1481#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
1482#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val)
1483#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
1484#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val)
1485#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
1486#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val)
1487#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
1488#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val)
1489#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
1490#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val)
1491
1492#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
1493#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val)
1494#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
1495#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val)
1496#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
1497#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val)
1498#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
1499#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val)
1500#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
1501#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val)
1502#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
1503#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val)
1504#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
1505#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val)
1506#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
1507#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val)
1508
1509#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
1510#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val)
1511#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
1512#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val)
1513#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
1514#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val)
1515#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
1516#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val)
1517#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
1518#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val)
1519#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
1520#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val)
1521#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
1522#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val)
1523#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
1524#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val)
1525
1526#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
1527#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val)
1528#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
1529#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val)
1530#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
1531#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val)
1532#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
1533#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val)
1534#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
1535#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val)
1536#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
1537#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val)
1538#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
1539#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val)
1540#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
1541#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val)
1542
1543#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
1544#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val)
1545#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
1546#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val)
1547#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
1548#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val)
1549#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
1550#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val)
1551#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
1552#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val)
1553#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
1554#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val)
1555#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
1556#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val)
1557#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
1558#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val)
1559
1560#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
1561#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val)
1562#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
1563#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val)
1564#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
1565#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val)
1566#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
1567#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val)
1568#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
1569#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val)
1570#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
1571#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val)
1572#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
1573#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val)
1574#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
1575#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val)
1576
1577#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
1578#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val)
1579#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
1580#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val)
1581#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
1582#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val)
1583#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
1584#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val)
1585#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
1586#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val)
1587#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
1588#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val)
1589#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
1590#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val)
1591#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
1592#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val)
1593
1594#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
1595#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val)
1596#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
1597#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val)
1598#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
1599#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val)
1600#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
1601#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val)
1602#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
1603#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val)
1604#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
1605#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val)
1606#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
1607#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val)
1608#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
1609#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val)
1610
1611#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
1612#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val)
1613#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
1614#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val)
1615#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
1616#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val)
1617#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
1618#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val)
1619#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
1620#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val)
1621#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
1622#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val)
1623#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
1624#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val)
1625#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
1626#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val)
1627
1628#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
1629#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val)
1630#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
1631#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val)
1632#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
1633#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val)
1634#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
1635#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val)
1636#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
1637#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val)
1638#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
1639#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val)
1640#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
1641#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val)
1642#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
1643#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val)
1644
1645#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
1646#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val)
1647#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
1648#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val)
1649#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
1650#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val)
1651#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
1652#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val)
1653#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
1654#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val)
1655#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
1656#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val)
1657#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
1658#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val)
1659#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
1660#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val)
1661
1662#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
1663#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val)
1664#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
1665#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val)
1666#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
1667#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val)
1668#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
1669#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val)
1670#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
1671#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val)
1672#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
1673#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val)
1674#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
1675#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val)
1676#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
1677#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val)
1678
1679#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
1680#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val)
1681#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
1682#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val)
1683#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
1684#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val)
1685#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
1686#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val)
1687#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
1688#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val)
1689#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
1690#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val)
1691#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
1692#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val)
1693#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
1694#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val)
1695
1696#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
1697#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val)
1698#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
1699#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val)
1700#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
1701#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val)
1702#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
1703#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val)
1704#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
1705#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val)
1706#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
1707#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val)
1708#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
1709#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val)
1710#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
1711#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val)
1712
1713#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
1714#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val)
1715#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
1716#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val)
1717#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
1718#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val)
1719#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
1720#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val)
1721#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
1722#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val)
1723#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
1724#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val)
1725#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
1726#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val)
1727#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
1728#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val)
1729
1730#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
1731#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val)
1732#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
1733#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val)
1734#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
1735#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val)
1736#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
1737#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val)
1738#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
1739#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val)
1740#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
1741#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val)
1742#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
1743#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val)
1744#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
1745#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val)
1746
1747#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
1748#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val)
1749#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
1750#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val)
1751#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
1752#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val)
1753#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
1754#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val)
1755#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
1756#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val)
1757#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
1758#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val)
1759#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
1760#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val)
1761#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
1762#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val)
1763
1764/* CAN Mailbox Area Macros */
1765#define bfin_read_CAN_MB_ID1(x)() bfin_read16(CAN_MB_ID1(x))
1766#define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val)
1767#define bfin_read_CAN_MB_ID0(x)() bfin_read16(CAN_MB_ID0(x))
1768#define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val)
1769#define bfin_read_CAN_MB_TIMESTAMP(x)() bfin_read16(CAN_MB_TIMESTAMP(x))
1770#define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val)
1771#define bfin_read_CAN_MB_LENGTH(x)() bfin_read16(CAN_MB_LENGTH(x))
1772#define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val)
1773#define bfin_read_CAN_MB_DATA3(x)() bfin_read16(CAN_MB_DATA3(x))
1774#define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val)
1775#define bfin_read_CAN_MB_DATA2(x)() bfin_read16(CAN_MB_DATA2(x))
1776#define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val)
1777#define bfin_read_CAN_MB_DATA1(x)() bfin_read16(CAN_MB_DATA1(x))
1778#define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val)
1779#define bfin_read_CAN_MB_DATA0(x)() bfin_read16(CAN_MB_DATA0(x))
1780#define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val)
1781
1782/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
1783#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1784#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val)
1785#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1786#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val)
1787#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1788#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val)
1789#define bfin_read_PORT_MUX() bfin_read16(BFIN_PORT_MUX)
1790#define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val)
1791
1792/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
1793#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1794#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val)
1795#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1796#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val)
1797#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1798#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val)
1799#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1800#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val)
1801#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1802#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val)
1803#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1804#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val)
1805#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1806#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val)
1807
1808#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1809#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val)
1810#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1811#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val)
1812#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1813#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val)
1814#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1815#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val)
1816#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1817#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val)
1818#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1819#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val)
1820#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1821#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
1822
1823#endif /* _CDEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF537.h b/include/asm-blackfin/mach-bf537/cdefBF537.h
new file mode 100644
index 000000000000..932a1b6b5d14
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/cdefBF537.h
@@ -0,0 +1,209 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefBF537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 * System MMR Register Map
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF537_H
33#define _CDEF_BF537_H
34
35/* Include MMRs Common to BF534 */
36#include "cdefBF534.h"
37
38/* Include all Core registers and bit definitions */
39#include "defBF537.h"
40
41/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
42/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
43#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
44#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
45#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
46#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
47#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
48#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
49#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
50#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
51#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
52#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
53#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
54#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
55#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
56#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
57#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
58#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
59#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
60#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
61#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
62#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
63#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
64#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
65#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val)
66#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
67#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val)
68#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
69#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val)
70#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
71#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val)
72#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
73#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val)
74#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
75#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val)
76#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
77#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val)
78#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
79#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val)
80#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
81#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
82
83#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
84#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
85#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
86#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
87#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val)
88#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
89#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val)
90#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
91#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val)
92#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
93#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val)
94#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
95#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val)
96#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
97#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val)
98#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
99#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val)
100
101#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
102#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val)
103#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
104#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val)
105#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
106#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val)
107#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
108#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
109#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
110#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val)
111
112#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
113#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val)
114#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
115#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val)
116#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
117#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val)
118#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
119#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val)
120#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
121#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val)
122#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
123#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val)
124#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
125#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val)
126#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
127#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val)
128#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
129#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val)
130#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
131#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val)
132#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
133#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val)
134#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
135#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val)
136#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
137#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val)
138#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
139#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val)
140#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
141#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val)
142#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
143#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val)
144#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
145#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val)
146#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
147#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
148#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
149#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
150#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
151#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
152#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
153#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
154#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val)
155#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
156#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val)
157#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
158#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val)
159#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
160#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val)
161
162#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
163#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val)
164#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
165#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val)
166#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
167#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val)
168#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
169#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val)
170#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
171#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val)
172#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
173#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val)
174#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
175#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val)
176#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
177#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val)
178#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
179#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val)
180#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
181#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val)
182#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
183#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val)
184#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
185#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val)
186#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
187#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val)
188#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
189#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val)
190#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
191#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val)
192#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
193#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val)
194#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
195#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val)
196#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
197#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val)
198#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
199#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val)
200#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
201#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val)
202#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
203#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val)
204#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
205#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val)
206#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
207#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val)
208
209#endif /* _CDEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
new file mode 100644
index 000000000000..e605e9709004
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -0,0 +1,2501 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefBF537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF534_H
32#define _DEF_BF534_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/************************************************************************************
38** System MMR Register Map
39*************************************************************************************/
40/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
41#define PLL_CTL 0xFFC00000 /* PLL Control Register */
42#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
43#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
44#define PLL_STAT 0xFFC0000C /* PLL Status Register */
45#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
46#define CHIPID 0xFFC00014 /* Chip ID Register */
47
48/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
49#define SWRST 0xFFC00100 /* Software Reset Register */
50#define SYSCR 0xFFC00104 /* System Configuration Register */
51#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
52#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
53#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
54#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
55#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
56#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
57#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
58#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
59
60/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
61#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
62#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
63#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
64
65/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
66#define RTC_STAT 0xFFC00300 /* RTC Status Register */
67#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
68#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
69#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
70#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
71#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
72#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
73
74/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
75#define UART0_THR 0xFFC00400 /* Transmit Holding register */
76#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
77#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
78#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
79#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
80#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
81#define UART0_LCR 0xFFC0040C /* Line Control Register */
82#define UART0_MCR 0xFFC00410 /* Modem Control Register */
83#define UART0_LSR 0xFFC00414 /* Line Status Register */
84#define UART0_MSR 0xFFC00418 /* Modem Status Register */
85#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
86#define UART0_GCTL 0xFFC00424 /* Global Control Register */
87
88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
89#define SPI_CTL 0xFFC00500 /* SPI Control Register */
90#define SPI_FLG 0xFFC00504 /* SPI Flag register */
91#define SPI_STAT 0xFFC00508 /* SPI Status register */
92#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
93#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
94#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
95#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
96
97/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
98#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
99#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
100#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
101#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
102
103#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
104#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
105#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
106#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
107
108#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
109#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
110#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
111#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
112
113#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
114#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
115#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
116#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
117
118#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
119#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
120#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
121#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
122
123#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
124#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
125#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
126#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
127
128#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
129#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
130#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
131#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
132
133#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
134#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
135#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
136#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
137
138#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
139#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
140#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
141
142/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
143#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
144#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
145#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
146#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
147#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
148#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
149#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
150#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
151#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
152#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
153#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
154#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
155#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
156#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
157#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
158#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
159#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
160
161/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
162#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
163#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
164#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
165#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
166#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
167#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
168#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
169#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
170#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
171#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
172#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
173#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
174#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
175#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
176#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
177#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
178#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
179#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
180#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
181#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
182#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
183#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
184
185/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
186#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
187#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
188#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
189#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
190#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
191#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
192#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
193#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
194#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
195#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
196#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
197#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
198#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
199#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
200#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
201#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
202#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
203#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
204#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
205#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
206#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
207#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
208
209/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
210#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
211#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
212#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
213#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
214#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
215#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
216#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
217
218/* DMA Traffic Control Registers */
219#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
220#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
221
222/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
223#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
224#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
225#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
226#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
227#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
228#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
229#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
230#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
231#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
232#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
233#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
234#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
235#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
236
237#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
238#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
239#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
240#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
241#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
242#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
243#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
244#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
245#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
246#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
247#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
248#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
249#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
250
251#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
252#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
253#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
254#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
255#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
256#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
257#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
258#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
259#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
260#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
261#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
262#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
263#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
264
265#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
266#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
267#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
268#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
269#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
270#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
271#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
272#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
273#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
274#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
275#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
276#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
277#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
278
279#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
280#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
281#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
282#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
283#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
284#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
285#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
286#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
287#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
288#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
289#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
290#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
291#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
292
293#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
294#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
295#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
296#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
297#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
298#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
299#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
300#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
301#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
302#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
303#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
304#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
305#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
306
307#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
308#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
309#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
310#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
311#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
312#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
313#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
314#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
315#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
316#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
317#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
318#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
319#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
320
321#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
322#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
323#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
324#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
325#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
326#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
327#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
328#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
329#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
330#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
331#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
332#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
333#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
334
335#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
336#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
337#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
338#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
339#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
340#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
341#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
342#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
343#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
344#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
345#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
346#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
347#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
348
349#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
350#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
351#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
352#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
353#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
354#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
355#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
356#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
357#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
358#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
359#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
360#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
361#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
362
363#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
364#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
365#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
366#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
367#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
368#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
369#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
370#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
371#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
372#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
373#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
374#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
375#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
376
377#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
378#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
379#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
380#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
381#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
382#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
383#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
384#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
385#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
386#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
387#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
388#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
389#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
390
391#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
392#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
393#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
394#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
395#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
396#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
397#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
398#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
399#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
400#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
401#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
402#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
403#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
404
405#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
406#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
407#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
408#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
409#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
410#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
411#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
412#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
413#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
414#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
415#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
416#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
417#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
418
419#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
420#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
421#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
422#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
423#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
424#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
425#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
426#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
427#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
428#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
429#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
430#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
431#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
432
433#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
434#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
435#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
436#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
437#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
438#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
439#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
440#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
441#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
442#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
443#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
444#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
445#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
446
447/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
448#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
449#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
450#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
451#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
452#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
453
454/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
455#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
456#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
457#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
458#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
459#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
460#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
461#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
462#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
463#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
464#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
465#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
466#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
467#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
468#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
469#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
470#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
471
472/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
473#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
474#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
475#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
476#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
477#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
478#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
479#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
480#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
481#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
482#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
483#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
484#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
485#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
486#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
487#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
488#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
489#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
490
491/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
492#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
493#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
494#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
495#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
496#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
497#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
498#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
499#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
500#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
501#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
502#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
503#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
504#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
505#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
506#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
507#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
508#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
509
510/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
511#define UART1_THR 0xFFC02000 /* Transmit Holding register */
512#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
513#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
514#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
515#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
516#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
517#define UART1_LCR 0xFFC0200C /* Line Control Register */
518#define UART1_MCR 0xFFC02010 /* Modem Control Register */
519#define UART1_LSR 0xFFC02014 /* Line Status Register */
520#define UART1_MSR 0xFFC02018 /* Modem Status Register */
521#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
522#define UART1_GCTL 0xFFC02024 /* Global Control Register */
523
524/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
525/* For Mailboxes 0-15 */
526#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
527#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
528#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
529#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
530#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
531#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
532#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
533#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
534#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
535#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
536#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
537#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
538#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
539
540/* For Mailboxes 16-31 */
541#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
542#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
543#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
544#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
545#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
546#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
547#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
548#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
549#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
550#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
551#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
552#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
553#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
554
555/* CAN Configuration, Control, and Status Registers */
556#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
557#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
558#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
559#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
560#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
561#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
562#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
563#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
564#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
565#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
566#define CAN_SFCMVER 0xFFC02AA8 /* Version Code Register */
567#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
568#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
569#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
570#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
571#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
572#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
573#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
574
575/* Mailbox Acceptance Masks */
576#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
577#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
578#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
579#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
580#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
581#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
582#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
583#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
584#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
585#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
586#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
587#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
588#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
589#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
590#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
591#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
592#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
593#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
594#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
595#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
596#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
597#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
598#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
599#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
600#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
601#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
602#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
603#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
604#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
605#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
606#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
607#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
608
609#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
610#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
611#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
612#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
613#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
614#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
615#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
616#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
617#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
618#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
619#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
620#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
621#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
622#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
623#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
624#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
625#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
626#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
627#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
628#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
629#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
630#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
631#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
632#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
633#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
634#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
635#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
636#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
637#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
638#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
639#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
640#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
641
642/* CAN Acceptance Mask Macros */
643#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
644#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
645
646/* Mailbox Registers */
647#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
648#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
649#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
650#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
651#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
652#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
653#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
654#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
655
656#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
657#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
658#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
659#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
660#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
661#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
662#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
663#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
664
665#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
666#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
667#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
668#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
669#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
670#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
671#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
672#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
673
674#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
675#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
676#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
677#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
678#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
679#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
680#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
681#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
682
683#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
684#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
685#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
686#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
687#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
688#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
689#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
690#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
691
692#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
693#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
694#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
695#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
696#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
697#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
698#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
699#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
700
701#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
702#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
703#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
704#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
705#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
706#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
707#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
708#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
709
710#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
711#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
712#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
713#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
714#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
715#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
716#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
717#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
718
719#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
720#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
721#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
722#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
723#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
724#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
725#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
726#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
727
728#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
729#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
730#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
731#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
732#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
733#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
734#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
735#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
736
737#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
738#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
739#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
740#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
741#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
742#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
743#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
744#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
745
746#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
747#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
748#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
749#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
750#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
751#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
752#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
753#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
754
755#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
756#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
757#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
758#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
759#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
760#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
761#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
762#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
763
764#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
765#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
766#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
767#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
768#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
769#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
770#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
771#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
772
773#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
774#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
775#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
776#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
777#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
778#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
779#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
780#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
781
782#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
783#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
784#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
785#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
786#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
787#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
788#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
789#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
790
791#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
792#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
793#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
794#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
795#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
796#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
797#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
798#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
799
800#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
801#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
802#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
803#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
804#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
805#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
806#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
807#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
808
809#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
810#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
811#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
812#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
813#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
814#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
815#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
816#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
817
818#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
819#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
820#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
821#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
822#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
823#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
824#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
825#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
826
827#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
828#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
829#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
830#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
831#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
832#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
833#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
834#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
835
836#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
837#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
838#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
839#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
840#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
841#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
842#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
843#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
844
845#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
846#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
847#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
848#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
849#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
850#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
851#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
852#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
853
854#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
855#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
856#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
857#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
858#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
859#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
860#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
861#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
862
863#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
864#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
865#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
866#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
867#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
868#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
869#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
870#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
871
872#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
873#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
874#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
875#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
876#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
877#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
878#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
879#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
880
881#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
882#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
883#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
884#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
885#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
886#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
887#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
888#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
889
890#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
891#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
892#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
893#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
894#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
895#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
896#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
897#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
898
899#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
900#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
901#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
902#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
903#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
904#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
905#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
906#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
907
908#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
909#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
910#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
911#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
912#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
913#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
914#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
915#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
916
917#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
918#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
919#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
920#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
921#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
922#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
923#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
924#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
925
926#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
927#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
928#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
929#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
930#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
931#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
932#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
933#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
934
935/* CAN Mailbox Area Macros */
936#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
937#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
938#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
939#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
940#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
941#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
942#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
943#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
944
945/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
946#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
947#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
948#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
949#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
950
951/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
952#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
953#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
954#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
955#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
956#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
957#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
958#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
959
960#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
961#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
962#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
963#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
964#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
965#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
966#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
967
968/***********************************************************************************
969** System MMR Register Bits And Macros
970**
971** Disclaimer: All macros are intended to make C and Assembly code more readable.
972** Use these macros carefully, as any that do left shifts for field
973** depositing will result in the lower order bits being destroyed. Any
974** macro that shifts left to properly position the bit-field should be
975** used as part of an OR to initialize a register and NOT as a dynamic
976** modifier UNLESS the lower order bits are saved and ORed back in when
977** the macro is used.
978*************************************************************************************/
979/*
980** ********************* PLL AND RESET MASKS ****************************************/
981/* PLL_CTL Masks */
982#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
983#define PLL_OFF 0x0002 /* PLL Not Powered */
984#define STOPCK 0x0008 /* Core Clock Off */
985#define PDWN 0x0020 /* Enter Deep Sleep Mode */
986#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
987#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
988#define BYPASS 0x0100 /* Bypass the PLL */
989#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
990/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
991#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
992
993/* PLL_DIV Masks */
994#define SSEL 0x000F /* System Select */
995#define CSEL 0x0030 /* Core Select */
996#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
997#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
998#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
999#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1000/* PLL_DIV Macros */
1001#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1002
1003/* VR_CTL Masks */
1004#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1005#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1006#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1007#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1008#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1009
1010#define GAIN 0x000C /* Voltage Level Gain */
1011#define GAIN_5 0x0000 /* GAIN = 5 */
1012#define GAIN_10 0x0004 /* GAIN = 10 */
1013#define GAIN_20 0x0008 /* GAIN = 20 */
1014#define GAIN_50 0x000C /* GAIN = 50 */
1015
1016#define VLEV 0x00F0 /* Internal Voltage Level */
1017#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
1018#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
1019#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
1020#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
1021#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
1022#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
1023#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
1024#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
1025#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
1026#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
1027
1028#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1029#define PHYWE 0x0200 /* Enable PHY Wakeup From Hibernate */
1030#define CANWE 0x0400 /* Enable CAN Wakeup From Hibernate */
1031#define PHYCLKOE 0x4000 /* PHY Clock Output Enable */
1032#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */
1033
1034/* PLL_STAT Masks */
1035#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1036#define FULL_ON 0x0002 /* Processor In Full On Mode */
1037#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1038#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1039
1040/* CHIPID Masks */
1041#define CHIPID_VERSION 0xF0000000
1042#define CHIPID_FAMILY 0x0FFFF000
1043#define CHIPID_MANUFACTURE 0x00000FFE
1044
1045/* SWRST Masks */
1046#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1047#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
1048#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
1049#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
1050#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1051
1052/* SYSCR Masks */
1053#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
1054#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1055
1056/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
1057
1058/* SIC_IAR0 Macros */
1059#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
1060#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
1061#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
1062#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
1063#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
1064#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
1065#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
1066#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
1067
1068/* SIC_IAR1 Macros */
1069#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
1070#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
1071#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
1072#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
1073#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
1074#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
1075#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
1076#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
1077
1078/* SIC_IAR2 Macros */
1079#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
1080#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
1081#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
1082#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
1083#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
1084#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
1085#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
1086#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
1087
1088/* SIC_IAR3 Macros */
1089#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
1090#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
1091#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
1092#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
1093#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
1094#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
1095#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
1096#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
1097
1098/* SIC_IMASK Masks */
1099#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1100#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1101#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1102#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
1103
1104/* SIC_IWR Masks */
1105#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1106#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1107#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1108#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1109
1110/* *************** WATCHDOG TIMER MASKS *******************************************/
1111/* WDOG_CTL Masks */
1112#define WDOG_RESET 0x0000 /* Generate Reset Event */
1113#define WDOG_NMI 0x0002 /* Generate Non-Maskable Interrupt (NMI) Event */
1114#define WDOG_GPI 0x0004 /* Generate General Purpose (GP) Interrupt */
1115#define WDOG_NONE 0x0006 /* Disable Watchdog Timer Interrupts */
1116#define TMR_EN 0x0FF0 /* Watchdog Counter Enable */
1117#define TMR_DIS 0x0AD0 /* Watchdog Counter Disable */
1118#define TRO 0x8000 /* Watchdog Expired */
1119
1120/* ************** UART CONTROLLER MASKS *************************/
1121/* UARTx_LCR Masks */
1122#define WLS(x) ((((x)&0x3)-5) & 0x03) /* Word Length Select */
1123#define STB 0x04 /* Stop Bits */
1124#define PEN 0x08 /* Parity Enable */
1125#define EPS 0x10 /* Even Parity Select */
1126#define STP 0x20 /* Stick Parity */
1127#define SB 0x40 /* Set Break */
1128#define DLAB 0x80 /* Divisor Latch Access */
1129
1130/* UARTx_MCR Mask */
1131#define LOOP 0x10 /* Loopback Mode Enable */
1132
1133/* UARTx_LSR Masks */
1134#define DR 0x01 /* Data Ready */
1135#define OE 0x02 /* Overrun Error */
1136#define PE 0x04 /* Parity Error */
1137#define FE 0x08 /* Framing Error */
1138#define BI 0x10 /* Break Interrupt */
1139#define THRE 0x20 /* THR Empty */
1140#define TEMT 0x40 /* TSR and UART_THR Empty */
1141
1142/* UARTx_IER Masks */
1143#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1144#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1145#define ELSI 0x04 /* Enable RX Status Interrupt */
1146
1147/* UARTx_IIR Masks */
1148#define NINT 0x01 /* Pending Interrupt */
1149#define IIR_TX_READY 0x02 /* UART_THR empty */
1150#define IIR_RX_READY 0x04 /* Receive data ready */
1151#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1152#define IIR_STATUS 0x06
1153
1154/* UARTx_GCTL Masks */
1155#define UCEN 0x01 /* Enable UARTx Clocks */
1156#define IREN 0x02 /* Enable IrDA Mode */
1157#define TPOLC 0x04 /* IrDA TX Polarity Change */
1158#define RPOLC 0x08 /* IrDA RX Polarity Change */
1159#define FPE 0x10 /* Force Parity Error On Transmit */
1160#define FFE 0x20 /* Force Framing Error On Transmit */
1161
1162/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
1163/* SPI_CTL Masks */
1164#define TIMOD 0x0003 /* Transfer Initiate Mode */
1165#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1166#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1167#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1168#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1169#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1170#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1171#define PSSE 0x0010 /* Slave-Select Input Enable */
1172#define EMISO 0x0020 /* Enable MISO As Output */
1173#define SPI_SIZE 0x0100 /* Size of Words (16/8* Bits) */
1174#define LSBF 0x0200 /* LSB First */
1175#define CPHA 0x0400 /* Clock Phase */
1176#define CPOL 0x0800 /* Clock Polarity */
1177#define MSTR 0x1000 /* Master/Slave* */
1178#define WOM 0x2000 /* Write Open Drain Master */
1179#define SPE 0x4000 /* SPI Enable */
1180
1181/* SPI_FLG Masks */
1182#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1183#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1184#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1185#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1186#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1187#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1188#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1189#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1190#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1191#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1192#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1193#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1194#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1195#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1196
1197/* SPI_STAT Masks */
1198#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1199#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1200#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1201#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
1202#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1203#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
1204#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1205
1206/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1207/* TIMER_ENABLE Masks */
1208#define TIMEN0 0x0001 /* Enable Timer 0 */
1209#define TIMEN1 0x0002 /* Enable Timer 1 */
1210#define TIMEN2 0x0004 /* Enable Timer 2 */
1211#define TIMEN3 0x0008 /* Enable Timer 3 */
1212#define TIMEN4 0x0010 /* Enable Timer 4 */
1213#define TIMEN5 0x0020 /* Enable Timer 5 */
1214#define TIMEN6 0x0040 /* Enable Timer 6 */
1215#define TIMEN7 0x0080 /* Enable Timer 7 */
1216
1217/* TIMER_DISABLE Masks */
1218#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
1219#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
1220#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
1221#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
1222#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
1223#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
1224#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
1225#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
1226
1227/* TIMER_STATUS Masks */
1228#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
1229#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
1230#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
1231#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
1232#define TOVL_ERR0 0x00000010 /* Timer 0 Counter Overflow */
1233#define TOVL_ERR1 0x00000020 /* Timer 1 Counter Overflow */
1234#define TOVL_ERR2 0x00000040 /* Timer 2 Counter Overflow */
1235#define TOVL_ERR3 0x00000080 /* Timer 3 Counter Overflow */
1236#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
1237#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
1238#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
1239#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
1240#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
1241#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
1242#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
1243#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
1244#define TOVL_ERR4 0x00100000 /* Timer 4 Counter Overflow */
1245#define TOVL_ERR5 0x00200000 /* Timer 5 Counter Overflow */
1246#define TOVL_ERR6 0x00400000 /* Timer 6 Counter Overflow */
1247#define TOVL_ERR7 0x00800000 /* Timer 7 Counter Overflow */
1248#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
1249#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
1250#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1251#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1252
1253/* TIMERx_CONFIG Masks */
1254#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1255#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
1256#define EXT_CLK 0x0003 /* External Clock Mode */
1257#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
1258#define PERIOD_CNT 0x0008 /* Period Count */
1259#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
1260#define TIN_SEL 0x0020 /* Timer Input Select */
1261#define OUT_DIS 0x0040 /* Output Pad Disable */
1262#define CLK_SEL 0x0080 /* Timer Clock Select */
1263#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1264#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1265#define ERR_TYP 0xC000 /* Error Type */
1266
1267/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1268/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1269/* Port F Masks */
1270#define PF0 0x0001
1271#define PF1 0x0002
1272#define PF2 0x0004
1273#define PF3 0x0008
1274#define PF4 0x0010
1275#define PF5 0x0020
1276#define PF6 0x0040
1277#define PF7 0x0080
1278#define PF8 0x0100
1279#define PF9 0x0200
1280#define PF10 0x0400
1281#define PF11 0x0800
1282#define PF12 0x1000
1283#define PF13 0x2000
1284#define PF14 0x4000
1285#define PF15 0x8000
1286
1287/* Port G Masks */
1288#define PG0 0x0001
1289#define PG1 0x0002
1290#define PG2 0x0004
1291#define PG3 0x0008
1292#define PG4 0x0010
1293#define PG5 0x0020
1294#define PG6 0x0040
1295#define PG7 0x0080
1296#define PG8 0x0100
1297#define PG9 0x0200
1298#define PG10 0x0400
1299#define PG11 0x0800
1300#define PG12 0x1000
1301#define PG13 0x2000
1302#define PG14 0x4000
1303#define PG15 0x8000
1304
1305/* Port H Masks */
1306#define PH0 0x0001
1307#define PH1 0x0002
1308#define PH2 0x0004
1309#define PH3 0x0008
1310#define PH4 0x0010
1311#define PH5 0x0020
1312#define PH6 0x0040
1313#define PH7 0x0080
1314#define PH8 0x0100
1315#define PH9 0x0200
1316#define PH10 0x0400
1317#define PH11 0x0800
1318#define PH12 0x1000
1319#define PH13 0x2000
1320#define PH14 0x4000
1321#define PH15 0x8000
1322
1323/* ******************* SERIAL PORT MASKS **************************************/
1324/* SPORTx_TCR1 Masks */
1325#define TSPEN 0x0001 /* Transmit Enable */
1326#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1327#define DTYPE_NORM 0x0004 /* Data Format Normal */
1328#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1329#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1330#define TLSBIT 0x0010 /* Transmit Bit Order */
1331#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1332#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1333#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1334#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1335#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1336#define TCKFE 0x4000 /* Clock Falling Edge Select */
1337
1338/* SPORTx_TCR2 Masks and Macro */
1339#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1340#define TXSE 0x0100 /* TX Secondary Enable */
1341#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1342#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1343
1344/* SPORTx_RCR1 Masks */
1345#define RSPEN 0x0001 /* Receive Enable */
1346#define IRCLK 0x0002 /* Internal Receive Clock Select */
1347#define DTYPE_NORM 0x0004 /* Data Format Normal */
1348#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1349#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1350#define RLSBIT 0x0010 /* Receive Bit Order */
1351#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1352#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1353#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1354#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1355#define RCKFE 0x4000 /* Clock Falling Edge Select */
1356
1357/* SPORTx_RCR2 Masks */
1358#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1359#define RXSE 0x0100 /* RX Secondary Enable */
1360#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1361#define RRFST 0x0400 /* Right-First Data Order */
1362
1363/* SPORTx_STAT Masks */
1364#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1365#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1366#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1367#define TXF 0x0008 /* Transmit FIFO Full Status */
1368#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1369#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1370#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1371
1372/* SPORTx_MCMC1 Macros */
1373#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1374
1375/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1376#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1377
1378/* SPORTx_MCMC2 Masks */
1379#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1380#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1381#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1382#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1383#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1384#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1385#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1386#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1387#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1388#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1389#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1390#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1391#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1392#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1393#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1394#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1395#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1396#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1397#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1398#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1399#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1400#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1401#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1402
1403/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1404/* EBIU_AMGCTL Masks */
1405#define AMCKEN 0x0001 /* Enable CLKOUT */
1406#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1407#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1408#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1409#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1410#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1411
1412/* EBIU_AMBCTL0 Masks */
1413#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1414#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1415#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1416#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1417#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1418#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1419#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1420#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1421#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1422#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1423#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1424#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1425#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1426#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1427#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1428#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1429#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1430#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1431#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1432#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1433#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1434#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1435#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1436#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1437#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1438#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1439#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1440#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1441#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1442#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1443#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1444#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1445#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1446#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1447#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1448#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1449#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1450#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1451#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1452#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1453#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1454#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1455#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1456#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1457
1458#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1459#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1460#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1461#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1462#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1463#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1464#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1465#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1466#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1467#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1468#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1469#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1470#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1471#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1472#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1473#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1474#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1475#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1476#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1477#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1478#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1479#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1480#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1481#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1482#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1483#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1484#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1485#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1486#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1487#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1488#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1489#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1490#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1491#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1492#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1493#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1494#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1495#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1496#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1497#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1498#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1499#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1500#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1501#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1502
1503/* EBIU_AMBCTL1 Masks */
1504#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1505#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1506#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1507#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1508#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1509#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1510#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1511#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1512#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1513#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1514#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1515#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1516#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1517#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1518#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1519#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1520#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1521#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1522#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1523#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1524#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1525#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1526#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1527#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1528#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1529#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1530#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1531#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1532#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1533#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1534#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1535#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1536#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1537#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1538#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1539#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1540#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1541#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1542#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1543#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1544#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1545#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1546#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1547#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1548
1549#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1550#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1551#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1552#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1553#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1554#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1555#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1556#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1557#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1558#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1559#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1560#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1561#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1562#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1563#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1564#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1565#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1566#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1567#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1568#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1569#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1570#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1571#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1572#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1573#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1574#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1575#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1576#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1577#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1578#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1579#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1580#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1581#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1582#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1583#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1584#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1585#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1586#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1587#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1588#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1589#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1590#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1591#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1592#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1593
1594/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1595/* EBIU_SDGCTL Masks */
1596#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1597#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1598#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1599#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1600#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1601#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1602#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1603#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1604#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1605#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1606#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1607#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1608#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1609#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1610#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1611#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1612#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1613#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1614#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1615#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1616#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1617#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1618#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1619#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1620#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1621#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1622#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1623#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1624#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1625#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1626#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1627#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1628#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1629#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1630#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1631#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1632#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1633#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1634#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1635#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1636#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1637#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1638#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1639#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1640#define EMREN 0x10000000 /* Extended Mode Register Enable */
1641#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1642#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1643
1644/* EBIU_SDBCTL Masks */
1645#define EBE 0x0001 /* Enable SDRAM External Bank */
1646#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1647#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1648#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1649#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1650#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1651#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1652#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1653#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1654
1655/* EBIU_SDSTAT Masks */
1656#define SDCI 0x0001 /* SDRAM Controller Idle */
1657#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1658#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1659#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1660#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1661#define BGSTAT 0x0020 /* Bus Grant Status */
1662
1663/* ************************** DMA CONTROLLER MASKS ********************************/
1664/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1665#define DMAEN 0x0001 /* DMA Channel Enable */
1666#define WNR 0x0002 /* Channel Direction (W/R*) */
1667#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1668#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1669#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1670#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1671#define RESTART 0x0020 /* DMA Buffer Clear */
1672#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1673#define DI_EN 0x0080 /* Data Interrupt Enable */
1674#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1675#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1676#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1677#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1678#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1679#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1680#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1681#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1682#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1683#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1684#define NDSIZE 0x0900 /* Next Descriptor Size */
1685
1686#define DMAFLOW 0x7000 /* Flow Control */
1687#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1688#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1689#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1690#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1691#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1692
1693/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1694#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1695#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1696#define PMAP_PPI 0x0000 /* PPI Port DMA */
1697#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1698#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1699#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1700#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1701#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1702#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1703#define PMAP_SPI 0x7000 /* SPI Port DMA */
1704#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1705#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1706#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1707#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1708
1709/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1710#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1711#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1712#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1713#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1714
1715/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1716/* PPI_CONTROL Masks */
1717#define PORT_EN 0x0001 /* PPI Port Enable */
1718#define PORT_DIR 0x0002 /* PPI Port Direction */
1719#define XFR_TYPE 0x000C /* PPI Transfer Type */
1720#define PORT_CFG 0x0030 /* PPI Port Configuration */
1721#define FLD_SEL 0x0040 /* PPI Active Field Select */
1722#define PACK_EN 0x0080 /* PPI Packing Mode */
1723#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1724#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1725#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1726#define DLENGTH 0x3800 /* PPI Data Length */
1727#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1728#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1729#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1730#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1731#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1732#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1733#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1734#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1735#define POLC 0x4000 /* PPI Clock Polarity */
1736#define POLS 0x8000 /* PPI Frame Sync Polarity */
1737
1738/* PPI_STATUS Masks */
1739#define FLD 0x0400 /* Field Indicator */
1740#define FT_ERR 0x0800 /* Frame Track Error */
1741#define OVR 0x1000 /* FIFO Overflow Error */
1742#define UNDR 0x2000 /* FIFO Underrun Error */
1743#define ERR_DET 0x4000 /* Error Detected Indicator */
1744#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1745
1746/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1747/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1748#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1749#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1750
1751/* TWI_PRESCALE Masks */
1752#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1753#define TWI_ENA 0x0080 /* TWI Enable */
1754#define SCCB 0x0200 /* SCCB Compatibility Enable */
1755
1756/* TWI_SLAVE_CTRL Masks */
1757#define SEN 0x0001 /* Slave Enable */
1758#define SADD_LEN 0x0002 /* Slave Address Length */
1759#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1760#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1761#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1762
1763/* TWI_SLAVE_STAT Masks */
1764#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1765#define GCALL 0x0002 /* General Call Indicator */
1766
1767/* TWI_MASTER_CTRL Masks */
1768#define MEN 0x0001 /* Master Mode Enable */
1769#define MADD_LEN 0x0002 /* Master Address Length */
1770#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1771#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1772#define STOP 0x0010 /* Issue Stop Condition */
1773#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1774#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1775#define SDAOVR 0x4000 /* Serial Data Override */
1776#define SCLOVR 0x8000 /* Serial Clock Override */
1777
1778/* TWI_MASTER_STAT Masks */
1779#define MPROG 0x0001 /* Master Transfer In Progress */
1780#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1781#define ANAK 0x0004 /* Address Not Acknowledged */
1782#define DNAK 0x0008 /* Data Not Acknowledged */
1783#define BUFRDERR 0x0010 /* Buffer Read Error */
1784#define BUFWRERR 0x0020 /* Buffer Write Error */
1785#define SDASEN 0x0040 /* Serial Data Sense */
1786#define SCLSEN 0x0080 /* Serial Clock Sense */
1787#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1788
1789/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1790#define SINIT 0x0001 /* Slave Transfer Initiated */
1791#define SCOMP 0x0002 /* Slave Transfer Complete */
1792#define SERR 0x0004 /* Slave Transfer Error */
1793#define SOVF 0x0008 /* Slave Overflow */
1794#define MCOMP 0x0010 /* Master Transfer Complete */
1795#define MERR 0x0020 /* Master Transfer Error */
1796#define XMTSERV 0x0040 /* Transmit FIFO Service */
1797#define RCVSERV 0x0080 /* Receive FIFO Service */
1798
1799/* TWI_FIFO_CTRL Masks */
1800#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1801#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1802#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1803#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1804
1805/* TWI_FIFO_STAT Masks */
1806#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1807#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1808#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1809#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1810
1811#define RCVSTAT 0x000C /* Receive FIFO Status */
1812#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1813#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1814#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1815
1816/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
1817/* CAN_CONTROL Masks */
1818#define SRS 0x0001 /* Software Reset */
1819#define DNM 0x0002 /* Device Net Mode */
1820#define ABO 0x0004 /* Auto-Bus On Enable */
1821#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
1822#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
1823#define SMR 0x0020 /* Sleep Mode Request */
1824#define CSR 0x0040 /* CAN Suspend Mode Request */
1825#define CCR 0x0080 /* CAN Configuration Mode Request */
1826
1827/* CAN_STATUS Masks */
1828#define WT 0x0001 /* TX Warning Flag */
1829#define WR 0x0002 /* RX Warning Flag */
1830#define EP 0x0004 /* Error Passive Mode */
1831#define EBO 0x0008 /* Error Bus Off Mode */
1832#define SMA 0x0020 /* Sleep Mode Acknowledge */
1833#define CSA 0x0040 /* Suspend Mode Acknowledge */
1834#define CCA 0x0080 /* Configuration Mode Acknowledge */
1835#define MBPTR 0x1F00 /* Mailbox Pointer */
1836#define TRM 0x4000 /* Transmit Mode */
1837#define REC 0x8000 /* Receive Mode */
1838
1839/* CAN_CLOCK Masks */
1840#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
1841
1842/* CAN_TIMING Masks */
1843#define TSEG1 0x000F /* Time Segment 1 */
1844#define TSEG2 0x0070 /* Time Segment 2 */
1845#define SAM 0x0080 /* Sampling */
1846#define SJW 0x0300 /* Synchronization Jump Width */
1847
1848/* CAN_DEBUG Masks */
1849#define DEC 0x0001 /* Disable CAN Error Counters */
1850#define DRI 0x0002 /* Disable CAN RX Input */
1851#define DTO 0x0004 /* Disable CAN TX Output */
1852#define DIL 0x0008 /* Disable CAN Internal Loop */
1853#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
1854#define MRB 0x0020 /* Mode Read Back Enable */
1855#define CDE 0x8000 /* CAN Debug Enable */
1856
1857/* CAN_CEC Masks */
1858#define RXECNT 0x00FF /* Receive Error Counter */
1859#define TXECNT 0xFF00 /* Transmit Error Counter */
1860
1861/* CAN_INTR Masks */
1862#define MBRIF 0x0001 /* Mailbox Receive Interrupt */
1863#define MBTIF 0x0002 /* Mailbox Transmit Interrupt */
1864#define GIRQ 0x0004 /* Global Interrupt */
1865#define SMACK 0x0008 /* Sleep Mode Acknowledge */
1866#define CANTX 0x0040 /* CAN TX Bus Value */
1867#define CANRX 0x0080 /* CAN RX Bus Value */
1868
1869/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
1870#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
1871#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
1872#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
1873#define BASEID 0x1FFC /* Base Identifier */
1874#define IDE 0x2000 /* Identifier Extension */
1875#define RTR 0x4000 /* Remote Frame Transmission Request */
1876#define AME 0x8000 /* Acceptance Mask Enable */
1877
1878/* CAN_MBxx_TIMESTAMP Masks */
1879#define TSV 0xFFFF /* Timestamp */
1880
1881/* CAN_MBxx_LENGTH Masks */
1882#define DLC 0x000F /* Data Length Code */
1883
1884/* CAN_AMxxH and CAN_AMxxL Masks */
1885#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
1886#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
1887#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
1888#define BASEID 0x1FFC /* Base Identifier */
1889#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
1890#define FMD 0x4000 /* Full Mask Data Field Enable */
1891#define FDF 0x8000 /* Filter On Data Field Enable */
1892
1893/* CAN_MC1 Masks */
1894#define MC0 0x0001 /* Enable Mailbox 0 */
1895#define MC1 0x0002 /* Enable Mailbox 1 */
1896#define MC2 0x0004 /* Enable Mailbox 2 */
1897#define MC3 0x0008 /* Enable Mailbox 3 */
1898#define MC4 0x0010 /* Enable Mailbox 4 */
1899#define MC5 0x0020 /* Enable Mailbox 5 */
1900#define MC6 0x0040 /* Enable Mailbox 6 */
1901#define MC7 0x0080 /* Enable Mailbox 7 */
1902#define MC8 0x0100 /* Enable Mailbox 8 */
1903#define MC9 0x0200 /* Enable Mailbox 9 */
1904#define MC10 0x0400 /* Enable Mailbox 10 */
1905#define MC11 0x0800 /* Enable Mailbox 11 */
1906#define MC12 0x1000 /* Enable Mailbox 12 */
1907#define MC13 0x2000 /* Enable Mailbox 13 */
1908#define MC14 0x4000 /* Enable Mailbox 14 */
1909#define MC15 0x8000 /* Enable Mailbox 15 */
1910
1911/* CAN_MC2 Masks */
1912#define MC16 0x0001 /* Enable Mailbox 16 */
1913#define MC17 0x0002 /* Enable Mailbox 17 */
1914#define MC18 0x0004 /* Enable Mailbox 18 */
1915#define MC19 0x0008 /* Enable Mailbox 19 */
1916#define MC20 0x0010 /* Enable Mailbox 20 */
1917#define MC21 0x0020 /* Enable Mailbox 21 */
1918#define MC22 0x0040 /* Enable Mailbox 22 */
1919#define MC23 0x0080 /* Enable Mailbox 23 */
1920#define MC24 0x0100 /* Enable Mailbox 24 */
1921#define MC25 0x0200 /* Enable Mailbox 25 */
1922#define MC26 0x0400 /* Enable Mailbox 26 */
1923#define MC27 0x0800 /* Enable Mailbox 27 */
1924#define MC28 0x1000 /* Enable Mailbox 28 */
1925#define MC29 0x2000 /* Enable Mailbox 29 */
1926#define MC30 0x4000 /* Enable Mailbox 30 */
1927#define MC31 0x8000 /* Enable Mailbox 31 */
1928
1929/* CAN_MD1 Masks */
1930#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
1931#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
1932#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
1933#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
1934#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
1935#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
1936#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
1937#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
1938#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
1939#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
1940#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
1941#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
1942#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
1943#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
1944#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
1945#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
1946
1947/* CAN_MD2 Masks */
1948#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
1949#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
1950#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
1951#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
1952#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
1953#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
1954#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
1955#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
1956#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
1957#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
1958#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
1959#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
1960#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
1961#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
1962#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
1963#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
1964
1965/* CAN_RMP1 Masks */
1966#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
1967#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
1968#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
1969#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
1970#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
1971#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
1972#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
1973#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
1974#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
1975#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
1976#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
1977#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
1978#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
1979#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
1980#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
1981#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
1982
1983/* CAN_RMP2 Masks */
1984#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
1985#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
1986#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
1987#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
1988#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
1989#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
1990#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
1991#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
1992#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
1993#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
1994#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
1995#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
1996#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
1997#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
1998#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
1999#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
2000
2001/* CAN_RML1 Masks */
2002#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
2003#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
2004#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
2005#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
2006#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
2007#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
2008#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
2009#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
2010#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
2011#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
2012#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
2013#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
2014#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
2015#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
2016#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
2017#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
2018
2019/* CAN_RML2 Masks */
2020#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
2021#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
2022#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
2023#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
2024#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
2025#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
2026#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
2027#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
2028#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
2029#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
2030#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
2031#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
2032#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
2033#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
2034#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
2035#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
2036
2037/* CAN_OPSS1 Masks */
2038#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
2039#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
2040#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
2041#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
2042#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
2043#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
2044#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
2045#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
2046#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
2047#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
2048#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
2049#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
2050#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
2051#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
2052#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
2053#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
2054
2055/* CAN_OPSS2 Masks */
2056#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
2057#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
2058#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
2059#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
2060#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
2061#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
2062#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
2063#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
2064#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
2065#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
2066#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
2067#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
2068#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
2069#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
2070#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
2071#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
2072
2073/* CAN_TRR1 Masks */
2074#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
2075#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
2076#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
2077#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
2078#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
2079#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
2080#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
2081#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
2082#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
2083#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
2084#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
2085#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
2086#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
2087#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
2088#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
2089#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
2090
2091/* CAN_TRR2 Masks */
2092#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
2093#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
2094#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
2095#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
2096#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
2097#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
2098#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
2099#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
2100#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
2101#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
2102#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
2103#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
2104#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
2105#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
2106#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
2107#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
2108
2109/* CAN_TRS1 Masks */
2110#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
2111#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
2112#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
2113#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
2114#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
2115#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
2116#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
2117#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
2118#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
2119#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
2120#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
2121#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
2122#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
2123#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
2124#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
2125#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
2126
2127/* CAN_TRS2 Masks */
2128#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
2129#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
2130#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
2131#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
2132#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
2133#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
2134#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
2135#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
2136#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
2137#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
2138#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
2139#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
2140#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
2141#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
2142#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
2143#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
2144
2145/* CAN_AA1 Masks */
2146#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
2147#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
2148#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
2149#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
2150#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
2151#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
2152#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
2153#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
2154#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
2155#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
2156#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
2157#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
2158#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
2159#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
2160#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
2161#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
2162
2163/* CAN_AA2 Masks */
2164#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
2165#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
2166#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
2167#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
2168#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
2169#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
2170#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
2171#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
2172#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
2173#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
2174#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
2175#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
2176#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
2177#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
2178#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
2179#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
2180
2181/* CAN_TA1 Masks */
2182#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
2183#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
2184#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
2185#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
2186#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
2187#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
2188#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
2189#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
2190#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
2191#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
2192#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
2193#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
2194#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
2195#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
2196#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
2197#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
2198
2199/* CAN_TA2 Masks */
2200#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
2201#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
2202#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
2203#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
2204#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
2205#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
2206#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
2207#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
2208#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
2209#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
2210#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
2211#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
2212#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
2213#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
2214#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
2215#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
2216
2217/* CAN_MBTD Masks */
2218#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
2219#define TDA 0x0040 /* Temporary Disable Acknowledge */
2220#define TDR 0x0080 /* Temporary Disable Request */
2221
2222/* CAN_RFH1 Masks */
2223#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
2224#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
2225#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
2226#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
2227#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
2228#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
2229#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
2230#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
2231#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
2232#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
2233#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
2234#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
2235#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
2236#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
2237#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
2238#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
2239
2240/* CAN_RFH2 Masks */
2241#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
2242#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
2243#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
2244#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
2245#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
2246#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
2247#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
2248#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
2249#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
2250#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
2251#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
2252#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
2253#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
2254#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
2255#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
2256#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
2257
2258/* CAN_MBTIF1 Masks */
2259#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
2260#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
2261#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
2262#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
2263#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
2264#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
2265#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
2266#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
2267#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
2268#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
2269#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
2270#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
2271#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
2272#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
2273#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
2274#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
2275
2276/* CAN_MBTIF2 Masks */
2277#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
2278#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
2279#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
2280#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
2281#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
2282#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
2283#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
2284#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
2285#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
2286#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
2287#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
2288#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
2289#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
2290#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
2291#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
2292#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
2293
2294/* CAN_MBRIF1 Masks */
2295#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
2296#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
2297#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
2298#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
2299#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
2300#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
2301#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
2302#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
2303#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
2304#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
2305#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
2306#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
2307#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
2308#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
2309#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
2310#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
2311
2312/* CAN_MBRIF2 Masks */
2313#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
2314#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
2315#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
2316#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
2317#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
2318#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
2319#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
2320#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
2321#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
2322#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
2323#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
2324#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
2325#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
2326#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
2327#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
2328#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
2329
2330/* CAN_MBIM1 Masks */
2331#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
2332#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
2333#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
2334#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
2335#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
2336#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
2337#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
2338#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
2339#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
2340#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
2341#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
2342#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
2343#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
2344#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
2345#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
2346#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
2347
2348/* CAN_MBIM2 Masks */
2349#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
2350#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
2351#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
2352#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
2353#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
2354#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
2355#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
2356#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
2357#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
2358#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
2359#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
2360#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
2361#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
2362#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
2363#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
2364#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
2365
2366/* CAN_GIM Masks */
2367#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
2368#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
2369#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
2370#define BOIM 0x0008 /* Enable Bus Off Interrupt */
2371#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
2372#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
2373#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
2374#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
2375#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
2376#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
2377#define ADIM 0x0400 /* Enable Access Denied Interrupt */
2378
2379/* CAN_GIS Masks */
2380#define EWTIS 0x0001 /* TX Error Count IRQ Status */
2381#define EWRIS 0x0002 /* RX Error Count IRQ Status */
2382#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
2383#define BOIS 0x0008 /* Bus Off IRQ Status */
2384#define WUIS 0x0010 /* Wake-Up IRQ Status */
2385#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
2386#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
2387#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
2388#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
2389#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
2390#define ADIS 0x0400 /* Access Denied IRQ Status */
2391
2392/* CAN_GIF Masks */
2393#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
2394#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
2395#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
2396#define BOIF 0x0008 /* Bus Off IRQ Flag */
2397#define WUIF 0x0010 /* Wake-Up IRQ Flag */
2398#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
2399#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
2400#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
2401#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
2402#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
2403#define ADIF 0x0400 /* Access Denied IRQ Flag */
2404
2405/* CAN_UCCNF Masks */
2406#define UCCNF 0x000F /* Universal Counter Mode */
2407#define UC_STAMP 0x0001 /* Timestamp Mode */
2408#define UC_WDOG 0x0002 /* Watchdog Mode */
2409#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
2410#define UC_ERROR 0x0006 /* CAN Error Frame Count */
2411#define UC_OVER 0x0007 /* CAN Overload Frame Count */
2412#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
2413#define UC_AA 0x0009 /* TX Abort Count */
2414#define UC_TA 0x000A /* TX Successful Count */
2415#define UC_REJECT 0x000B /* RX Message Rejected Count */
2416#define UC_RML 0x000C /* RX Message Lost Count */
2417#define UC_RX 0x000D /* Total Successful RX Messages Count */
2418#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
2419#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
2420#define UCRC 0x0020 /* Universal Counter Reload/Clear */
2421#define UCCT 0x0040 /* Universal Counter CAN Trigger */
2422#define UCE 0x0080 /* Universal Counter Enable */
2423
2424/* CAN_ESR Masks */
2425#define ACKE 0x0004 /* Acknowledge Error */
2426#define SER 0x0008 /* Stuff Error */
2427#define CRCE 0x0010 /* CRC Error */
2428#define SA0 0x0020 /* Stuck At Dominant Error */
2429#define BEF 0x0040 /* Bit Error Flag */
2430#define FER 0x0080 /* Form Error Flag */
2431
2432/* CAN_EWR Masks */
2433#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
2434#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
2435
2436/* ******************* PIN CONTROL REGISTER MASKS ************************/
2437/* PORT_MUX Masks */
2438#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
2439#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
2440#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
2441
2442#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
2443#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
2444#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
2445#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
2446
2447#define PFDE 0x0008 /* Port F DMA Request Enable */
2448#define PGDE_UART 0x0000 /* Enable UART0 RX/TX */
2449#define PGDE_DMA 0x0008 /* Enable DMAR1:0 */
2450
2451#define PFTE 0x0010 /* Port F Timer Enable */
2452#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
2453#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
2454
2455#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
2456#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
2457#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
2458
2459#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
2460#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
2461#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
2462
2463#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
2464#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
2465#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
2466
2467#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
2468#define PFFE_TIMER 0x0000 /* Enable TMR2 */
2469#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
2470
2471#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
2472#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
2473#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
2474
2475#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
2476#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
2477#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
2478
2479#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
2480#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
2481#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
2482
2483/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
2484/* HDMAx_CTL Masks */
2485#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
2486#define REP 0x0002 /* HDMA Request Polarity */
2487#define UTE 0x0004 /* Urgency Threshold Enable */
2488#define OIE 0x0010 /* Overflow Interrupt Enable */
2489#define BDIE 0x0020 /* Block Done Interrupt Enable */
2490#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
2491#define DRQ 0x0300 /* HDMA Request Type */
2492#define DRQ_NONE 0x0000 /* No Request */
2493#define DRQ_SINGLE 0x0100 /* Channels Request Single */
2494#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
2495#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
2496#define RBC 0x1000 /* Reload BCNT With IBCNT */
2497#define PS 0x2000 /* HDMA Pin Status */
2498#define OI 0x4000 /* Overflow Interrupt Generated */
2499#define BDI 0x8000 /* Block Done Interrupt Generated */
2500
2501#endif /* _DEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h
new file mode 100644
index 000000000000..26f9c02eb73c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/defBF537.h
@@ -0,0 +1,404 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/defbf537.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _DEF_BF537_H
33#define _DEF_BF537_H
34
35/*include all Core registers and bit definitions*/
36#include "defBF537.h"
37
38/*include core specific register pointer definitions*/
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41/************************************************************************************
42** Define EMAC Section Unique to BF536/BF537
43*************************************************************************************/
44
45/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
46#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
47#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
48#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
49#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
50#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
51#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
52#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
53#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
54#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
55#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
56#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
57#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
58#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
59#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
60#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
61#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
62#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
63#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
64#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
65
66#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
67#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
68#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
69#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
70#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
71#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
72#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
73#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
74
75#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
76#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
77#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
78#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
79#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
80
81#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
82#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
83#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
84#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
85#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
86#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
87#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
88#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
89#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
90#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
91#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
92#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
93#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
94#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
95#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
96#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
97#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
98#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
99#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
100#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
101#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
102#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
103#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
104#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
105
106#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
107#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
108#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
109#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
110#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
111#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
112#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
113#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
114#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
115#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
116#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
117#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
118#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
119#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
120#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
121#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
122#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
123#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
124#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
125#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
126#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
127#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
128#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
129
130/* Listing for IEEE-Supported Count Registers */
131#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
132#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
133#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
134#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
135#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
136#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
137#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
138#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
139#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
140#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
141#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
142#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
143#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
144#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
145#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
146#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
147#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
148#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
149#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
150#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
151#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
152#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
153#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
154#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
155
156#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
157#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
158#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
159#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
160#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
161#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
162#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
163#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
164#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
165#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
166#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
167#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
168#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
169#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
170#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
171#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
172#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
173#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
174#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
175#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
176#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
177#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
178#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
179
180/***********************************************************************************
181** System MMR Register Bits And Macros
182**
183** Disclaimer: All macros are intended to make C and Assembly code more readable.
184** Use these macros carefully, as any that do left shifts for field
185** depositing will result in the lower order bits being destroyed. Any
186** macro that shifts left to properly position the bit-field should be
187** used as part of an OR to initialize a register and NOT as a dynamic
188** modifier UNLESS the lower order bits are saved and ORed back in when
189** the macro is used.
190*************************************************************************************/
191/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
192/* EMAC_OPMODE Masks */
193#define RE 0x00000001 /* Receiver Enable */
194#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
195#define HU 0x00000010 /* Hash Filter Unicast Address */
196#define HM 0x00000020 /* Hash Filter Multicast Address */
197#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
198#define PR 0x00000080 /* Promiscuous Mode Enable */
199#define IFE 0x00000100 /* Inverse Filtering Enable */
200#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
201#define PBF 0x00000400 /* Pass Bad Frames Enable */
202#define PSF 0x00000800 /* Pass Short Frames Enable */
203#define RAF 0x00001000 /* Receive-All Mode */
204#define TE 0x00010000 /* Transmitter Enable */
205#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
206#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
207#define DC 0x00080000 /* Deferral Check */
208#define BOLMT 0x00300000 /* Back-Off Limit */
209#define BOLMT_10 0x00000000 /* 10-bit range */
210#define BOLMT_8 0x00100000 /* 8-bit range */
211#define BOLMT_4 0x00200000 /* 4-bit range */
212#define BOLMT_1 0x00300000 /* 1-bit range */
213#define DRTY 0x00400000 /* Disable TX Retry On Collision */
214#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
215#define RMII 0x01000000 /* RMII/MII* Mode */
216#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
217#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
218#define LB 0x08000000 /* Internal Loopback Enable */
219#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
220
221/* EMAC_STAADD Masks */
222#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
223#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
224#define STADISPRE 0x00000004 /* Disable Preamble Generation */
225#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
226#define REGAD 0x000007C0 /* STA Register Address */
227#define PHYAD 0x0000F800 /* PHY Device Address */
228
229#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
230#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
231
232/* EMAC_STADAT Mask */
233#define STADATA 0x0000FFFF /* Station Management Data */
234
235/* EMAC_FLC Masks */
236#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
237#define FLCE 0x00000002 /* Flow Control Enable */
238#define PCF 0x00000004 /* Pass Control Frames */
239#define BKPRSEN 0x00000008 /* Enable Backpressure */
240#define FLCPAUSE 0xFFFF0000 /* Pause Time */
241
242#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
243
244/* EMAC_WKUP_CTL Masks */
245#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
246#define MPKE 0x00000002 /* Magic Packet Enable */
247#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
248#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
249#define MPKS 0x00000020 /* Magic Packet Received Status */
250#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
251
252/* EMAC_WKUP_FFCMD Masks */
253#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
254#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
255#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
256#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
257#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
258#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
259#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
260#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
261
262/* EMAC_WKUP_FFOFF Masks */
263#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
264#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
265#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
266#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
267
268#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
269#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
270#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
271#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
272/* Set ALL Offsets */
273#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
274
275/* EMAC_WKUP_FFCRC0 Masks */
276#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
277#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
278
279#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
280#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
281
282/* EMAC_WKUP_FFCRC1 Masks */
283#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
284#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
285
286#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
287#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
288
289/* EMAC_SYSCTL Masks */
290#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
291#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
292#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
293#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
294
295#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
296
297/* EMAC_SYSTAT Masks */
298#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
299#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
300#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
301#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
302#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
303#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
304#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
305#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
306
307/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
308#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
309#define RX_COMP 0x00001000 /* RX Frame Complete */
310#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
311#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
312#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
313#define RX_CRC 0x00010000 /* RX Frame CRC Error */
314#define RX_LEN 0x00020000 /* RX Frame Length Error */
315#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
316#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
317#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
318#define RX_PHY 0x00200000 /* RX Frame PHY Error */
319#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
320#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
321#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
322#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
323#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
324#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
325#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
326#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
327#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
328#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
329
330/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
331#define TX_COMP 0x00000001 /* TX Frame Complete */
332#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
333#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
334#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
335#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
336#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
337#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
338#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
339#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
340#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
341#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
342#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
343#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
344#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
345#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
346
347/* EMAC_MMC_CTL Masks */
348#define RSTC 0x00000001 /* Reset All Counters */
349#define CROLL 0x00000002 /* Counter Roll-Over Enable */
350#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
351#define MMCE 0x00000008 /* Enable MMC Counter Operation */
352
353/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
354#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
355#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
356#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
357#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
358#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
359#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
360#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
361#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
362#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
363#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
364#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
365#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
366#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
367#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
368#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
369#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
370#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
371#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
372#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
373#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
374#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
375#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
376#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
377#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
378
379/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
380#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
381#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
382#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
383#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
384#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
385#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
386#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
387#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
388#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
389#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
390#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
391#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
392#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
393#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
394#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
395#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
396#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
397#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
398#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
399#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
400#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
401#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
402#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
403
404#endif /* _DEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
new file mode 100644
index 000000000000..7a964040870a
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/dma.h
@@ -0,0 +1,55 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/dma.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define MAX_BLACKFIN_DMA_CHANNEL 16
36
37#define CH_PPI 0
38#define CH_EMAC_RX 1
39#define CH_EMAC_TX 2
40#define CH_SPORT0_RX 3
41#define CH_SPORT0_TX 4
42#define CH_SPORT1_RX 5
43#define CH_SPORT1_TX 6
44#define CH_SPI 7
45#define CH_UART0_RX 8
46#define CH_UART0_TX 9
47#define CH_UART1_RX 10
48#define CH_UART1_TX 11
49
50#define CH_MEM_STREAM0_DEST 12 /* TX */
51#define CH_MEM_STREAM0_SRC 13 /* RX */
52#define CH_MEM_STREAM1_DEST 14 /* TX */
53#define CH_MEM_STREAM1_SRC 15 /* RX */
54
55#endif
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
new file mode 100644
index 000000000000..8af2a832ef6b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -0,0 +1,219 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/irq.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF537_IRQ_H_
33#define _BF537_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38Core Emulation **
39 Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47.....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52 */
53
54#define SYS_IRQS 41
55#define NR_PERI_INTS 32
56
57/* The ABSTRACT IRQ definitions */
58/** the first seven of the following are fixed, the rest you change if you need to **/
59#define IRQ_EMU 0 /*Emulation */
60#define IRQ_RST 1 /*reset */
61#define IRQ_NMI 2 /*Non Maskable */
62#define IRQ_EVX 3 /*Exception */
63#define IRQ_UNUSED 4 /*- unused interrupt*/
64#define IRQ_HWERR 5 /*Hardware Error */
65#define IRQ_CORETMR 6 /*Core timer */
66
67#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
68#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
69#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
70#define IRQ_RTC 10 /*RTC Interrupt */
71#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
72#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
73#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
74#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
75#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
76#define IRQ_TWI 16 /*TWI Interrupt */
77#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
78#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
79#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
80#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
81#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
82#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
83#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
84#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
85#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
86#define IRQ_TMR0 26 /*Timer 0 */
87#define IRQ_TMR1 27 /*Timer 1 */
88#define IRQ_TMR2 28 /*Timer 2 */
89#define IRQ_TMR3 29 /*Timer 3 */
90#define IRQ_TMR4 30 /*Timer 4 */
91#define IRQ_TMR5 31 /*Timer 5 */
92#define IRQ_TMR6 32 /*Timer 6 */
93#define IRQ_TMR7 33 /*Timer 7 */
94#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
95#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
96#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
97#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
98#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
99#define IRQ_WATCH 38 /*Watch Dog Timer */
100#define IRQ_SW_INT1 40 /*Software Int 1 */
101#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */
102
103#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
104#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
105#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */
106#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
107#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
108#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
109#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
110#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
111
112#define IRQ_PF0 50
113#define IRQ_PF1 51
114#define IRQ_PF2 52
115#define IRQ_PF3 53
116#define IRQ_PF4 54
117#define IRQ_PF5 55
118#define IRQ_PF6 56
119#define IRQ_PF7 57
120#define IRQ_PF8 58
121#define IRQ_PF9 59
122#define IRQ_PF10 60
123#define IRQ_PF11 61
124#define IRQ_PF12 62
125#define IRQ_PF13 63
126#define IRQ_PF14 64
127#define IRQ_PF15 65
128
129#define IRQ_PG0 66
130#define IRQ_PG1 67
131#define IRQ_PG2 68
132#define IRQ_PG3 69
133#define IRQ_PG4 70
134#define IRQ_PG5 71
135#define IRQ_PG6 72
136#define IRQ_PG7 73
137#define IRQ_PG8 74
138#define IRQ_PG9 75
139#define IRQ_PG10 76
140#define IRQ_PG11 77
141#define IRQ_PG12 78
142#define IRQ_PG13 79
143#define IRQ_PG14 80
144#define IRQ_PG15 81
145
146#define IRQ_PH0 82
147#define IRQ_PH1 83
148#define IRQ_PH2 84
149#define IRQ_PH3 85
150#define IRQ_PH4 86
151#define IRQ_PH5 87
152#define IRQ_PH6 88
153#define IRQ_PH7 89
154#define IRQ_PH8 90
155#define IRQ_PH9 91
156#define IRQ_PH10 92
157#define IRQ_PH11 93
158#define IRQ_PH12 94
159#define IRQ_PH13 95
160#define IRQ_PH14 96
161#define IRQ_PH15 97
162
163#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
164#define NR_IRQS (IRQ_PH15+1)
165#else
166#define NR_IRQS (IRQ_UART1_ERROR+1)
167#endif
168
169#define IVG7 7
170#define IVG8 8
171#define IVG9 9
172#define IVG10 10
173#define IVG11 11
174#define IVG12 12
175#define IVG13 13
176#define IVG14 14
177#define IVG15 15
178
179/* IAR0 BIT FIELDS*/
180#define IRQ_PLL_WAKEUP_POS 0
181#define IRQ_DMA_ERROR_POS 4
182#define IRQ_ERROR_POS 8
183#define IRQ_RTC_POS 12
184#define IRQ_PPI_POS 16
185#define IRQ_SPORT0_RX_POS 20
186#define IRQ_SPORT0_TX_POS 24
187#define IRQ_SPORT1_RX_POS 28
188
189/* IAR1 BIT FIELDS*/
190#define IRQ_SPORT1_TX_POS 0
191#define IRQ_TWI_POS 4
192#define IRQ_SPI_POS 8
193#define IRQ_UART0_RX_POS 12
194#define IRQ_UART0_TX_POS 16
195#define IRQ_UART1_RX_POS 20
196#define IRQ_UART1_TX_POS 24
197#define IRQ_CAN_RX_POS 28
198
199/* IAR2 BIT FIELDS*/
200#define IRQ_CAN_TX_POS 0
201#define IRQ_MAC_RX_POS 4
202#define IRQ_MAC_TX_POS 8
203#define IRQ_TMR0_POS 12
204#define IRQ_TMR1_POS 16
205#define IRQ_TMR2_POS 20
206#define IRQ_TMR3_POS 24
207#define IRQ_TMR4_POS 28
208
209/* IAR3 BIT FIELDS*/
210#define IRQ_TMR5_POS 0
211#define IRQ_TMR6_POS 4
212#define IRQ_TMR7_POS 8
213#define IRQ_PROG_INTA_POS 12
214#define IRQ_PORTG_INTB_POS 16
215#define IRQ_MEM_DMA0_POS 20
216#define IRQ_MEM_DMA1_POS 24
217#define IRQ_WATCH_POS 28
218
219#endif /* _BF537_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf537/mem_init.h b/include/asm-blackfin/mach-bf537/mem_init.h
new file mode 100644
index 000000000000..9ad979d416c6
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/mem_init.h
@@ -0,0 +1,330 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_MT48LC32M8A2_75)
122 /*SDRAM INFORMATION: */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129 /*SDRAM INFORMATION: */
130#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132#define SDRAM_CL CL_3
133#endif
134
135#if (CONFIG_MEM_GENERIC_BOARD)
136 /*SDRAM INFORMATION: Modify this for your board */
137#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139#define SDRAM_CL CL_3
140#endif
141
142#if (CONFIG_MEM_SIZE == 128)
143#define SDRAM_SIZE EBSZ_128
144#endif
145#if (CONFIG_MEM_SIZE == 64)
146#define SDRAM_SIZE EBSZ_64
147#endif
148#if (CONFIG_MEM_SIZE == 32)
149#define SDRAM_SIZE EBSZ_32
150#endif
151#if (CONFIG_MEM_SIZE == 16)
152#define SDRAM_SIZE EBSZ_16
153#endif
154#if (CONFIG_MEM_ADD_WIDTH == 11)
155#define SDRAM_WIDTH EBCAW_11
156#endif
157#if (CONFIG_MEM_ADD_WIDTH == 10)
158#define SDRAM_WIDTH EBCAW_10
159#endif
160#if (CONFIG_MEM_ADD_WIDTH == 9)
161#define SDRAM_WIDTH EBCAW_9
162#endif
163#if (CONFIG_MEM_ADD_WIDTH == 8)
164#define SDRAM_WIDTH EBCAW_8
165#endif
166
167#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
168
169/* Equation from section 17 (p17-46) of BF533 HRM */
170#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
171
172/* Enable SCLK Out */
173#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
174
175#if defined CONFIG_CLKIN_HALF
176#define CLKIN_HALF 1
177#else
178#define CLKIN_HALF 0
179#endif
180
181#if defined CONFIG_PLL_BYPASS
182#define PLL_BYPASS 1
183#else
184#define PLL_BYPASS 0
185#endif
186
187/***************************************Currently Not Being Used *********************************/
188#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
189#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
190#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
191#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
192#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
193
194#if (flash_EBIU_AMBCTL_TT > 3)
195#define flash_EBIU_AMBCTL0_TT B0TT_4
196#endif
197#if (flash_EBIU_AMBCTL_TT == 3)
198#define flash_EBIU_AMBCTL0_TT B0TT_3
199#endif
200#if (flash_EBIU_AMBCTL_TT == 2)
201#define flash_EBIU_AMBCTL0_TT B0TT_2
202#endif
203#if (flash_EBIU_AMBCTL_TT < 2)
204#define flash_EBIU_AMBCTL0_TT B0TT_1
205#endif
206
207#if (flash_EBIU_AMBCTL_ST > 3)
208#define flash_EBIU_AMBCTL0_ST B0ST_4
209#endif
210#if (flash_EBIU_AMBCTL_ST == 3)
211#define flash_EBIU_AMBCTL0_ST B0ST_3
212#endif
213#if (flash_EBIU_AMBCTL_ST == 2)
214#define flash_EBIU_AMBCTL0_ST B0ST_2
215#endif
216#if (flash_EBIU_AMBCTL_ST < 2)
217#define flash_EBIU_AMBCTL0_ST B0ST_1
218#endif
219
220#if (flash_EBIU_AMBCTL_HT > 2)
221#define flash_EBIU_AMBCTL0_HT B0HT_3
222#endif
223#if (flash_EBIU_AMBCTL_HT == 2)
224#define flash_EBIU_AMBCTL0_HT B0HT_2
225#endif
226#if (flash_EBIU_AMBCTL_HT == 1)
227#define flash_EBIU_AMBCTL0_HT B0HT_1
228#endif
229#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
230#define flash_EBIU_AMBCTL0_HT B0HT_0
231#endif
232#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
233#define flash_EBIU_AMBCTL0_HT B0HT_1
234#endif
235
236#if (flash_EBIU_AMBCTL_WAT > 14)
237#define flash_EBIU_AMBCTL0_WAT B0WAT_15
238#endif
239#if (flash_EBIU_AMBCTL_WAT == 14)
240#define flash_EBIU_AMBCTL0_WAT B0WAT_14
241#endif
242#if (flash_EBIU_AMBCTL_WAT == 13)
243#define flash_EBIU_AMBCTL0_WAT B0WAT_13
244#endif
245#if (flash_EBIU_AMBCTL_WAT == 12)
246#define flash_EBIU_AMBCTL0_WAT B0WAT_12
247#endif
248#if (flash_EBIU_AMBCTL_WAT == 11)
249#define flash_EBIU_AMBCTL0_WAT B0WAT_11
250#endif
251#if (flash_EBIU_AMBCTL_WAT == 10)
252#define flash_EBIU_AMBCTL0_WAT B0WAT_10
253#endif
254#if (flash_EBIU_AMBCTL_WAT == 9)
255#define flash_EBIU_AMBCTL0_WAT B0WAT_9
256#endif
257#if (flash_EBIU_AMBCTL_WAT == 8)
258#define flash_EBIU_AMBCTL0_WAT B0WAT_8
259#endif
260#if (flash_EBIU_AMBCTL_WAT == 7)
261#define flash_EBIU_AMBCTL0_WAT B0WAT_7
262#endif
263#if (flash_EBIU_AMBCTL_WAT == 6)
264#define flash_EBIU_AMBCTL0_WAT B0WAT_6
265#endif
266#if (flash_EBIU_AMBCTL_WAT == 5)
267#define flash_EBIU_AMBCTL0_WAT B0WAT_5
268#endif
269#if (flash_EBIU_AMBCTL_WAT == 4)
270#define flash_EBIU_AMBCTL0_WAT B0WAT_4
271#endif
272#if (flash_EBIU_AMBCTL_WAT == 3)
273#define flash_EBIU_AMBCTL0_WAT B0WAT_3
274#endif
275#if (flash_EBIU_AMBCTL_WAT == 2)
276#define flash_EBIU_AMBCTL0_WAT B0WAT_2
277#endif
278#if (flash_EBIU_AMBCTL_WAT == 1)
279#define flash_EBIU_AMBCTL0_WAT B0WAT_1
280#endif
281
282#if (flash_EBIU_AMBCTL_RAT > 14)
283#define flash_EBIU_AMBCTL0_RAT B0RAT_15
284#endif
285#if (flash_EBIU_AMBCTL_RAT == 14)
286#define flash_EBIU_AMBCTL0_RAT B0RAT_14
287#endif
288#if (flash_EBIU_AMBCTL_RAT == 13)
289#define flash_EBIU_AMBCTL0_RAT B0RAT_13
290#endif
291#if (flash_EBIU_AMBCTL_RAT == 12)
292#define flash_EBIU_AMBCTL0_RAT B0RAT_12
293#endif
294#if (flash_EBIU_AMBCTL_RAT == 11)
295#define flash_EBIU_AMBCTL0_RAT B0RAT_11
296#endif
297#if (flash_EBIU_AMBCTL_RAT == 10)
298#define flash_EBIU_AMBCTL0_RAT B0RAT_10
299#endif
300#if (flash_EBIU_AMBCTL_RAT == 9)
301#define flash_EBIU_AMBCTL0_RAT B0RAT_9
302#endif
303#if (flash_EBIU_AMBCTL_RAT == 8)
304#define flash_EBIU_AMBCTL0_RAT B0RAT_8
305#endif
306#if (flash_EBIU_AMBCTL_RAT == 7)
307#define flash_EBIU_AMBCTL0_RAT B0RAT_7
308#endif
309#if (flash_EBIU_AMBCTL_RAT == 6)
310#define flash_EBIU_AMBCTL0_RAT B0RAT_6
311#endif
312#if (flash_EBIU_AMBCTL_RAT == 5)
313#define flash_EBIU_AMBCTL0_RAT B0RAT_5
314#endif
315#if (flash_EBIU_AMBCTL_RAT == 4)
316#define flash_EBIU_AMBCTL0_RAT B0RAT_4
317#endif
318#if (flash_EBIU_AMBCTL_RAT == 3)
319#define flash_EBIU_AMBCTL0_RAT B0RAT_3
320#endif
321#if (flash_EBIU_AMBCTL_RAT == 2)
322#define flash_EBIU_AMBCTL0_RAT B0RAT_2
323#endif
324#if (flash_EBIU_AMBCTL_RAT == 1)
325#define flash_EBIU_AMBCTL0_RAT B0RAT_1
326#endif
327
328#define flash_EBIU_AMBCTL0 \
329 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
330 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
new file mode 100644
index 000000000000..2a808c1202bf
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -0,0 +1,175 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_537_H_
32#define _MEM_MAP_537_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50
51/* Level 1 Memory */
52
53/* Memory Map for ADSP-BF537 processors */
54
55#ifdef CONFIG_BLKFIN_CACHE
56#define BLKFIN_ICACHESIZE (16*1024)
57#else
58#define BLKFIN_ICACHESIZE (0*1024)
59#endif
60
61
62#ifdef CONFIG_BF537
63#define L1_CODE_START 0xFFA00000
64#define L1_DATA_A_START 0xFF800000
65#define L1_DATA_B_START 0xFF900000
66
67#define L1_CODE_LENGTH 0xC000
68
69#ifdef CONFIG_BLKFIN_DCACHE
70
71#ifdef CONFIG_BLKFIN_DCACHE_BANKA
72#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
73#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
74#define L1_DATA_B_LENGTH 0x8000
75#define BLKFIN_DCACHESIZE (16*1024)
76#define BLKFIN_DSUPBANKS 1
77#else
78#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
79#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
80#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
81#define BLKFIN_DCACHESIZE (32*1024)
82#define BLKFIN_DSUPBANKS 2
83#endif
84
85#else
86#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
87#define L1_DATA_A_LENGTH 0x8000
88#define L1_DATA_B_LENGTH 0x8000
89#define BLKFIN_DCACHESIZE (0*1024)
90#define BLKFIN_DSUPBANKS 0
91#endif /*CONFIG_BLKFIN_DCACHE*/
92
93#endif /*CONFIG_BF537*/
94
95/* Memory Map for ADSP-BF536 processors */
96
97#ifdef CONFIG_BF536
98#define L1_CODE_START 0xFFA00000
99#define L1_DATA_A_START 0xFF804000
100#define L1_DATA_B_START 0xFF904000
101
102#define L1_CODE_LENGTH 0xC000
103
104
105#ifdef CONFIG_BLKFIN_DCACHE
106
107#ifdef CONFIG_BLKFIN_DCACHE_BANKA
108#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
109#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
110#define L1_DATA_B_LENGTH 0x4000
111#define BLKFIN_DCACHESIZE (16*1024)
112#define BLKFIN_DSUPBANKS 1
113
114#else
115#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
116#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
117#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
118#define BLKFIN_DCACHESIZE (32*1024)
119#define BLKFIN_DSUPBANKS 2
120#endif
121
122#else
123#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
124#define L1_DATA_A_LENGTH 0x4000
125#define L1_DATA_B_LENGTH 0x4000
126#define BLKFIN_DCACHESIZE (0*1024)
127#define BLKFIN_DSUPBANKS 0
128#endif /*CONFIG_BLKFIN_DCACHE*/
129
130#endif
131
132/* Memory Map for ADSP-BF534 processors */
133
134#ifdef CONFIG_BF534
135#define L1_CODE_START 0xFFA00000
136#define L1_DATA_A_START 0xFF800000
137#define L1_DATA_B_START 0xFF900000
138
139#define L1_CODE_LENGTH 0xC000
140
141#ifdef CONFIG_BLKFIN_DCACHE
142
143#ifdef CONFIG_BLKFIN_DCACHE_BANKA
144#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
145#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
146#define L1_DATA_B_LENGTH 0x8000
147#define BLKFIN_DCACHESIZE (16*1024)
148#define BLKFIN_DSUPBANKS 1
149
150#else
151#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
152#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
153#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
154#define BLKFIN_DCACHESIZE (32*1024)
155#define BLKFIN_DSUPBANKS 2
156#endif
157
158#else
159#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
160#define L1_DATA_A_LENGTH 0x8000
161#define L1_DATA_B_LENGTH 0x8000
162#define BLKFIN_DCACHESIZE (0*1024)
163#define BLKFIN_DSUPBANKS 0
164#endif /*CONFIG_BLKFIN_DCACHE*/
165
166#endif
167
168/* Scratch Pad Memory */
169
170#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
171#define L1_SCRATCH_START 0xFFB00000
172#define L1_SCRATCH_LENGTH 0x1000
173#endif
174
175#endif /* _MEM_MAP_537_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 16:14:49 -0500