diff options
author | Graf Yang <graf.yang@analog.com> | 2008-04-23 16:43:14 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-04-23 16:43:14 -0400 |
commit | 6ed839423073251b513664fdadb180634aed704b (patch) | |
tree | 073350299070ba091f4fb4fb146b9a931edc44b8 /include/asm-blackfin/mach-bf537 | |
parent | db68254f0639a357309f02cf8707490265fa7a31 (diff) |
[Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Cc: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf537')
-rw-r--r-- | include/asm-blackfin/mach-bf537/blackfin.h | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h index 53fcfa3408d0..4f10ee0ae10d 100644 --- a/include/asm-blackfin/mach-bf537/blackfin.h +++ b/include/asm-blackfin/mach-bf537/blackfin.h | |||
@@ -82,8 +82,6 @@ | |||
82 | #define STATUS_P1 0x02 | 82 | #define STATUS_P1 0x02 |
83 | #define STATUS_P0 0x01 | 83 | #define STATUS_P0 0x01 |
84 | 84 | ||
85 | /* UART 0*/ | ||
86 | |||
87 | /* DMA Channnel */ | 85 | /* DMA Channnel */ |
88 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() | 86 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() |
89 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) | 87 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) |
@@ -106,37 +104,37 @@ | |||
106 | /* MMR Registers*/ | 104 | /* MMR Registers*/ |
107 | #define bfin_read_UART_THR() bfin_read_UART0_THR() | 105 | #define bfin_read_UART_THR() bfin_read_UART0_THR() |
108 | #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) | 106 | #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) |
109 | #define UART_THR UART0_THR | 107 | #define BFIN_UART_THR UART0_THR |
110 | #define bfin_read_UART_RBR() bfin_read_UART0_RBR() | 108 | #define bfin_read_UART_RBR() bfin_read_UART0_RBR() |
111 | #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) | 109 | #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) |
112 | #define UART_RBR UART0_RBR | 110 | #define BFIN_UART_RBR UART0_RBR |
113 | #define bfin_read_UART_DLL() bfin_read_UART0_DLL() | 111 | #define bfin_read_UART_DLL() bfin_read_UART0_DLL() |
114 | #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) | 112 | #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) |
115 | #define UART_DLL UART0_DLL | 113 | #define BFIN_UART_DLL UART0_DLL |
116 | #define bfin_read_UART_IER() bfin_read_UART0_IER() | 114 | #define bfin_read_UART_IER() bfin_read_UART0_IER() |
117 | #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) | 115 | #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) |
118 | #define UART_IER UART0_IER | 116 | #define BFIN_UART_IER UART0_IER |
119 | #define bfin_read_UART_DLH() bfin_read_UART0_DLH() | 117 | #define bfin_read_UART_DLH() bfin_read_UART0_DLH() |
120 | #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) | 118 | #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) |
121 | #define UART_DLH UART0_DLH | 119 | #define BFIN_UART_DLH UART0_DLH |
122 | #define bfin_read_UART_IIR() bfin_read_UART0_IIR() | 120 | #define bfin_read_UART_IIR() bfin_read_UART0_IIR() |
123 | #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) | 121 | #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) |
124 | #define UART_IIR UART0_IIR | 122 | #define BFIN_UART_IIR UART0_IIR |
125 | #define bfin_read_UART_LCR() bfin_read_UART0_LCR() | 123 | #define bfin_read_UART_LCR() bfin_read_UART0_LCR() |
126 | #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) | 124 | #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) |
127 | #define UART_LCR UART0_LCR | 125 | #define BFIN_UART_LCR UART0_LCR |
128 | #define bfin_read_UART_MCR() bfin_read_UART0_MCR() | 126 | #define bfin_read_UART_MCR() bfin_read_UART0_MCR() |
129 | #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) | 127 | #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) |
130 | #define UART_MCR UART0_MCR | 128 | #define BFIN_UART_MCR UART0_MCR |
131 | #define bfin_read_UART_LSR() bfin_read_UART0_LSR() | 129 | #define bfin_read_UART_LSR() bfin_read_UART0_LSR() |
132 | #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) | 130 | #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) |
133 | #define UART_LSR UART0_LSR | 131 | #define BFIN_UART_LSR UART0_LSR |
134 | #define bfin_read_UART_SCR() bfin_read_UART0_SCR() | 132 | #define bfin_read_UART_SCR() bfin_read_UART0_SCR() |
135 | #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) | 133 | #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) |
136 | #define UART_SCR UART0_SCR | 134 | #define BFIN_UART_SCR UART0_SCR |
137 | #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() | 135 | #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() |
138 | #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) | 136 | #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) |
139 | #define UART_GCTL UART0_GCTL | 137 | #define BFIN_UART_GCTL UART0_GCTL |
140 | 138 | ||
141 | /* DPMC*/ | 139 | /* DPMC*/ |
142 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | 140 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() |