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authorSonic Zhang <sonic.zhang@analog.com>2008-04-24 15:28:10 -0400
committerBryan Wu <cooloney@kernel.org>2008-04-24 15:28:10 -0400
commit4d555630704d3f6c0257dde3e622f9295f221c8b (patch)
tree8b53f8f2acf44ca00dfe159a79b7c4ed5880795f /include/asm-blackfin/mach-bf537
parent18628e4375264edb53e6d9aaaf91f1a480019304 (diff)
[Blackfin] arch: Update anomaly list.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf537')
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h17
1 files changed, 16 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 746a794b3119..a6b08facb242 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List 10 * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -132,10 +132,24 @@
132#define ANOMALY_05000322 (1) 132#define ANOMALY_05000322 (1)
133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) 134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
135/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */
136#define ANOMALY_05000350 (__SILICON_REVISION__ < 3)
137/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
138#define ANOMALY_05000355 (1)
135/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 139/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
136#define ANOMALY_05000357 (1) 140#define ANOMALY_05000357 (1)
137/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ 141/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
138#define ANOMALY_05000359 (1) 142#define ANOMALY_05000359 (1)
143/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
144#define ANOMALY_05000366 (1)
145/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
146#define ANOMALY_05000371 (1)
147/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
148#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3)
149/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
150#define ANOMALY_05000403 (1)
151
152
139 153
140/* Anomalies that don't exist on this proc */ 154/* Anomalies that don't exist on this proc */
141#define ANOMALY_05000125 (0) 155#define ANOMALY_05000125 (0)
@@ -146,5 +160,6 @@
146#define ANOMALY_05000266 (0) 160#define ANOMALY_05000266 (0)
147#define ANOMALY_05000311 (0) 161#define ANOMALY_05000311 (0)
148#define ANOMALY_05000323 (0) 162#define ANOMALY_05000323 (0)
163#define ANOMALY_05000363 (0)
149 164
150#endif 165#endif