diff options
author | Mike Frysinger <michael.frysinger@analog.com> | 2007-12-24 06:40:05 -0500 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2007-12-24 06:40:05 -0500 |
commit | 0bcfd70ea11a5d6f2362be463513a60245a62baf (patch) | |
tree | fdf47e68cc5fc916da5d985f797b262c36997c4e /include/asm-blackfin/mach-bf537 | |
parent | 4c195ad88b7df54b2e7340dec3446aee6ca84cd1 (diff) |
[Blackfin] serial driver: fix bug - cache the bits of the LSR on systems where the LSR is read-to-clear
Cache the bits of the LSR on systems where the LSR is read-to-clear
so that we can safely read the LSR in random places. this fixes
older parts where break/framing/parity/overflow was not being detected
at all in PIO mode, and this fixes newer parts where
break/framing/parity/overflow was being reported all the time
without being cleared.
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf537')
-rw-r--r-- | include/asm-blackfin/mach-bf537/bfin_serial_5xx.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index 86e45c379838..f18c517cc935 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h | |||
@@ -23,7 +23,6 @@ | |||
23 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) | 23 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) |
24 | #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) | 24 | #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) |
25 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) | 25 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) |
26 | #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) | ||
27 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) | 26 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) |
28 | 27 | ||
29 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) | 28 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) |
@@ -58,6 +57,7 @@ | |||
58 | struct bfin_serial_port { | 57 | struct bfin_serial_port { |
59 | struct uart_port port; | 58 | struct uart_port port; |
60 | unsigned int old_status; | 59 | unsigned int old_status; |
60 | unsigned int lsr; | ||
61 | #ifdef CONFIG_SERIAL_BFIN_DMA | 61 | #ifdef CONFIG_SERIAL_BFIN_DMA |
62 | int tx_done; | 62 | int tx_done; |
63 | int tx_count; | 63 | int tx_count; |
@@ -76,6 +76,23 @@ struct bfin_serial_port { | |||
76 | #endif | 76 | #endif |
77 | }; | 77 | }; |
78 | 78 | ||
79 | /* The hardware clears the LSR bits upon read, so we need to cache | ||
80 | * some of the more fun bits in software so they don't get lost | ||
81 | * when checking the LSR in other code paths (TX). | ||
82 | */ | ||
83 | static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) | ||
84 | { | ||
85 | unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); | ||
86 | uart->lsr |= (lsr & (BI|FE|PE|OE)); | ||
87 | return lsr | uart->lsr; | ||
88 | } | ||
89 | |||
90 | static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) | ||
91 | { | ||
92 | uart->lsr = 0; | ||
93 | bfin_write16(uart->port.membase + OFFSET_LSR, -1); | ||
94 | } | ||
95 | |||
79 | struct bfin_serial_port bfin_serial_ports[NR_PORTS]; | 96 | struct bfin_serial_port bfin_serial_ports[NR_PORTS]; |
80 | struct bfin_serial_res { | 97 | struct bfin_serial_res { |
81 | unsigned long uart_base_addr; | 98 | unsigned long uart_base_addr; |