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authorMichael Hennerich <michael.hennerich@analog.com>2008-05-09 12:11:59 -0400
committerBryan Wu <cooloney@kernel.org>2008-05-09 12:11:59 -0400
commit56f87713022a6bdf00b0a50d086fdaddb54e8e5c (patch)
tree7687e2bcf5bcad67f14367f4208e001cd490010c /include/asm-blackfin/mach-bf537/irq.h
parente4f7c0bf1f2e8a1b184a33ab60e874391d70f86c (diff)
[Blackfin] arch: remove useless IRQ_SW_INT defines
IRQ_SW_INT1 and IRQ_SW_INT2 obsolete: Remove useless defines Fix SYS_IRQS Keep numbering scheme, so we don't break existing configurations. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf537/irq.h')
-rw-r--r--include/asm-blackfin/mach-bf537/irq.h35
1 files changed, 16 insertions, 19 deletions
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index be6f2ff77f31..2e68a8a1e730 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -34,24 +34,23 @@
34 34
35/* 35/*
36 * Interrupt source definitions 36 * Interrupt source definitions
37 Event Source Core Event Name 37 * Event Source Core Event Name
38Core Emulation ** 38 * Core Emulation **
39 Events (highest priority) EMU 0 39 * Events (highest priority) EMU 0
40 Reset RST 1 40 * Reset RST 1
41 NMI NMI 2 41 * NMI NMI 2
42 Exception EVX 3 42 * Exception EVX 3
43 Reserved -- 4 43 * Reserved -- 4
44 Hardware Error IVHW 5 44 * Hardware Error IVHW 5
45 Core Timer IVTMR 6 * 45 * Core Timer IVTMR 6
46 46 * .....
47..... 47 *
48 48 * Softirq IVG14
49 Software Interrupt 1 IVG14 31 49 * System Call --
50 Software Interrupt 2 -- 50 * (lowest priority) IVG15
51 (lowest priority) IVG15 32 *
52 */ 51 */
53 52
54#define SYS_IRQS 41 53#define SYS_IRQS 39
55#define NR_PERI_INTS 32 54#define NR_PERI_INTS 32
56 55
57/* The ABSTRACT IRQ definitions */ 56/* The ABSTRACT IRQ definitions */
@@ -95,10 +94,8 @@ Core Emulation **
95#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ 94#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
96#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ 95#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
97#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ 96#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
98#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ 97#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
99#define IRQ_WATCH 38 /*Watch Dog Timer */ 98#define IRQ_WATCH 38 /*Watch Dog Timer */
100#define IRQ_SW_INT1 40 /*Software Int 1 */
101#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */
102 99
103#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ 100#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
104#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ 101#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */