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authorBryan Wu <bryan.wu@analog.com>2007-05-21 06:09:31 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-21 12:50:23 -0400
commit19381f024b01413d83cec1655c3fc4c9c09ae274 (patch)
tree4ba1d63900e031c97130638c2d678aaf15c3d37e /include/asm-blackfin/mach-bf537/defBF534.h
parentc09c4e006590210001ced90d59e62182bfd396f9 (diff)
Blackfin arch: update blackfin header files to latest one in VDSP.
a) add new processor BF52x/BF54x header files b) update blackfin BF533/BF537/BF561 header files to latest one in VDSP. c) scrub watchdog/rtc masks from headers as we dont need/want them (too generic and the drivers dont use them) Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf537/defBF534.h')
-rw-r--r--include/asm-blackfin/mach-bf537/defBF534.h90
1 files changed, 57 insertions, 33 deletions
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
index e605e9709004..1859f2fee5a7 100644
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -216,8 +216,12 @@
216#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 216#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
217 217
218/* DMA Traffic Control Registers */ 218/* DMA Traffic Control Registers */
219#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ 219#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
220#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 220#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
221
222/* Alternate deprecated register names (below) provided for backwards code compatibility */
223#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
224#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
221 225
222/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 226/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
223#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 227#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -563,7 +567,7 @@
563#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ 567#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
564#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ 568#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
565#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ 569#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
566#define CAN_SFCMVER 0xFFC02AA8 /* Version Code Register */ 570
567#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ 571#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
568#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ 572#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
569#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ 573#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
@@ -1026,10 +1030,11 @@
1026#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 1030#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
1027 1031
1028#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 1032#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1029#define PHYWE 0x0200 /* Enable PHY Wakeup From Hibernate */ 1033#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1030#define CANWE 0x0400 /* Enable CAN Wakeup From Hibernate */ 1034#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
1031#define PHYCLKOE 0x4000 /* PHY Clock Output Enable */ 1035#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
1032#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */ 1036#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
1037#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
1033 1038
1034/* PLL_STAT Masks */ 1039/* PLL_STAT Masks */
1035#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 1040#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
@@ -1050,7 +1055,7 @@
1050#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 1055#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1051 1056
1052/* SYSCR Masks */ 1057/* SYSCR Masks */
1053#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ 1058#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
1054#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ 1059#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1055 1060
1056/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ 1061/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
@@ -1107,19 +1112,9 @@
1107#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1112#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1108#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1113#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1109 1114
1110/* *************** WATCHDOG TIMER MASKS *******************************************/
1111/* WDOG_CTL Masks */
1112#define WDOG_RESET 0x0000 /* Generate Reset Event */
1113#define WDOG_NMI 0x0002 /* Generate Non-Maskable Interrupt (NMI) Event */
1114#define WDOG_GPI 0x0004 /* Generate General Purpose (GP) Interrupt */
1115#define WDOG_NONE 0x0006 /* Disable Watchdog Timer Interrupts */
1116#define TMR_EN 0x0FF0 /* Watchdog Counter Enable */
1117#define TMR_DIS 0x0AD0 /* Watchdog Counter Disable */
1118#define TRO 0x8000 /* Watchdog Expired */
1119
1120/* ************** UART CONTROLLER MASKS *************************/ 1115/* ************** UART CONTROLLER MASKS *************************/
1121/* UARTx_LCR Masks */ 1116/* UARTx_LCR Masks */
1122#define WLS(x) ((((x)&0x3)-5) & 0x03) /* Word Length Select */ 1117#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1123#define STB 0x04 /* Stop Bits */ 1118#define STB 0x04 /* Stop Bits */
1124#define PEN 0x08 /* Parity Enable */ 1119#define PEN 0x08 /* Parity Enable */
1125#define EPS 0x10 /* Even Parity Select */ 1120#define EPS 0x10 /* Even Parity Select */
@@ -1128,8 +1123,8 @@
1128#define DLAB 0x80 /* Divisor Latch Access */ 1123#define DLAB 0x80 /* Divisor Latch Access */
1129 1124
1130/* UARTx_MCR Mask */ 1125/* UARTx_MCR Mask */
1131#define LOOP 0x10 /* Loopback Mode Enable */ 1126#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1132 1127#define LOOP_ENA_P 0x04
1133/* UARTx_LSR Masks */ 1128/* UARTx_LSR Masks */
1134#define DR 0x01 /* Data Ready */ 1129#define DR 0x01 /* Data Ready */
1135#define OE 0x02 /* Overrun Error */ 1130#define OE 0x02 /* Overrun Error */
@@ -1229,10 +1224,10 @@
1229#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ 1224#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
1230#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ 1225#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
1231#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ 1226#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
1232#define TOVL_ERR0 0x00000010 /* Timer 0 Counter Overflow */ 1227#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
1233#define TOVL_ERR1 0x00000020 /* Timer 1 Counter Overflow */ 1228#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
1234#define TOVL_ERR2 0x00000040 /* Timer 2 Counter Overflow */ 1229#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
1235#define TOVL_ERR3 0x00000080 /* Timer 3 Counter Overflow */ 1230#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
1236#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ 1231#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
1237#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ 1232#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
1238#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ 1233#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
@@ -1241,15 +1236,24 @@
1241#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ 1236#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
1242#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ 1237#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
1243#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ 1238#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
1244#define TOVL_ERR4 0x00100000 /* Timer 4 Counter Overflow */ 1239#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
1245#define TOVL_ERR5 0x00200000 /* Timer 5 Counter Overflow */ 1240#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
1246#define TOVL_ERR6 0x00400000 /* Timer 6 Counter Overflow */ 1241#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
1247#define TOVL_ERR7 0x00800000 /* Timer 7 Counter Overflow */ 1242#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
1248#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ 1243#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
1249#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ 1244#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
1250#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ 1245#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1251#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ 1246#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1252 1247
1248/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1249#define TOVL_ERR0 TOVF_ERR0
1250#define TOVL_ERR1 TOVF_ERR1
1251#define TOVL_ERR2 TOVF_ERR2
1252#define TOVL_ERR3 TOVF_ERR3
1253#define TOVL_ERR4 TOVF_ERR4
1254#define TOVL_ERR5 TOVF_ERR5
1255#define TOVL_ERR6 TOVF_ERR6
1256#define TOVL_ERR7 TOVF_ERR7
1253/* TIMERx_CONFIG Masks */ 1257/* TIMERx_CONFIG Masks */
1254#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ 1258#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1255#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ 1259#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
@@ -1647,6 +1651,8 @@
1647#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ 1651#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1648#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ 1652#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1649#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ 1653#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1654#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1655#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1650#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ 1656#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1651#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ 1657#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1652#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ 1658#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
@@ -1859,8 +1865,10 @@
1859#define TXECNT 0xFF00 /* Transmit Error Counter */ 1865#define TXECNT 0xFF00 /* Transmit Error Counter */
1860 1866
1861/* CAN_INTR Masks */ 1867/* CAN_INTR Masks */
1862#define MBRIF 0x0001 /* Mailbox Receive Interrupt */ 1868#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
1863#define MBTIF 0x0002 /* Mailbox Transmit Interrupt */ 1869#define MBRIF MBRIRQ /* legacy */
1870#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
1871#define MBTIF MBTIRQ /* legacy */
1864#define GIRQ 0x0004 /* Global Interrupt */ 1872#define GIRQ 0x0004 /* Global Interrupt */
1865#define SMACK 0x0008 /* Sleep Mode Acknowledge */ 1873#define SMACK 0x0008 /* Sleep Mode Acknowledge */
1866#define CANTX 0x0040 /* CAN TX Bus Value */ 1874#define CANTX 0x0040 /* CAN TX Bus Value */
@@ -2445,8 +2453,8 @@
2445#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ 2453#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
2446 2454
2447#define PFDE 0x0008 /* Port F DMA Request Enable */ 2455#define PFDE 0x0008 /* Port F DMA Request Enable */
2448#define PGDE_UART 0x0000 /* Enable UART0 RX/TX */ 2456#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
2449#define PGDE_DMA 0x0008 /* Enable DMAR1:0 */ 2457#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
2450 2458
2451#define PFTE 0x0010 /* Port F Timer Enable */ 2459#define PFTE 0x0010 /* Port F Timer Enable */
2452#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ 2460#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
@@ -2498,4 +2506,20 @@
2498#define OI 0x4000 /* Overflow Interrupt Generated */ 2506#define OI 0x4000 /* Overflow Interrupt Generated */
2499#define BDI 0x8000 /* Block Done Interrupt Generated */ 2507#define BDI 0x8000 /* Block Done Interrupt Generated */
2500 2508
2509/* entry addresses of the user-callable Boot ROM functions */
2510
2511#define _BOOTROM_RESET 0xEF000000
2512#define _BOOTROM_FINAL_INIT 0xEF000002
2513#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
2514#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
2515#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
2516#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
2517#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
2518#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
2519#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
2520
2521/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
2522#define PGDE_UART PFDE_UART
2523#define PGDE_DMA PFDE_DMA
2524#define CKELOW SCKELOW
2501#endif /* _DEF_BF534_H */ 2525#endif /* _DEF_BF534_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 00:29:15 -0500