diff options
author | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-05-31 00:57:05 -0400 |
---|---|---|
committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-05-31 00:57:05 -0400 |
commit | 5bc65793cbf8da0d35f19ef025dda22887e79e80 (patch) | |
tree | 8291998abd73055de6f487fafa174ee2a5d3afee /include/asm-blackfin/mach-bf537/cdefBF534.h | |
parent | 6edae708bf77e012d855a7e2c7766f211d234f4f (diff) | |
parent | 3f0a6766e0cc5a577805732e5adb50a585c58175 (diff) |
[SCSI] Merge up to linux-2.6 head
Conflicts:
drivers/scsi/jazz_esp.c
Same changes made by both SCSI and SPARC trees: problem with UTF-8
conversion in the copyright.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf537/cdefBF534.h')
-rw-r--r-- | include/asm-blackfin/mach-bf537/cdefBF534.h | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h index 7b658c175f85..84e58fa73dce 100644 --- a/include/asm-blackfin/mach-bf537/cdefBF534.h +++ b/include/asm-blackfin/mach-bf537/cdefBF534.h | |||
@@ -51,12 +51,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
51 | { | 51 | { |
52 | unsigned long flags, iwr; | 52 | unsigned long flags, iwr; |
53 | 53 | ||
54 | bfin_write16(VR_CTL, val); | ||
55 | __builtin_bfin_ssync(); | ||
56 | /* Enable the PLL Wakeup bit in SIC IWR */ | 54 | /* Enable the PLL Wakeup bit in SIC IWR */ |
57 | iwr = bfin_read32(SIC_IWR); | 55 | iwr = bfin_read32(SIC_IWR); |
58 | /* Only allow PPL Wakeup) */ | 56 | /* Only allow PPL Wakeup) */ |
59 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | 57 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); |
58 | |||
59 | bfin_write16(VR_CTL, val); | ||
60 | __builtin_bfin_ssync(); | ||
61 | |||
60 | local_irq_save(flags); | 62 | local_irq_save(flags); |
61 | asm("IDLE;"); | 63 | asm("IDLE;"); |
62 | local_irq_restore(flags); | 64 | local_irq_restore(flags); |
@@ -73,7 +75,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
73 | #define bfin_write_SWRST(val) bfin_write16(SWRST,val) | 75 | #define bfin_write_SWRST(val) bfin_write16(SWRST,val) |
74 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | 76 | #define bfin_read_SYSCR() bfin_read16(SYSCR) |
75 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) | 77 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) |
76 | #define pSIC_RVECT ((void * volatile *)SIC_RVECT) | ||
77 | #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) | 78 | #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) |
78 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val) | 79 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val) |
79 | #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) | 80 | #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) |
@@ -398,10 +399,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
398 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) | 399 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) |
399 | 400 | ||
400 | /* DMA Traffic Control Registers */ | 401 | /* DMA Traffic Control Registers */ |
401 | #define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) | 402 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) |
403 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) | ||
404 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | ||
405 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) | ||
406 | |||
407 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
402 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | 408 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) |
403 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) | 409 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) |
404 | #define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) | ||
405 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | 410 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) |
406 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) | 411 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) |
407 | 412 | ||
@@ -1076,8 +1081,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
1076 | #define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val) | 1081 | #define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val) |
1077 | #define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) | 1082 | #define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) |
1078 | #define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val) | 1083 | #define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val) |
1079 | #define bfin_read_CAN_SFCMVER2() bfin_read16(CAN_SFCMVER2) | ||
1080 | #define bfin_write_CAN_SFCMVER2(val) bfin_write16(CAN_SFCMVER2,val) | ||
1081 | 1084 | ||
1082 | /* Mailbox Acceptance Masks */ | 1085 | /* Mailbox Acceptance Masks */ |
1083 | #define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) | 1086 | #define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) |