diff options
author | Graf Yang <graf.yang@analog.com> | 2008-04-24 15:09:15 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-04-24 15:09:15 -0400 |
commit | 5be36d22b28f01e5074f78b29aa6128da0a53641 (patch) | |
tree | 1fda8bcb0680eda6a826fc3753ee8c9f52a2c75b /include/asm-blackfin/mach-bf537/blackfin.h | |
parent | 37b6972ad8fb08d438fd600888aff212b1b193b0 (diff) |
[Blackfin] arch: add Blackfin on-chip SIR IrDA driver support
- add platform device resources in board files
- add new bfin_sir.h to each machines
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf537/blackfin.h')
-rw-r--r-- | include/asm-blackfin/mach-bf537/blackfin.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h index 4f10ee0ae10d..cffc786b2a2b 100644 --- a/include/asm-blackfin/mach-bf537/blackfin.h +++ b/include/asm-blackfin/mach-bf537/blackfin.h | |||
@@ -136,6 +136,21 @@ | |||
136 | #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) | 136 | #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) |
137 | #define BFIN_UART_GCTL UART0_GCTL | 137 | #define BFIN_UART_GCTL UART0_GCTL |
138 | 138 | ||
139 | #define BFIN_UART_NR_PORTS 2 | ||
140 | |||
141 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | ||
142 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | ||
143 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | ||
144 | #define OFFSET_IER 0x04 /* Interrupt Enable Register */ | ||
145 | #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | ||
146 | #define OFFSET_IIR 0x08 /* Interrupt Identification Register */ | ||
147 | #define OFFSET_LCR 0x0C /* Line Control Register */ | ||
148 | #define OFFSET_MCR 0x10 /* Modem Control Register */ | ||
149 | #define OFFSET_LSR 0x14 /* Line Status Register */ | ||
150 | #define OFFSET_MSR 0x18 /* Modem Status Register */ | ||
151 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | ||
152 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | ||
153 | |||
139 | /* DPMC*/ | 154 | /* DPMC*/ |
140 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | 155 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() |
141 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | 156 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) |