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authorBryan Wu <cooloney@kernel.org>2008-08-26 22:51:02 -0400
committerBryan Wu <cooloney@kernel.org>2008-08-26 22:51:02 -0400
commit639f6571458948b5112be2cf00c0c2c04db2897d (patch)
treea4dd7af33d0e92c935ba1e904f6fb7e923ac825e /include/asm-blackfin/mach-bf537/bf537.h
parent3d9b7a5ce534f3963afcf8f4777267e5899fe007 (diff)
Blackfin arch: move include/asm-blackfin header files to arch/blackfin
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf537/bf537.h')
-rw-r--r--include/asm-blackfin/mach-bf537/bf537.h141
1 files changed, 0 insertions, 141 deletions
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
deleted file mode 100644
index cfe2a221112e..000000000000
--- a/include/asm-blackfin/mach-bf537/bf537.h
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/bf537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF537_H__
31#define __MACH_BF537_H__
32
33#define SUPPORTED_REVID 2
34
35/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
36
37#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
38#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
39#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
42#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
43#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
44
45#define OFFSET_(x) ((x) & 0x0000FFFF)
46
47/*some misc defines*/
48#define IMASK_IVG15 0x8000
49#define IMASK_IVG14 0x4000
50#define IMASK_IVG13 0x2000
51#define IMASK_IVG12 0x1000
52
53#define IMASK_IVG11 0x0800
54#define IMASK_IVG10 0x0400
55#define IMASK_IVG9 0x0200
56#define IMASK_IVG8 0x0100
57
58#define IMASK_IVG7 0x0080
59#define IMASK_IVGTMR 0x0040
60#define IMASK_IVGHW 0x0020
61
62/***************************/
63
64
65#define BFIN_DSUBBANKS 4
66#define BFIN_DWAYS 2
67#define BFIN_DLINES 64
68#define BFIN_ISUBBANKS 4
69#define BFIN_IWAYS 4
70#define BFIN_ILINES 32
71
72#define WAY0_L 0x1
73#define WAY1_L 0x2
74#define WAY01_L 0x3
75#define WAY2_L 0x4
76#define WAY02_L 0x5
77#define WAY12_L 0x6
78#define WAY012_L 0x7
79
80#define WAY3_L 0x8
81#define WAY03_L 0x9
82#define WAY13_L 0xA
83#define WAY013_L 0xB
84
85#define WAY32_L 0xC
86#define WAY320_L 0xD
87#define WAY321_L 0xE
88#define WAYALL_L 0xF
89
90#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
91
92/********************************* EBIU Settings ************************************/
93#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
94#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
95
96#ifdef CONFIG_C_AMBEN_ALL
97#define V_AMBEN AMBEN_ALL
98#endif
99#ifdef CONFIG_C_AMBEN
100#define V_AMBEN 0x0
101#endif
102#ifdef CONFIG_C_AMBEN_B0
103#define V_AMBEN AMBEN_B0
104#endif
105#ifdef CONFIG_C_AMBEN_B0_B1
106#define V_AMBEN AMBEN_B0_B1
107#endif
108#ifdef CONFIG_C_AMBEN_B0_B1_B2
109#define V_AMBEN AMBEN_B0_B1_B2
110#endif
111#ifdef CONFIG_C_AMCKEN
112#define V_AMCKEN AMCKEN
113#else
114#define V_AMCKEN 0x0
115#endif
116#ifdef CONFIG_C_CDPRIO
117#define V_CDPRIO 0x100
118#else
119#define V_CDPRIO 0x0
120#endif
121
122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
123
124#ifdef CONFIG_BF537
125#define CPU "BF537"
126#define CPUID 0x027c8000
127#endif
128#ifdef CONFIG_BF536
129#define CPU "BF536"
130#define CPUID 0x027c8000
131#endif
132#ifdef CONFIG_BF534
133#define CPU "BF534"
134#define CPUID 0x027c6000
135#endif
136#ifndef CPU
137#define CPU "UNKNOWN"
138#define CPUID 0x0
139#endif
140
141#endif /* __MACH_BF537_H__ */