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authorBryan Wu <bryan.wu@analog.com>2007-05-06 17:50:22 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-07 15:12:58 -0400
commit1394f03221790a988afc3e4b3cb79f2e477246a9 (patch)
tree2c1963c9a4f2d84a5e021307fde240c5d567cf70 /include/asm-blackfin/mach-bf533
parent73243284463a761e04d69d22c7516b2be7de096c (diff)
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf533')
-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h175
-rw-r--r--include/asm-blackfin/mach-bf533/bf533.h306
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h108
-rw-r--r--include/asm-blackfin/mach-bf533/blackfin.h45
-rw-r--r--include/asm-blackfin/mach-bf533/cdefBF532.h706
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h1175
-rw-r--r--include/asm-blackfin/mach-bf533/dma.h54
-rw-r--r--include/asm-blackfin/mach-bf533/irq.h177
-rw-r--r--include/asm-blackfin/mach-bf533/mem_init.h316
-rw-r--r--include/asm-blackfin/mach-bf533/mem_map.h168
10 files changed, 3230 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
new file mode 100644
index 000000000000..a84d3909345e
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -0,0 +1,175 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/* This file shoule be up to date with:
32 * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
33 * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
34 * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
35 */
36
37#ifndef _MACH_ANOMALY_H_
38#define _MACH_ANOMALY_H_
39
40/* We do not support 0.1 or 0.2 silicon - sorry */
41#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
42#error Kernel will not work on BF533 Version 0.1 or 0.2
43#endif
44
45/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
46#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
47#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
48 slot1 and store of a P register in slot 2 is not
49 supported */
50#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
51 every corresponding match */
52#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
53 Channel DMA stops */
54#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
55 registers. */
56#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
57 upper bits*/
58#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
59#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
60 syncs */
61#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
62 functional */
63#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
64 state */
65#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
66#define ANOMALY_05000272 /* Certain data cache write through modes fail for
67 VDDint <=0.9V */
68#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
69#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
70 an edge is detected may clear interrupt */
71#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
72 DMA system instability */
73#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
74 not restored */
75#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
76 control */
77#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
78 killed in a particular stage*/
79#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
80 registers are interrupted */
81#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/
82
83#endif
84
85/* These issues only occur on 0.3 or 0.4 BF533 */
86#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
87#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
88 updated at the same time. */
89#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
90 Cache Fill can be corrupted after or during
91 Instruction DMA if certain core stalls exist */
92#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
93 Purpose TX or RX modes */
94#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
95 preceding memory read */
96#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
97 inactive channels in certain conditions */
98#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
99 situation */
100#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
101#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
102#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
103 data*/
104#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
105 Differences in certain Conditions */
106#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
107#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
108 hardware reset */
109#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
110 IDLE around a Change of Control causes
111 unpredictable results */
112#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
113 shadow of a conditional branch */
114#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
115 errors */
116#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
117#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
118 interrupt not functional */
119#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
120 loops may cause the instruction fetch unit to
121 malfunction */
122#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
123 the ICPLB Data registers differ */
124#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
125#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
126#define ANOMALY_05000262 /* Stores to data cache may be lost */
127#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
128#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
129 instruction will cause an infinite stall in the
130 second to last instruction in a hardware loop */
131#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
132 SPORT external receive and transmit clocks. */
133#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
134 internal voltage regulator (VDDint) to increase. */
135#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
136 internal voltage regulator (VDDint) to decrease */
137#endif
138
139/* These issues are only on 0.4 silicon */
140#if (defined(CONFIG_BF_REV_0_4))
141#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
142#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
143 (TDM) */
144#endif
145
146/* These issues are only on 0.3 silicon */
147#if defined(CONFIG_BF_REV_0_3)
148#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
149 External Frame Syncs */
150#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
151 Instruction or Data Fetches, or by Fetches at the
152 boundary of reserved memory space */
153#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
154 when polarity setting is changed */
155#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
156 corruption */
157#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
158 fix */
159#define ANOMALY_05000201 /* Receive frame sync not ignored during active
160 frames in sport MCM */
161#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
162 stopping */
163#if defined(CONFIG_BF533)
164#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
165 allocate cache lines on reads only mode */
166#endif /* CONFIG_BF533 */
167#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
168#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
169 instructions */
170#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
171 Sync Transmit Mode */
172#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
173#endif
174
175#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h
new file mode 100644
index 000000000000..185fc1284858
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/bf533.h
@@ -0,0 +1,306 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/bf533.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF533_H__
31#define __MACH_BF533_H__
32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54
55#define BLKFIN_DSUBBANKS 4
56#define BLKFIN_DWAYS 2
57#define BLKFIN_DLINES 64
58#define BLKFIN_ISUBBANKS 4
59#define BLKFIN_IWAYS 4
60#define BLKFIN_ILINES 32
61
62#define WAY0_L 0x1
63#define WAY1_L 0x2
64#define WAY01_L 0x3
65#define WAY2_L 0x4
66#define WAY02_L 0x5
67#define WAY12_L 0x6
68#define WAY012_L 0x7
69
70#define WAY3_L 0x8
71#define WAY03_L 0x9
72#define WAY13_L 0xA
73#define WAY013_L 0xB
74
75#define WAY32_L 0xC
76#define WAY320_L 0xD
77#define WAY321_L 0xE
78#define WAYALL_L 0xF
79
80#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
81
82/* IAR0 BIT FIELDS*/
83#define RTC_ERROR_BIT 0x0FFFFFFF
84#define UART_ERROR_BIT 0xF0FFFFFF
85#define SPORT1_ERROR_BIT 0xFF0FFFFF
86#define SPI_ERROR_BIT 0xFFF0FFFF
87#define SPORT0_ERROR_BIT 0xFFFF0FFF
88#define PPI_ERROR_BIT 0xFFFFF0FF
89#define DMA_ERROR_BIT 0xFFFFFF0F
90#define PLLWAKE_ERROR_BIT 0xFFFFFFFF
91
92/* IAR1 BIT FIELDS*/
93#define DMA7_UARTTX_BIT 0x0FFFFFFF
94#define DMA6_UARTRX_BIT 0xF0FFFFFF
95#define DMA5_SPI_BIT 0xFF0FFFFF
96#define DMA4_SPORT1TX_BIT 0xFFF0FFFF
97#define DMA3_SPORT1RX_BIT 0xFFFF0FFF
98#define DMA2_SPORT0TX_BIT 0xFFFFF0FF
99#define DMA1_SPORT0RX_BIT 0xFFFFFF0F
100#define DMA0_PPI_BIT 0xFFFFFFFF
101
102/* IAR2 BIT FIELDS*/
103#define WDTIMER_BIT 0x0FFFFFFF
104#define MEMDMA1_BIT 0xF0FFFFFF
105#define MEMDMA0_BIT 0xFF0FFFFF
106#define PFB_BIT 0xFFF0FFFF
107#define PFA_BIT 0xFFFF0FFF
108#define TIMER2_BIT 0xFFFFF0FF
109#define TIMER1_BIT 0xFFFFFF0F
110#define TIMER0_BIT 0xFFFFFFFF
111
112/********************************* EBIU Settings ************************************/
113#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
114#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
115
116#ifdef CONFIG_C_AMBEN_ALL
117#define V_AMBEN AMBEN_ALL
118#endif
119#ifdef CONFIG_C_AMBEN
120#define V_AMBEN 0x0
121#endif
122#ifdef CONFIG_C_AMBEN_B0
123#define V_AMBEN AMBEN_B0
124#endif
125#ifdef CONFIG_C_AMBEN_B0_B1
126#define V_AMBEN AMBEN_B0_B1
127#endif
128#ifdef CONFIG_C_AMBEN_B0_B1_B2
129#define V_AMBEN AMBEN_B0_B1_B2
130#endif
131#ifdef CONFIG_C_AMCKEN
132#define V_AMCKEN AMCKEN
133#else
134#define V_AMCKEN 0x0
135#endif
136#ifdef CONFIG_C_CDPRIO
137#define V_CDPRIO 0x100
138#else
139#define V_CDPRIO 0x0
140#endif
141
142#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
143
144#define MAX_VC 650000000
145#define MIN_VC 50000000
146
147#ifdef CONFIG_BFIN_KERNEL_CLOCK
148/********************************PLL Settings **************************************/
149#if (CONFIG_VCO_MULT < 0)
150#error "VCO Multiplier is less than 0. Please select a different value"
151#endif
152
153#if (CONFIG_VCO_MULT == 0)
154#error "VCO Multiplier should be greater than 0. Please select a different value"
155#endif
156
157#if (CONFIG_VCO_MULT > 64)
158#error "VCO Multiplier is more than 64. Please select a different value"
159#endif
160
161#ifndef CONFIG_CLKIN_HALF
162#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
163#else
164#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
165#endif
166
167#ifndef CONFIG_PLL_BYPASS
168#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
169#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
170#else
171#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
172#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
173#endif
174
175#if (CONFIG_SCLK_DIV < 1)
176#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
177#endif
178
179#if (CONFIG_SCLK_DIV > 15)
180#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
181#endif
182
183#if (CONFIG_CCLK_DIV != 1)
184#if (CONFIG_CCLK_DIV != 2)
185#if (CONFIG_CCLK_DIV != 4)
186#if (CONFIG_CCLK_DIV != 8)
187#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
188#endif
189#endif
190#endif
191#endif
192
193#if (CONFIG_VCO_HZ > MAX_VC)
194#error "VCO selected is more than maximum value. Please change the VCO multipler"
195#endif
196
197#if (CONFIG_SCLK_HZ > 133000000)
198#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
199#endif
200
201#if (CONFIG_SCLK_HZ < 27000000)
202#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
203#endif
204
205#if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ)
206#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
207#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
208#error "Please select sclk less than cclk"
209#endif
210#endif
211#endif
212
213#if (CONFIG_CCLK_DIV == 1)
214#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
215#endif
216#if (CONFIG_CCLK_DIV == 2)
217#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
218#endif
219#if (CONFIG_CCLK_DIV == 4)
220#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
221#endif
222#if (CONFIG_CCLK_DIV == 8)
223#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
224#endif
225#ifndef CONFIG_CCLK_ACT_DIV
226#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
227#endif
228
229#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
230#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
231#endif
232
233#endif /* CONFIG_BFIN_KERNEL_CLOCK */
234
235#ifdef CONFIG_BF533
236#define CPU "BF533"
237#define CPUID 0x027a5000
238#endif
239#ifdef CONFIG_BF532
240#define CPU "BF532"
241#define CPUID 0x0275A000
242#endif
243#ifdef CONFIG_BF531
244#define CPU "BF531"
245#define CPUID 0x027a5000
246#endif
247#ifndef CPU
248#define CPU "UNKNOWN"
249#define CPUID 0x0
250#endif
251
252#if (CONFIG_MEM_SIZE % 4)
253#error "SDRAM mem size must be multible of 4MB"
254#endif
255
256#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
257#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
258#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
259#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
260
261/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
262
263#define ANOMALY_05000158_WORKAROUND 0x200
264#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
265#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
266 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
267#else /*Write Through */
268#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
269 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
270#endif
271
272#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
273#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
274#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
275#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
276
277#define SIZE_1K 0x00000400 /* 1K */
278#define SIZE_4K 0x00001000 /* 4K */
279#define SIZE_1M 0x00100000 /* 1M */
280#define SIZE_4M 0x00400000 /* 4M */
281
282#define MAX_CPLBS (16 * 2)
283
284/*
285* Number of required data CPLB switchtable entries
286* MEMSIZE / 4 (we mostly install 4M page size CPLBs
287* approx 16 for smaller 1MB page size CPLBs for allignment purposes
288* 1 for L1 Data Memory
289* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
290* 1 for ASYNC Memory
291*/
292
293
294#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
295
296/*
297* Number of required instruction CPLB switchtable entries
298* MEMSIZE / 4 (we mostly install 4M page size CPLBs
299* approx 12 for smaller 1MB page size CPLBs for allignment purposes
300* 1 for L1 Instruction Memory
301* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
302*/
303
304#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
305
306#endif /* __MACH_BF533_H__ */
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
new file mode 100644
index 000000000000..23bf76aa3451
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -0,0 +1,108 @@
1#include <linux/serial.h>
2#include <asm/dma.h>
3
4#define NR_PORTS 1
5
6#define OFFSET_THR 0x00 /* Transmit Holding register */
7#define OFFSET_RBR 0x00 /* Receive Buffer register */
8#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
9#define OFFSET_IER 0x04 /* Interrupt Enable Register */
10#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
11#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
12#define OFFSET_LCR 0x0C /* Line Control Register */
13#define OFFSET_MCR 0x10 /* Modem Control Register */
14#define OFFSET_LSR 0x14 /* Line Status Register */
15#define OFFSET_MSR 0x18 /* Modem Status Register */
16#define OFFSET_SCR 0x1C /* SCR Scratch Register */
17#define OFFSET_GCTL 0x24 /* Global Control Register */
18
19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
27
28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
30#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
32#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
33#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
34
35#ifdef CONFIG_BFIN_UART0_CTSRTS
36# define CONFIG_SERIAL_BFIN_CTSRTS
37# ifndef CONFIG_UART0_CTS_PIN
38# define CONFIG_UART0_CTS_PIN -1
39# endif
40# ifndef CONFIG_UART0_RTS_PIN
41# define CONFIG_UART0_RTS_PIN -1
42# endif
43#endif
44
45struct bfin_serial_port {
46 struct uart_port port;
47 unsigned int old_status;
48#ifdef CONFIG_SERIAL_BFIN_DMA
49 int tx_done;
50 int tx_count;
51 struct circ_buf rx_dma_buf;
52 struct timer_list rx_dma_timer;
53 int rx_dma_nrows;
54 unsigned int tx_dma_channel;
55 unsigned int rx_dma_channel;
56 struct work_struct tx_dma_workqueue;
57#else
58 struct work_struct cts_workqueue;
59#endif
60#ifdef CONFIG_SERIAL_BFIN_CTSRTS
61 int cts_pin;
62 int rts_pin;
63#endif
64};
65
66struct bfin_serial_port bfin_serial_ports[NR_PORTS];
67struct bfin_serial_res {
68 unsigned long uart_base_addr;
69 int uart_irq;
70#ifdef CONFIG_SERIAL_BFIN_DMA
71 unsigned int uart_tx_dma_channel;
72 unsigned int uart_rx_dma_channel;
73#endif
74#ifdef CONFIG_SERIAL_BFIN_CTSRTS
75 int uart_cts_pin;
76 int uart_rts_pin;
77#endif
78};
79
80struct bfin_serial_res bfin_serial_resource[] = {
81 0xFFC00400,
82 IRQ_UART_RX,
83#ifdef CONFIG_SERIAL_BFIN_DMA
84 CH_UART_TX,
85 CH_UART_RX,
86#endif
87#ifdef CONFIG_BFIN_UART0_CTSRTS
88 CONFIG_UART0_CTS_PIN,
89 CONFIG_UART0_RTS_PIN,
90#endif
91};
92
93
94int nr_ports = NR_PORTS;
95static void bfin_serial_hw_init(struct bfin_serial_port *uart)
96{
97
98#ifdef CONFIG_SERIAL_BFIN_CTSRTS
99 if (uart->cts_pin >= 0) {
100 gpio_request(uart->cts_pin, NULL);
101 gpio_direction_input(uart->cts_pin);
102 }
103 if (uart->rts_pin >= 0) {
104 gpio_request(uart->rts_pin, NULL);
105 gpio_direction_input(uart->rts_pin);
106 }
107#endif
108}
diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h
new file mode 100644
index 000000000000..e4384491e972
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/blackfin.h
@@ -0,0 +1,45 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MACH_BLACKFIN_H_
32#define _MACH_BLACKFIN_H_
33
34#define BF533_FAMILY
35
36#include "bf533.h"
37#include "mem_map.h"
38#include "defBF532.h"
39#include "anomaly.h"
40
41#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
42#include "cdefBF532.h"
43#endif
44
45#endif /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
new file mode 100644
index 000000000000..1d7c494ceb64
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/cdefBF532.h
@@ -0,0 +1,706 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/cdefBF532.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF532_H
32#define _CDEF_BF532_H
33/*
34#if !defined(__ADSPLPBLACKFIN__)
35#warning cdefBF532.h should only be included for 532 compatible chips.
36#endif
37*/
38/*include all Core registers and bit definitions*/
39#include "defBF532.h"
40
41/*include core specific register pointer definitions*/
42#include <asm/mach-common/cdef_LPBlackfin.h>
43
44#include <asm/system.h>
45
46/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
47#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
48#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
49#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
50#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
51#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
52#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
53#define bfin_read_CHIPID() bfin_read32(CHIPID)
54#define bfin_read_SWRST() bfin_read16(SWRST)
55#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
56#define bfin_read_SYSCR() bfin_read16(SYSCR)
57#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
58#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
59#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
60#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
61/* Writing to VR_CTL initiates a PLL relock sequence. */
62static __inline__ void bfin_write_VR_CTL(unsigned int val)
63{
64 unsigned long flags, iwr;
65
66 bfin_write16(VR_CTL, val);
67 __builtin_bfin_ssync();
68 /* Enable the PLL Wakeup bit in SIC IWR */
69 iwr = bfin_read32(SIC_IWR);
70 /* Only allow PPL Wakeup) */
71 bfin_write32(SIC_IWR, IWR_ENABLE(0));
72 local_irq_save(flags);
73 asm("IDLE;");
74 local_irq_restore(flags);
75 bfin_write32(SIC_IWR, iwr);
76}
77
78/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
79#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
80#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
81#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
82#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
83#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
84#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
85#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
86#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
87#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
88#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
89#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
90#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
91#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
92#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
93
94/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
95#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
96#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
97#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
98#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
99#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
100#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
101
102/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
103#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
104#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
105#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
106#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
107#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
108#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
109#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
110#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
111#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
112#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
113#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
114#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
115#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
116#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
117
118/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
119#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
120#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
121#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
122#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val)
123#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
124#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val)
125#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
126#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
127#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
128#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
129#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
130#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
131#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
132#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
133#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
134#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
135#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
136#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
137#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
138#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
139#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
140#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
141#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
142#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val)
143#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
144#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val)
145#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
146#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
147#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
148#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
149#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
150#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
151#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
152#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
153
154/* DMA Traffic controls */
155#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
156#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
157#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
158#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
159#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
160#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
161#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
162#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
163
164/* DMA Controller */
165#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
166#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
167#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
168#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
169#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
170#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
171#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
172#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
173#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
174#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
175#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
176#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
177#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
178#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
179#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
180#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
181#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
182#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
183#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
184#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
185#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
186#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
187#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
188#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
189#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
190#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
191
192#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
193#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
194#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
195#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
196#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
197#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
198#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
199#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
200#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
201#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
202#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
203#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
204#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
205#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
206#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
207#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
208#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
209#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
210#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
211#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
212#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
213#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
214#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
215#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
216#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
217#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
218
219#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
220#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
221#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
222#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
223#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
224#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
225#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
226#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
227#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
228#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
229#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
230#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
231#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
232#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
233#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
234#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
235#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
236#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
237#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
238#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
239#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
240#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
241#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
242#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
243#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
244#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
245
246#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
247#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
248#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
249#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
250#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
251#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
252#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
253#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
254#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
255#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
256#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
257#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
258#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
259#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
260#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
261#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
262#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
263#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
264#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
265#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
266#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
267#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
268#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
269#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
270#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
271#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
272
273#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
274#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
275#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
276#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
277#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
278#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
279#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
280#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
281#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
282#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
283#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
284#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
285#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
286#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
287#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
288#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
289#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
290#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
291#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
292#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
293#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
294#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
295#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
296#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
297#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
298#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
299
300#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
301#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
302#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
303#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
304#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
305#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
306#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
307#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
308#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
309#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
310#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
311#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
312#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
313#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
314#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
315#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
316#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
317#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
318#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
319#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
320#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
321#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
322#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
323#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
324#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
325#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
326
327#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
328#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
329#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
330#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
331#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
332#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
333#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
334#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
335#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
336#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
337#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
338#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
339#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
340#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
341#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
342#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
343#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
344#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
345#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
346#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
347#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
348#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
349#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
350#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
351#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
352#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
353
354#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
355#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
356#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
357#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
358#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
359#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
360#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
361#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
362#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
363#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
364#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
365#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
366#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
367#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
368#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
369#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
370#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
371#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
372#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
373#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
374#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
375#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
376#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
377#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
378#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
379#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
380
381#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
382#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
383#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
384#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
385#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
386#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
387#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
388#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
389#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
390#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
391#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
392#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
393#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
394#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
395#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
396#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
397#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
398#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
399#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
400#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
401#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
402#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
403#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
404#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
405#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
406#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
407
408#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
409#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
410#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
411#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
412#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
413#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
414#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
415#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
416#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
417#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
418#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
419#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
420#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
421#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
422#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
423#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
424#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
425#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
426#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
427#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
428#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
429#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
430#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
431#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
432#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
433#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
434
435#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
436#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
437#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
438#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
439#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
440#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
441#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
442#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
443#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
444#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
445#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
446#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
447#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
448#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
449#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
450#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
451#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
452#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
453#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
454#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
455#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
456#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
457#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
458#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
459#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
460#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
461
462#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
463#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
464#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
465#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
466#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
467#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
468#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
469#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
470#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
471#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
472#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
473#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
474#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
475#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
476#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
477#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
478#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
479#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
480#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
481#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
482#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
483#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
484#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
485#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
486#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
487#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
488
489/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
490#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
491#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
492#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
493#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
494#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
495#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
496
497/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
498#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
499#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
500#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
501#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
502#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
503#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
504#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
505#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
506
507/* UART Controller */
508#define bfin_read_UART_THR() bfin_read16(UART_THR)
509#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
510#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
511#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
512#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
513#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
514#define bfin_read_UART_IER() bfin_read16(UART_IER)
515#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
516#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
517#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
518#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
519#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
520#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
521#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
522#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
523#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
524#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
525#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
526/*
527#define UART_MSR
528*/
529#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
530#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
531#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
532#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
533
534/* SPI Controller */
535#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
536#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
537#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
538#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
539#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
540#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
541#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
542#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
543#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
544#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
545#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
546#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
547#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
548#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
549
550/* TIMER 0, 1, 2 Registers */
551#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
552#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
553#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
554#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
555#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
556#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
557#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
558#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
559
560#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
561#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
562#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
563#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
564#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
565#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
566#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
567#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
568
569#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
570#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
571#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
572#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
573#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
574#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
575#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
576#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
577
578#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
579#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
580#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
581#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
582#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
583#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
584
585/* SPORT0 Controller */
586#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
587#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
588#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
589#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
590#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
591#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
592#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
593#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
594#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
595#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
596#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
597#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
598#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
599#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
600#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
601#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
602#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
603#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
604#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
605#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
606#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
607#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
608#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
609#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
610#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
611#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
612#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
613#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
614#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
615#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
616#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
617#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
618#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
619#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
620#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
621#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
622#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
623#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
624#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
625#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
626#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
627#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
628#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
629#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
630#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
631#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
632#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
633#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
634#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
635#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
636#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
637#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
638
639/* SPORT1 Controller */
640#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
641#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
642#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
643#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
644#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
645#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
646#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
647#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
648#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
649#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
650#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
651#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
652#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
653#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
654#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
655#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
656#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
657#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
658#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
659#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
660#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
661#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
662#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
663#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
664#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
665#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
666#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
667#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
668#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
669#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
670#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
671#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
672#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
673#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
674#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
675#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
676#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
677#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
678#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
679#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
680#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
681#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
682#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
683#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
684#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
685#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
686#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
687#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
688#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
689#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
690#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
691#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
692
693/* Parallel Peripheral Interface (PPI) */
694#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
695#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
696#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
697#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
698#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
699#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
700#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
701#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
702#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
703#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
704#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
705
706#endif /* _CDEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
new file mode 100644
index 000000000000..b240a082aa09
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -0,0 +1,1175 @@
1/************************************************************************
2 *
3 * This file is subject to the terms and conditions of the GNU Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Non-GPL License also available as part of VisualDSP++
8 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
9 *
10 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
11 *
12 * This file under source code control, please send bugs or changes to:
13 * dsptools.support@analog.com
14 *
15 ************************************************************************/
16/*
17 * File: include/asm-blackfin/mach-bf533/defBF532.h
18 * Based on:
19 * Author:
20 *
21 * Created:
22 * Description:
23 *
24 * Rev:
25 *
26 * Modified:
27 *
28 * Bugs: Enter bugs at http://blackfin.uclinux.org/
29 *
30 * This program is free software; you can redistribute it and/or modify
31 * it under the terms of the GNU General Public License as published by
32 * the Free Software Foundation; either version 2, or (at your option)
33 * any later version.
34 *
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
39 *
40 * You should have received a copy of the GNU General Public License
41 * along with this program; see the file COPYING.
42 * If not, write to the Free Software Foundation,
43 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
44 */
45/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
46
47#ifndef _DEF_BF532_H
48#define _DEF_BF532_H
49/*
50#if !defined(__ADSPLPBLACKFIN__)
51#warning defBF532.h should only be included for 532 compatible chips
52#endif
53*/
54/* include all Core registers and bit definitions */
55#include <asm/mach-common/def_LPBlackfin.h>
56
57/*********************************************************************************** */
58/* System MMR Register Map */
59/*********************************************************************************** */
60/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
61
62#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
63#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
64#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
65#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
66#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
67#define CHIPID 0xFFC00014 /* Chip ID Register */
68#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
69#define SYSCR 0xFFC00104 /* System Configuration registe */
70
71/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
72#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
73#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
74#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
75#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
76#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
77#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
78#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
79
80/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
81#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
82#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
83#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
84
85/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
86#define RTC_STAT 0xFFC00300 /* RTC Status Register */
87#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
88#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
89#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
90#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
91#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
92#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
93
94/* UART Controller (0xFFC00400 - 0xFFC004FF) */
95#define UART_THR 0xFFC00400 /* Transmit Holding register */
96#define UART_RBR 0xFFC00400 /* Receive Buffer register */
97#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
98#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
99#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
100#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
101#define UART_LCR 0xFFC0040C /* Line Control Register */
102#define UART_MCR 0xFFC00410 /* Modem Control Register */
103#define UART_LSR 0xFFC00414 /* Line Status Register */
104#if 0
105#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
106#endif
107#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
108#define UART_GCTL 0xFFC00424 /* Global Control Register */
109
110/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
111#define SPI_CTL 0xFFC00500 /* SPI Control Register */
112#define SPI_FLG 0xFFC00504 /* SPI Flag register */
113#define SPI_STAT 0xFFC00508 /* SPI Status register */
114#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
115#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
116#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
117#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
118
119/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
120
121#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
122#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
123#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
124#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
125
126#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
127#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
128#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
129#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
130
131#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
132#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
133#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
134#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
135
136#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
137#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
138#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
139
140/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
141
142#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
143#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
144#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
145#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
146#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
147#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
148#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
149#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
150#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
151#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
152#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
153#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
154#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
155#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
156#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
157#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
158#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
159
160/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
161#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
162#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
163#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
164#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
165#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
166#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
167#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
168#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
169#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
170#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
171#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
172#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
173#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
174#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
175#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
176#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
177#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
178#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
179#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
180#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
181#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
182#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
183
184/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
185#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
186#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
187#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
188#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
189#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
190#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
191#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
192#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
193#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
194#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
195#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
196#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
197#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
198#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
199#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
200#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
201#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
202#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
203#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
204#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
205#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
206#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
207
208/* Asynchronous Memory Controller - External Bus Interface Unit */
209#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
210#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
211#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
212
213/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
214
215#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
216#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
217#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
218#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
219
220/* DMA Traffic controls */
221#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
222#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
223#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
224#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
225
226/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
227#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
228#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
229#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
230#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
231#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
232#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
233#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
234#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
235#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
236#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
237#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
238#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
239#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
240
241#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
242#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
243#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
244#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
245#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
246#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
247#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
248#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
249#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
250#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
251#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
252#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
253#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
254
255#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
256#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
257#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
258#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
259#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
260#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
261#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
262#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
263#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
264#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
265#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
266#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
267#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
268
269#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
270#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
271#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
272#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
273#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
274#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
275#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
276#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
277#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
278#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
279#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
280#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
281#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
282
283#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
284#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
285#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
286#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
287#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
288#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
289#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
290#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
291#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
292#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
293#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
294#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
295#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
296
297#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
298#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
299#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
300#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
301#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
302#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
303#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
304#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
305#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
306#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
307#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
308#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
309#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
310
311#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
312#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
313#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
314#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
315#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
316#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
317#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
318#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
319#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
320#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
321#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
322#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
323#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
324
325#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
326#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
327#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
328#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
329#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
330#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
331#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
332#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
333#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
334#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
335#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
336#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
337#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
338
339#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
340#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
341#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
342#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
343#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
344#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
345#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
346#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
347#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
348#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
349#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
350#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
351#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
352
353#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
354#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
355#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
356#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
357#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
358#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
359#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
360#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
361#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
362#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
363#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
364#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
365#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
366
367#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
368#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
369#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
370#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
371#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
372#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
373#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
374#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
375#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
376#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
377#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
378#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
379#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
380
381#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
382#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
383#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
384#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
385#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
386#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
387#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
388#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
389#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
390#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
391#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
392#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
393#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
394
395/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
396
397#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
398#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
399#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
400#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
401#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
402
403/*********************************************************************************** */
404/* System MMR Register Bits */
405/******************************************************************************* */
406
407/* ********************* PLL AND RESET MASKS ************************ */
408
409/* PLL_CTL Masks */
410#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
411#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
412#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
413#define STOPCK_OFF 0x00000008 /* Core clock off */
414#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
415#define BYPASS 0x00000100 /* Bypass the PLL */
416
417/* PLL_DIV Masks */
418
419#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
420
421#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
422#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
423#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
424#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
425
426/* PLL_STAT Masks */
427#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
428#define FULL_ON 0x0002 /* Processor In Full On Mode */
429#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
430#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
431
432/* CHIPID Masks */
433#define CHIPID_VERSION 0xF0000000
434#define CHIPID_FAMILY 0x0FFFF000
435#define CHIPID_MANUFACTURE 0x00000FFE
436
437/* SWRST Mask */
438#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
439
440/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
441
442 /* SIC_IAR0 Masks */
443
444#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
445#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
446#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
447#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
448#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
449#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
450#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
451#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
452
453/* SIC_IAR1 Masks */
454
455#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
456#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
457#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
458#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
459#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
460#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
461#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
462#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
463
464/* SIC_IAR2 Masks */
465#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
466#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
467#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
468#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
469#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
470#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
471#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
472#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
473
474/* SIC_IMASK Masks */
475#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
476#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
477#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
478#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
479
480/* SIC_IWR Masks */
481#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
482#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
483#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
484#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
485
486/* ********* WATCHDOG TIMER MASKS ********************8 */
487
488/* Watchdog Timer WDOG_CTL Register */
489#define ICTL(x) ((x<<1) & 0x0006)
490#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
491#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
492#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
493#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
494
495#define TMR_EN 0x0000
496#define TMR_DIS 0x0AD0
497#define TRO 0x8000
498
499#define ICTL_P0 0x01
500#define ICTL_P1 0x02
501#define TRO_P 0x0F
502
503/* ***************************** UART CONTROLLER MASKS ********************** */
504
505/* UART_LCR Register */
506
507#define DLAB 0x80
508#define SB 0x40
509#define STP 0x20
510#define EPS 0x10
511#define PEN 0x08
512#define STB 0x04
513#define WLS(x) ((x-5) & 0x03)
514
515#define DLAB_P 0x07
516#define SB_P 0x06
517#define STP_P 0x05
518#define EPS_P 0x04
519#define PEN_P 0x03
520#define STB_P 0x02
521#define WLS_P1 0x01
522#define WLS_P0 0x00
523
524/* UART_MCR Register */
525#define LOOP_ENA 0x10
526#define LOOP_ENA_P 0x04
527
528/* UART_LSR Register */
529#define TEMT 0x40
530#define THRE 0x20
531#define BI 0x10
532#define FE 0x08
533#define PE 0x04
534#define OE 0x02
535#define DR 0x01
536
537#define TEMP_P 0x06
538#define THRE_P 0x05
539#define BI_P 0x04
540#define FE_P 0x03
541#define PE_P 0x02
542#define OE_P 0x01
543#define DR_P 0x00
544
545/* UART_IER Register */
546#define ELSI 0x04
547#define ETBEI 0x02
548#define ERBFI 0x01
549
550#define ELSI_P 0x02
551#define ETBEI_P 0x01
552#define ERBFI_P 0x00
553
554/* UART_IIR Register */
555#define STATUS(x) ((x << 1) & 0x06)
556#define NINT 0x01
557#define STATUS_P1 0x02
558#define STATUS_P0 0x01
559#define NINT_P 0x00
560#define IIR_TX_READY 0x02 /* UART_THR empty */
561#define IIR_RX_READY 0x04 /* Receive data ready */
562#define IIR_LINE_CHANGE 0x06 /* Receive line status */
563#define IIR_STATUS 0x06
564
565/* UART_GCTL Register */
566#define FFE 0x20
567#define FPE 0x10
568#define RPOLC 0x08
569#define TPOLC 0x04
570#define IREN 0x02
571#define UCEN 0x01
572
573#define FFE_P 0x05
574#define FPE_P 0x04
575#define RPOLC_P 0x03
576#define TPOLC_P 0x02
577#define IREN_P 0x01
578#define UCEN_P 0x00
579
580/* ********** SERIAL PORT MASKS ********************** */
581
582/* SPORTx_TCR1 Masks */
583#define TSPEN 0x0001 /* TX enable */
584#define ITCLK 0x0002 /* Internal TX Clock Select */
585#define TDTYPE 0x000C /* TX Data Formatting Select */
586#define TLSBIT 0x0010 /* TX Bit Order */
587#define ITFS 0x0200 /* Internal TX Frame Sync Select */
588#define TFSR 0x0400 /* TX Frame Sync Required Select */
589#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
590#define LTFS 0x1000 /* Low TX Frame Sync Select */
591#define LATFS 0x2000 /* Late TX Frame Sync Select */
592#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
593
594/* SPORTx_TCR2 Masks */
595#define SLEN 0x001F /*TX Word Length */
596#define TXSE 0x0100 /*TX Secondary Enable */
597#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
598#define TRFST 0x0400 /*TX Right-First Data Order */
599
600/* SPORTx_RCR1 Masks */
601#define RSPEN 0x0001 /* RX enable */
602#define IRCLK 0x0002 /* Internal RX Clock Select */
603#define RDTYPE 0x000C /* RX Data Formatting Select */
604#define RULAW 0x0008 /* u-Law enable */
605#define RALAW 0x000C /* A-Law enable */
606#define RLSBIT 0x0010 /* RX Bit Order */
607#define IRFS 0x0200 /* Internal RX Frame Sync Select */
608#define RFSR 0x0400 /* RX Frame Sync Required Select */
609#define LRFS 0x1000 /* Low RX Frame Sync Select */
610#define LARFS 0x2000 /* Late RX Frame Sync Select */
611#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
612
613/* SPORTx_RCR2 Masks */
614#define SLEN 0x001F /*RX Word Length */
615#define RXSE 0x0100 /*RX Secondary Enable */
616#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
617#define RRFST 0x0400 /*Right-First Data Order */
618
619/*SPORTx_STAT Masks */
620#define RXNE 0x0001 /*RX FIFO Not Empty Status */
621#define RUVF 0x0002 /*RX Underflow Status */
622#define ROVF 0x0004 /*RX Overflow Status */
623#define TXF 0x0008 /*TX FIFO Full Status */
624#define TUVF 0x0010 /*TX Underflow Status */
625#define TOVF 0x0020 /*TX Overflow Status */
626#define TXHRE 0x0040 /*TX Hold Register Empty */
627
628/*SPORTx_MCMC1 Masks */
629#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
630#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
631
632/*SPORTx_MCMC2 Masks */
633#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
634#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
635#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
636#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
637#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
638#define MFD 0x0000F000 /*Multichannel Frame Delay */
639
640/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
641
642/* PPI_CONTROL Masks */
643#define PORT_EN 0x00000001 /* PPI Port Enable */
644#define PORT_DIR 0x00000002 /* PPI Port Direction */
645#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
646#define PORT_CFG 0x00000030 /* PPI Port Configuration */
647#define FLD_SEL 0x00000040 /* PPI Active Field Select */
648#define PACK_EN 0x00000080 /* PPI Packing Mode */
649#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
650#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
651#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
652#define DLENGTH 0x00003800 /* PPI Data Length */
653#define DLEN_8 0x0000 /* Data Length = 8 Bits */
654#define DLEN_10 0x0800 /* Data Length = 10 Bits */
655#define DLEN_11 0x1000 /* Data Length = 11 Bits */
656#define DLEN_12 0x1800 /* Data Length = 12 Bits */
657#define DLEN_13 0x2000 /* Data Length = 13 Bits */
658#define DLEN_14 0x2800 /* Data Length = 14 Bits */
659#define DLEN_15 0x3000 /* Data Length = 15 Bits */
660#define DLEN_16 0x3800 /* Data Length = 16 Bits */
661#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
662#define POL 0x0000C000 /* PPI Signal Polarities */
663
664/* PPI_STATUS Masks */
665#define FLD 0x00000400 /* Field Indicator */
666#define FT_ERR 0x00000800 /* Frame Track Error */
667#define OVR 0x00001000 /* FIFO Overflow Error */
668#define UNDR 0x00002000 /* FIFO Underrun Error */
669#define ERR_DET 0x00004000 /* Error Detected Indicator */
670#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
671
672/* ********** DMA CONTROLLER MASKS *********************8 */
673
674/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
675#define DMAEN 0x00000001 /* Channel Enable */
676#define WNR 0x00000002 /* Channel Direction (W/R*) */
677#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
678#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
679#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
680#define DMA2D 0x00000010 /* 2D/1D* Mode */
681#define RESTART 0x00000020 /* Restart */
682#define DI_SEL 0x00000040 /* Data Interrupt Select */
683#define DI_EN 0x00000080 /* Data Interrupt Enable */
684#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
685#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
686#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
687#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
688#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
689#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
690#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
691#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
692#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
693#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
694#define NDSIZE 0x00000900 /* Next Descriptor Size */
695#define DMAFLOW 0x00007000 /* Flow Control */
696#define DMAFLOW_STOP 0x0000 /* Stop Mode */
697#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
698#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
699#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
700#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
701
702#define DMAEN_P 0 /* Channel Enable */
703#define WNR_P 1 /* Channel Direction (W/R*) */
704#define DMA2D_P 4 /* 2D/1D* Mode */
705#define RESTART_P 5 /* Restart */
706#define DI_SEL_P 6 /* Data Interrupt Select */
707#define DI_EN_P 7 /* Data Interrupt Enable */
708
709/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
710
711#define DMA_DONE 0x00000001 /* DMA Done Indicator */
712#define DMA_ERR 0x00000002 /* DMA Error Indicator */
713#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
714#define DMA_RUN 0x00000008 /* DMA Running Indicator */
715
716#define DMA_DONE_P 0 /* DMA Done Indicator */
717#define DMA_ERR_P 1 /* DMA Error Indicator */
718#define DFETCH_P 2 /* Descriptor Fetch Indicator */
719#define DMA_RUN_P 3 /* DMA Running Indicator */
720
721/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
722
723#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
724#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
725#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
726#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
727#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
728#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
729#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
730#define PMAP 0x00007000 /* DMA Peripheral Map Field */
731
732/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
733
734/* PWM Timer bit definitions */
735
736/* TIMER_ENABLE Register */
737#define TIMEN0 0x0001
738#define TIMEN1 0x0002
739#define TIMEN2 0x0004
740
741#define TIMEN0_P 0x00
742#define TIMEN1_P 0x01
743#define TIMEN2_P 0x02
744
745/* TIMER_DISABLE Register */
746#define TIMDIS0 0x0001
747#define TIMDIS1 0x0002
748#define TIMDIS2 0x0004
749
750#define TIMDIS0_P 0x00
751#define TIMDIS1_P 0x01
752#define TIMDIS2_P 0x02
753
754/* TIMER_STATUS Register */
755#define TIMIL0 0x0001
756#define TIMIL1 0x0002
757#define TIMIL2 0x0004
758#define TOVL_ERR0 0x0010
759#define TOVL_ERR1 0x0020
760#define TOVL_ERR2 0x0040
761#define TRUN0 0x1000
762#define TRUN1 0x2000
763#define TRUN2 0x4000
764
765#define TIMIL0_P 0x00
766#define TIMIL1_P 0x01
767#define TIMIL2_P 0x02
768#define TOVL_ERR0_P 0x04
769#define TOVL_ERR1_P 0x05
770#define TOVL_ERR2_P 0x06
771#define TRUN0_P 0x0C
772#define TRUN1_P 0x0D
773#define TRUN2_P 0x0E
774
775/* TIMERx_CONFIG Registers */
776#define PWM_OUT 0x0001
777#define WDTH_CAP 0x0002
778#define EXT_CLK 0x0003
779#define PULSE_HI 0x0004
780#define PERIOD_CNT 0x0008
781#define IRQ_ENA 0x0010
782#define TIN_SEL 0x0020
783#define OUT_DIS 0x0040
784#define CLK_SEL 0x0080
785#define TOGGLE_HI 0x0100
786#define EMU_RUN 0x0200
787#define ERR_TYP(x) ((x & 0x03) << 14)
788
789#define TMODE_P0 0x00
790#define TMODE_P1 0x01
791#define PULSE_HI_P 0x02
792#define PERIOD_CNT_P 0x03
793#define IRQ_ENA_P 0x04
794#define TIN_SEL_P 0x05
795#define OUT_DIS_P 0x06
796#define CLK_SEL_P 0x07
797#define TOGGLE_HI_P 0x08
798#define EMU_RUN_P 0x09
799#define ERR_TYP_P0 0x0E
800#define ERR_TYP_P1 0x0F
801
802/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
803
804/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
805#define PF0 0x0001
806#define PF1 0x0002
807#define PF2 0x0004
808#define PF3 0x0008
809#define PF4 0x0010
810#define PF5 0x0020
811#define PF6 0x0040
812#define PF7 0x0080
813#define PF8 0x0100
814#define PF9 0x0200
815#define PF10 0x0400
816#define PF11 0x0800
817#define PF12 0x1000
818#define PF13 0x2000
819#define PF14 0x4000
820#define PF15 0x8000
821
822/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
823#define PF0_P 0
824#define PF1_P 1
825#define PF2_P 2
826#define PF3_P 3
827#define PF4_P 4
828#define PF5_P 5
829#define PF6_P 6
830#define PF7_P 7
831#define PF8_P 8
832#define PF9_P 9
833#define PF10_P 10
834#define PF11_P 11
835#define PF12_P 12
836#define PF13_P 13
837#define PF14_P 14
838#define PF15_P 15
839
840/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
841
842/* SPI_CTL Masks */
843#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
844#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
845#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
846#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
847#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
848#define SPI_LEN 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
849#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
850#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
851#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
852#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
853#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
854#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
855
856/* SPI_FLG Masks */
857#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
858#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
859#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
860#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
861#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
862#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
863#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
864#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
865#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
866#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
867#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
868#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
869#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
870#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
871
872/* SPI_FLG Bit Positions */
873#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
874#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
875#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
876#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
877#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
878#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
879#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
880#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
881#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
882#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
883#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
884#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
885#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
886#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
887
888/* SPI_STAT Masks */
889#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
890#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
891#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
892#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
893#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
894#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
895#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
896
897/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
898
899/* AMGCTL Masks */
900#define AMCKEN 0x00000001 /* Enable CLKOUT */
901#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
902#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
903#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
904#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
905
906/* AMGCTL Bit Positions */
907#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
908#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
909#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
910#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
911
912/* AMBCTL0 Masks */
913#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
914#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
915#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
916#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
917#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
918#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
919#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
920#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
921#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
922#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
923#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
924#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
925#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
926#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
927#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
928#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
929#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
930#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
931#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
932#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
933#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
934#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
935#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
936#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
937#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
938#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
939#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
940#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
941#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
942#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
943#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
944#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
945#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
946#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
947#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
948#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
949#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
950#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
951#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
952#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
953#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
954#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
955#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
956#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
957#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
958#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
959#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
960#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
961#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
962#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
963#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
964#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
965#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
966#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
967#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
968#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
969#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
970#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
971#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
972#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
973#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
974#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
975#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
976#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
977#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
978#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
979#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
980#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
981#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
982#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
983#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
984#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
985#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
986#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
987#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
988#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
989#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
990#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
991#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
992#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
993#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
994#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
995#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
996#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
997#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
998#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
999#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1000#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1001
1002/* AMBCTL1 Masks */
1003#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1004#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1005#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1006#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1007#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1008#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1009#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1010#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1011#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1012#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1013#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1014#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1015#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1016#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1017#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1018#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1019#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1020#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1021#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1022#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1023#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1024#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1025#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1026#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1027#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1028#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1029#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1030#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1031#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1032#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1033#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1034#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1035#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1036#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1037#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1038#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1039#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1040#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1041#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1042#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1043#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1044#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1045#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1046#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1047#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1048#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1049#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1050#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1051#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1052#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1053#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1054#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1055#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1056#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1057#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1058#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1059#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1060#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1061#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1062#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1063#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1064#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1065#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1066#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1067#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1068#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1069#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1070#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1071#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1072#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1073#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1074#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1075#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1076#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1077#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1078#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1079#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1080#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1081#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1082#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1083#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1084#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1085#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1086#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1087#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1088#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1089#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1090#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1091
1092/* ********************** SDRAM CONTROLLER MASKS *************************** */
1093
1094/* SDGCTL Masks */
1095#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1096#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1097#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1098#define PFE 0x00000010 /* Enable SDRAM prefetch */
1099#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1100#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1101#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1102#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1103#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1104#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1105#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1106#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1107#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1108#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1109#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1110#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1111#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1112#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1113#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1114#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1115#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1116#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1117#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1118#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1119#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1120#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1121#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1122#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1123#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1124#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1125#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1126#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1127#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1128#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1129#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1130#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1131#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1132#define PUPSD 0x00200000 /*Power-up start delay */
1133#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1134#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1135#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1136#define EBUFE 0x02000000 /* Enable external buffering timing */
1137#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1138#define EMREN 0x10000000 /* Extended mode register enable */
1139#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1140#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1141
1142/* EBIU_SDBCTL Masks */
1143#define EBE 0x00000001 /* Enable SDRAM external bank */
1144#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1145#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1146#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1147#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1148#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1149#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1150#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1151#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1152
1153/* EBIU_SDSTAT Masks */
1154#define SDCI 0x00000001 /* SDRAM controller is idle */
1155#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1156#define SDPUA 0x00000004 /* SDRAM power up active */
1157#define SDRS 0x00000008 /* SDRAM is in reset state */
1158#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1159#define BGSTAT 0x00000020 /* Bus granted */
1160
1161/*VR_CTL Masks*/
1162#define WAKE 0x100
1163#define VLEV_6 0x60
1164#define VLEV_7 0x70
1165#define VLEV_8 0x80
1166#define VLEV_9 0x90
1167#define VLEV_10 0xA0
1168#define VLEV_11 0xB0
1169#define VLEV_12 0xC0
1170#define VLEV_13 0xD0
1171#define VLEV_14 0xE0
1172#define VLEV_15 0xF0
1173#define FREQ_3 0x03
1174
1175#endif /* _DEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
new file mode 100644
index 000000000000..bd9d5e94307d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/dma.h
@@ -0,0 +1,54 @@
1/*****************************************************************************
2*
3* BF-533/2/1 Specific Declarations
4*
5****************************************************************************/
6/*
7 * File: include/asm-blackfin/mach-bf533/dma.h
8 * Based on:
9 * Author:
10 *
11 * Created:
12 * Description:
13 *
14 * Rev:
15 *
16 * Modified:
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING.
32 * If not, write to the Free Software Foundation,
33 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 */
35
36#ifndef _MACH_DMA_H_
37#define _MACH_DMA_H_
38
39#define MAX_BLACKFIN_DMA_CHANNEL 12
40
41#define CH_PPI 0
42#define CH_SPORT0_RX 1
43#define CH_SPORT0_TX 2
44#define CH_SPORT1_RX 3
45#define CH_SPORT1_TX 4
46#define CH_SPI 5
47#define CH_UART_RX 6
48#define CH_UART_TX 7
49#define CH_MEM_STREAM0_DEST 8 /* TX */
50#define CH_MEM_STREAM0_SRC 9 /* RX */
51#define CH_MEM_STREAM1_DEST 10 /* TX */
52#define CH_MEM_STREAM1_SRC 11 /* RX */
53
54#endif
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
new file mode 100644
index 000000000000..9879e68e315c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -0,0 +1,177 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/defBF532.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _BF533_IRQ_H_
32#define _BF533_IRQ_H_
33
34/*
35 * Interrupt source definitions
36 Event Source Core Event Name
37Core Emulation **
38 Events (highest priority) EMU 0
39 Reset RST 1
40 NMI NMI 2
41 Exception EVX 3
42 Reserved -- 4
43 Hardware Error IVHW 5
44 Core Timer IVTMR 6 *
45 PLL Wakeup Interrupt IVG7 7
46 DMA Error (generic) IVG7 8
47 PPI Error Interrupt IVG7 9
48 SPORT0 Error Interrupt IVG7 10
49 SPORT1 Error Interrupt IVG7 11
50 SPI Error Interrupt IVG7 12
51 UART Error Interrupt IVG7 13
52 RTC Interrupt IVG8 14
53 DMA0 Interrupt (PPI) IVG8 15
54 DMA1 (SPORT0 RX) IVG9 16
55 DMA2 (SPORT0 TX) IVG9 17
56 DMA3 (SPORT1 RX) IVG9 18
57 DMA4 (SPORT1 TX) IVG9 19
58 DMA5 (PPI) IVG10 20
59 DMA6 (UART RX) IVG10 21
60 DMA7 (UART TX) IVG10 22
61 Timer0 IVG11 23
62 Timer1 IVG11 24
63 Timer2 IVG11 25
64 PF Interrupt A IVG12 26
65 PF Interrupt B IVG12 27
66 DMA8/9 Interrupt IVG13 28
67 DMA10/11 Interrupt IVG13 29
68 Watchdog Timer IVG13 30
69 Software Interrupt 1 IVG14 31
70 Software Interrupt 2 --
71 (lowest priority) IVG15 32 *
72 */
73#define SYS_IRQS 32
74#define NR_PERI_INTS 24
75
76/* The ABSTRACT IRQ definitions */
77/** the first seven of the following are fixed, the rest you change if you need to **/
78#define IRQ_EMU 0 /*Emulation */
79#define IRQ_RST 1 /*reset */
80#define IRQ_NMI 2 /*Non Maskable */
81#define IRQ_EVX 3 /*Exception */
82#define IRQ_UNUSED 4 /*- unused interrupt*/
83#define IRQ_HWERR 5 /*Hardware Error */
84#define IRQ_CORETMR 6 /*Core timer */
85
86#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
87#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
88#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
89#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
90#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
91#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
92#define IRQ_UART_ERROR 13 /*UART Error Interrupt */
93#define IRQ_RTC 14 /*RTC Interrupt */
94#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
95#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
96#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
97#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
98#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
99#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
100#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
101#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
102#define IRQ_TMR0 23 /*Timer 0 */
103#define IRQ_TMR1 24 /*Timer 1 */
104#define IRQ_TMR2 25 /*Timer 2 */
105#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
106#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
107#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
108#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
109#define IRQ_WATCH 30 /*Watch Dog Timer */
110
111#define IRQ_SW_INT1 31 /*Software Int 1 */
112#define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */
113
114#define IRQ_PF0 33
115#define IRQ_PF1 34
116#define IRQ_PF2 35
117#define IRQ_PF3 36
118#define IRQ_PF4 37
119#define IRQ_PF5 38
120#define IRQ_PF6 39
121#define IRQ_PF7 40
122#define IRQ_PF8 41
123#define IRQ_PF9 42
124#define IRQ_PF10 43
125#define IRQ_PF11 44
126#define IRQ_PF12 45
127#define IRQ_PF13 46
128#define IRQ_PF14 47
129#define IRQ_PF15 48
130
131#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
132#define NR_IRQS (IRQ_PF15+1)
133#else
134#define NR_IRQS SYS_IRQS
135#endif
136
137#define IVG7 7
138#define IVG8 8
139#define IVG9 9
140#define IVG10 10
141#define IVG11 11
142#define IVG12 12
143#define IVG13 13
144#define IVG14 14
145#define IVG15 15
146
147/* IAR0 BIT FIELDS*/
148#define RTC_ERROR_POS 28
149#define UART_ERROR_POS 24
150#define SPORT1_ERROR_POS 20
151#define SPI_ERROR_POS 16
152#define SPORT0_ERROR_POS 12
153#define PPI_ERROR_POS 8
154#define DMA_ERROR_POS 4
155#define PLLWAKE_ERROR_POS 0
156
157/* IAR1 BIT FIELDS*/
158#define DMA7_UARTTX_POS 28
159#define DMA6_UARTRX_POS 24
160#define DMA5_SPI_POS 20
161#define DMA4_SPORT1TX_POS 16
162#define DMA3_SPORT1RX_POS 12
163#define DMA2_SPORT0TX_POS 8
164#define DMA1_SPORT0RX_POS 4
165#define DMA0_PPI_POS 0
166
167/* IAR2 BIT FIELDS*/
168#define WDTIMER_POS 28
169#define MEMDMA1_POS 24
170#define MEMDMA0_POS 20
171#define PFB_POS 16
172#define PFA_POS 12
173#define TIMER2_POS 8
174#define TIMER1_POS 4
175#define TIMER0_POS 0
176
177#endif /* _BF533_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
new file mode 100644
index 000000000000..1620dae5254d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/mem_init.h
@@ -0,0 +1,316 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 8955223) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_GENERIC_BOARD)
122 /*SDRAM INFORMATION: Modify this for your board */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_SIZE == 128)
129#define SDRAM_SIZE EBSZ_128
130#endif
131#if (CONFIG_MEM_SIZE == 64)
132#define SDRAM_SIZE EBSZ_64
133#endif
134#if (CONFIG_MEM_SIZE == 32)
135#define SDRAM_SIZE EBSZ_32
136#endif
137#if (CONFIG_MEM_SIZE == 16)
138#define SDRAM_SIZE EBSZ_16
139#endif
140#if (CONFIG_MEM_ADD_WIDTH == 11)
141#define SDRAM_WIDTH EBCAW_11
142#endif
143#if (CONFIG_MEM_ADD_WIDTH == 10)
144#define SDRAM_WIDTH EBCAW_10
145#endif
146#if (CONFIG_MEM_ADD_WIDTH == 9)
147#define SDRAM_WIDTH EBCAW_9
148#endif
149#if (CONFIG_MEM_ADD_WIDTH == 8)
150#define SDRAM_WIDTH EBCAW_8
151#endif
152
153#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
154
155/* Equation from section 17 (p17-46) of BF533 HRM */
156#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
157
158/* Enable SCLK Out */
159#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
160
161#if defined CONFIG_CLKIN_HALF
162#define CLKIN_HALF 1
163#else
164#define CLKIN_HALF 0
165#endif
166
167#if defined CONFIG_PLL_BYPASS
168#define PLL_BYPASS 1
169#else
170#define PLL_BYPASS 0
171#endif
172
173/***************************************Currently Not Being Used *********************************/
174#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
175#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
176#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
177#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
178#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
179
180#if (flash_EBIU_AMBCTL_TT > 3)
181#define flash_EBIU_AMBCTL0_TT B0TT_4
182#endif
183#if (flash_EBIU_AMBCTL_TT == 3)
184#define flash_EBIU_AMBCTL0_TT B0TT_3
185#endif
186#if (flash_EBIU_AMBCTL_TT == 2)
187#define flash_EBIU_AMBCTL0_TT B0TT_2
188#endif
189#if (flash_EBIU_AMBCTL_TT < 2)
190#define flash_EBIU_AMBCTL0_TT B0TT_1
191#endif
192
193#if (flash_EBIU_AMBCTL_ST > 3)
194#define flash_EBIU_AMBCTL0_ST B0ST_4
195#endif
196#if (flash_EBIU_AMBCTL_ST == 3)
197#define flash_EBIU_AMBCTL0_ST B0ST_3
198#endif
199#if (flash_EBIU_AMBCTL_ST == 2)
200#define flash_EBIU_AMBCTL0_ST B0ST_2
201#endif
202#if (flash_EBIU_AMBCTL_ST < 2)
203#define flash_EBIU_AMBCTL0_ST B0ST_1
204#endif
205
206#if (flash_EBIU_AMBCTL_HT > 2)
207#define flash_EBIU_AMBCTL0_HT B0HT_3
208#endif
209#if (flash_EBIU_AMBCTL_HT == 2)
210#define flash_EBIU_AMBCTL0_HT B0HT_2
211#endif
212#if (flash_EBIU_AMBCTL_HT == 1)
213#define flash_EBIU_AMBCTL0_HT B0HT_1
214#endif
215#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
216#define flash_EBIU_AMBCTL0_HT B0HT_0
217#endif
218#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
219#define flash_EBIU_AMBCTL0_HT B0HT_1
220#endif
221
222#if (flash_EBIU_AMBCTL_WAT > 14)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_15
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 14)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_14
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 13)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_13
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 12)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_12
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 11)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_11
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 10)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_10
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 9)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_9
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 8)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_8
245#endif
246#if (flash_EBIU_AMBCTL_WAT == 7)
247#define flash_EBIU_AMBCTL0_WAT B0WAT_7
248#endif
249#if (flash_EBIU_AMBCTL_WAT == 6)
250#define flash_EBIU_AMBCTL0_WAT B0WAT_6
251#endif
252#if (flash_EBIU_AMBCTL_WAT == 5)
253#define flash_EBIU_AMBCTL0_WAT B0WAT_5
254#endif
255#if (flash_EBIU_AMBCTL_WAT == 4)
256#define flash_EBIU_AMBCTL0_WAT B0WAT_4
257#endif
258#if (flash_EBIU_AMBCTL_WAT == 3)
259#define flash_EBIU_AMBCTL0_WAT B0WAT_3
260#endif
261#if (flash_EBIU_AMBCTL_WAT == 2)
262#define flash_EBIU_AMBCTL0_WAT B0WAT_2
263#endif
264#if (flash_EBIU_AMBCTL_WAT == 1)
265#define flash_EBIU_AMBCTL0_WAT B0WAT_1
266#endif
267
268#if (flash_EBIU_AMBCTL_RAT > 14)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_15
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 14)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_14
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 13)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_13
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 12)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_12
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 11)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_11
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 10)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_10
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 9)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_9
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 8)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_8
291#endif
292#if (flash_EBIU_AMBCTL_RAT == 7)
293#define flash_EBIU_AMBCTL0_RAT B0RAT_7
294#endif
295#if (flash_EBIU_AMBCTL_RAT == 6)
296#define flash_EBIU_AMBCTL0_RAT B0RAT_6
297#endif
298#if (flash_EBIU_AMBCTL_RAT == 5)
299#define flash_EBIU_AMBCTL0_RAT B0RAT_5
300#endif
301#if (flash_EBIU_AMBCTL_RAT == 4)
302#define flash_EBIU_AMBCTL0_RAT B0RAT_4
303#endif
304#if (flash_EBIU_AMBCTL_RAT == 3)
305#define flash_EBIU_AMBCTL0_RAT B0RAT_3
306#endif
307#if (flash_EBIU_AMBCTL_RAT == 2)
308#define flash_EBIU_AMBCTL0_RAT B0RAT_2
309#endif
310#if (flash_EBIU_AMBCTL_RAT == 1)
311#define flash_EBIU_AMBCTL0_RAT B0RAT_1
312#endif
313
314#define flash_EBIU_AMBCTL0 \
315 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
316 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
new file mode 100644
index 000000000000..e84baa3e939d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -0,0 +1,168 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf533/mem_map.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MEM_MAP_533_H_
33#define _MEM_MAP_533_H_
34
35#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
36#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
37
38/* Async Memory Banks */
39#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
40#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
41#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
42#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
43#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
44#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
45#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
46#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
47
48/* Boot ROM Memory */
49
50#define BOOT_ROM_START 0xEF000000
51
52/* Level 1 Memory */
53
54#ifdef CONFIG_BLKFIN_CACHE
55#define BLKFIN_ICACHESIZE (16*1024)
56#else
57#define BLKFIN_ICACHESIZE (0*1024)
58#endif
59
60/* Memory Map for ADSP-BF533 processors */
61
62#ifdef CONFIG_BF533
63#define L1_CODE_START 0xFFA00000
64#define L1_DATA_A_START 0xFF800000
65#define L1_DATA_B_START 0xFF900000
66
67#ifdef CONFIG_BLKFIN_CACHE
68#define L1_CODE_LENGTH (0x14000 - 0x4000)
69#else
70#define L1_CODE_LENGTH 0x14000
71#endif
72
73#ifdef CONFIG_BLKFIN_DCACHE
74
75#ifdef CONFIG_BLKFIN_DCACHE_BANKA
76#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
77#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
78#define L1_DATA_B_LENGTH 0x8000
79#define BLKFIN_DCACHESIZE (16*1024)
80#define BLKFIN_DSUPBANKS 1
81#else
82#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
83#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
84#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
85#define BLKFIN_DCACHESIZE (32*1024)
86#define BLKFIN_DSUPBANKS 2
87#endif
88
89#else
90#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
91#define L1_DATA_A_LENGTH 0x8000
92#define L1_DATA_B_LENGTH 0x8000
93#define BLKFIN_DCACHESIZE (0*1024)
94#define BLKFIN_DSUPBANKS 0
95#endif /*CONFIG_BLKFIN_DCACHE*/
96#endif
97
98/* Memory Map for ADSP-BF532 processors */
99
100#ifdef CONFIG_BF532
101#define L1_CODE_START 0xFFA08000
102#define L1_DATA_A_START 0xFF804000
103#define L1_DATA_B_START 0xFF904000
104
105#ifdef CONFIG_BLKFIN_CACHE
106#define L1_CODE_LENGTH (0xC000 - 0x4000)
107#else
108#define L1_CODE_LENGTH 0xC000
109#endif
110
111#ifdef CONFIG_BLKFIN_DCACHE
112
113#ifdef CONFIG_BLKFIN_DCACHE_BANKA
114#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
115#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
116#define L1_DATA_B_LENGTH 0x4000
117#define BLKFIN_DCACHESIZE (16*1024)
118#define BLKFIN_DSUPBANKS 1
119
120#else
121#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
122#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
123#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
124#define BLKFIN_DCACHESIZE (32*1024)
125#define BLKFIN_DSUPBANKS 2
126#endif
127
128#else
129#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
130#define L1_DATA_A_LENGTH 0x4000
131#define L1_DATA_B_LENGTH 0x4000
132#define BLKFIN_DCACHESIZE (0*1024)
133#define BLKFIN_DSUPBANKS 0
134#endif /*CONFIG_BLKFIN_DCACHE*/
135#endif
136
137/* Memory Map for ADSP-BF531 processors */
138
139#ifdef CONFIG_BF531
140#define L1_CODE_START 0xFFA08000
141#define L1_DATA_A_START 0xFF804000
142#define L1_DATA_B_START 0xFF904000
143#define L1_CODE_LENGTH 0x4000
144#define L1_DATA_B_LENGTH 0x0000
145
146
147#ifdef CONFIG_BLKFIN_DCACHE
148#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
149#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
150#define BLKFIN_DCACHESIZE (16*1024)
151#define BLKFIN_DSUPBANKS 1
152#else
153#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
154#define L1_DATA_A_LENGTH 0x4000
155#define BLKFIN_DCACHESIZE (0*1024)
156#define BLKFIN_DSUPBANKS 0
157#endif
158
159#endif
160
161/* Scratch Pad Memory */
162
163#if defined(CONFIG_BF533) || defined(CONFIG_BF532) || defined(CONFIG_BF531)
164#define L1_SCRATCH_START 0xFFB00000
165#define L1_SCRATCH_LENGTH 0x1000
166#endif
167
168#endif /* _MEM_MAP_533_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 12:35:56 -0500