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authorBryan Wu <bryan.wu@analog.com>2007-05-06 17:50:22 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-07 15:12:58 -0400
commit1394f03221790a988afc3e4b3cb79f2e477246a9 (patch)
tree2c1963c9a4f2d84a5e021307fde240c5d567cf70 /include/asm-blackfin/mach-bf533/mem_init.h
parent73243284463a761e04d69d22c7516b2be7de096c (diff)
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf533/mem_init.h')
-rw-r--r--include/asm-blackfin/mach-bf533/mem_init.h316
1 files changed, 316 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
new file mode 100644
index 000000000000..1620dae5254d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/mem_init.h
@@ -0,0 +1,316 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 8955223) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_GENERIC_BOARD)
122 /*SDRAM INFORMATION: Modify this for your board */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_SIZE == 128)
129#define SDRAM_SIZE EBSZ_128
130#endif
131#if (CONFIG_MEM_SIZE == 64)
132#define SDRAM_SIZE EBSZ_64
133#endif
134#if (CONFIG_MEM_SIZE == 32)
135#define SDRAM_SIZE EBSZ_32
136#endif
137#if (CONFIG_MEM_SIZE == 16)
138#define SDRAM_SIZE EBSZ_16
139#endif
140#if (CONFIG_MEM_ADD_WIDTH == 11)
141#define SDRAM_WIDTH EBCAW_11
142#endif
143#if (CONFIG_MEM_ADD_WIDTH == 10)
144#define SDRAM_WIDTH EBCAW_10
145#endif
146#if (CONFIG_MEM_ADD_WIDTH == 9)
147#define SDRAM_WIDTH EBCAW_9
148#endif
149#if (CONFIG_MEM_ADD_WIDTH == 8)
150#define SDRAM_WIDTH EBCAW_8
151#endif
152
153#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
154
155/* Equation from section 17 (p17-46) of BF533 HRM */
156#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
157
158/* Enable SCLK Out */
159#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
160
161#if defined CONFIG_CLKIN_HALF
162#define CLKIN_HALF 1
163#else
164#define CLKIN_HALF 0
165#endif
166
167#if defined CONFIG_PLL_BYPASS
168#define PLL_BYPASS 1
169#else
170#define PLL_BYPASS 0
171#endif
172
173/***************************************Currently Not Being Used *********************************/
174#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
175#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
176#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
177#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
178#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
179
180#if (flash_EBIU_AMBCTL_TT > 3)
181#define flash_EBIU_AMBCTL0_TT B0TT_4
182#endif
183#if (flash_EBIU_AMBCTL_TT == 3)
184#define flash_EBIU_AMBCTL0_TT B0TT_3
185#endif
186#if (flash_EBIU_AMBCTL_TT == 2)
187#define flash_EBIU_AMBCTL0_TT B0TT_2
188#endif
189#if (flash_EBIU_AMBCTL_TT < 2)
190#define flash_EBIU_AMBCTL0_TT B0TT_1
191#endif
192
193#if (flash_EBIU_AMBCTL_ST > 3)
194#define flash_EBIU_AMBCTL0_ST B0ST_4
195#endif
196#if (flash_EBIU_AMBCTL_ST == 3)
197#define flash_EBIU_AMBCTL0_ST B0ST_3
198#endif
199#if (flash_EBIU_AMBCTL_ST == 2)
200#define flash_EBIU_AMBCTL0_ST B0ST_2
201#endif
202#if (flash_EBIU_AMBCTL_ST < 2)
203#define flash_EBIU_AMBCTL0_ST B0ST_1
204#endif
205
206#if (flash_EBIU_AMBCTL_HT > 2)
207#define flash_EBIU_AMBCTL0_HT B0HT_3
208#endif
209#if (flash_EBIU_AMBCTL_HT == 2)
210#define flash_EBIU_AMBCTL0_HT B0HT_2
211#endif
212#if (flash_EBIU_AMBCTL_HT == 1)
213#define flash_EBIU_AMBCTL0_HT B0HT_1
214#endif
215#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
216#define flash_EBIU_AMBCTL0_HT B0HT_0
217#endif
218#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
219#define flash_EBIU_AMBCTL0_HT B0HT_1
220#endif
221
222#if (flash_EBIU_AMBCTL_WAT > 14)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_15
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 14)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_14
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 13)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_13
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 12)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_12
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 11)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_11
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 10)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_10
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 9)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_9
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 8)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_8
245#endif
246#if (flash_EBIU_AMBCTL_WAT == 7)
247#define flash_EBIU_AMBCTL0_WAT B0WAT_7
248#endif
249#if (flash_EBIU_AMBCTL_WAT == 6)
250#define flash_EBIU_AMBCTL0_WAT B0WAT_6
251#endif
252#if (flash_EBIU_AMBCTL_WAT == 5)
253#define flash_EBIU_AMBCTL0_WAT B0WAT_5
254#endif
255#if (flash_EBIU_AMBCTL_WAT == 4)
256#define flash_EBIU_AMBCTL0_WAT B0WAT_4
257#endif
258#if (flash_EBIU_AMBCTL_WAT == 3)
259#define flash_EBIU_AMBCTL0_WAT B0WAT_3
260#endif
261#if (flash_EBIU_AMBCTL_WAT == 2)
262#define flash_EBIU_AMBCTL0_WAT B0WAT_2
263#endif
264#if (flash_EBIU_AMBCTL_WAT == 1)
265#define flash_EBIU_AMBCTL0_WAT B0WAT_1
266#endif
267
268#if (flash_EBIU_AMBCTL_RAT > 14)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_15
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 14)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_14
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 13)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_13
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 12)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_12
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 11)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_11
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 10)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_10
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 9)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_9
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 8)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_8
291#endif
292#if (flash_EBIU_AMBCTL_RAT == 7)
293#define flash_EBIU_AMBCTL0_RAT B0RAT_7
294#endif
295#if (flash_EBIU_AMBCTL_RAT == 6)
296#define flash_EBIU_AMBCTL0_RAT B0RAT_6
297#endif
298#if (flash_EBIU_AMBCTL_RAT == 5)
299#define flash_EBIU_AMBCTL0_RAT B0RAT_5
300#endif
301#if (flash_EBIU_AMBCTL_RAT == 4)
302#define flash_EBIU_AMBCTL0_RAT B0RAT_4
303#endif
304#if (flash_EBIU_AMBCTL_RAT == 3)
305#define flash_EBIU_AMBCTL0_RAT B0RAT_3
306#endif
307#if (flash_EBIU_AMBCTL_RAT == 2)
308#define flash_EBIU_AMBCTL0_RAT B0RAT_2
309#endif
310#if (flash_EBIU_AMBCTL_RAT == 1)
311#define flash_EBIU_AMBCTL0_RAT B0RAT_1
312#endif
313
314#define flash_EBIU_AMBCTL0 \
315 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
316 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 02:15:08 -0500