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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2007-10-12 21:27:47 -0400
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2007-10-12 21:27:47 -0400
commitb981d8b3f5e008ff10d993be633ad00564fc22cd (patch)
treee292dc07b22308912cf6a58354a608b9e5e8e1fd /include/asm-blackfin/mach-bf533/defBF532.h
parentb11d2127c4893a7315d1e16273bc8560049fa3ca (diff)
parent2b9e0aae1d50e880c58d46788e5e3ebd89d75d62 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: drivers/macintosh/adbhid.c
Diffstat (limited to 'include/asm-blackfin/mach-bf533/defBF532.h')
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 6a3cf93f8b57..37134aaf9954 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -104,6 +104,7 @@
104#define UART_GCTL 0xFFC00424 /* Global Control Register */ 104#define UART_GCTL 0xFFC00424 /* Global Control Register */
105 105
106/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 106/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
107#define SPI0_REGBASE 0xFFC00500
107#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 108#define SPI_CTL 0xFFC00500 /* SPI Control Register */
108#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 109#define SPI_FLG 0xFFC00504 /* SPI Flag register */
109#define SPI_STAT 0xFFC00508 /* SPI Status register */ 110#define SPI_STAT 0xFFC00508 /* SPI Status register */
@@ -928,7 +929,7 @@
928#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ 929#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
929#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ 930#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
930#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ 931#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
931#define SPI_LEN 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ 932#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
932#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ 933#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
933#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ 934#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
934#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ 935#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */