aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-bf533/defBF532.h
diff options
context:
space:
mode:
authorMike Frysinger <michael.frysinger@analog.com>2007-08-05 05:06:48 -0400
committerBryan Wu <bryan.wu@analog.com>2007-08-05 05:06:48 -0400
commitdbcc78bebe9daed8998d9f7c4e30bd3b73a4a169 (patch)
tree245245141a698ed20592b29e4416a3b066854202 /include/asm-blackfin/mach-bf533/defBF532.h
parentf0b5d12f2b3226c85258519d7725e63d9daf5e90 (diff)
Blackfin arch: all our other ports call this SIZE rather than SPI_LEN
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf533/defBF532.h')
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 6a3cf93f8b57..81b4af17c6a3 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -928,7 +928,7 @@
928#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ 928#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
929#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ 929#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
930#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ 930#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
931#define SPI_LEN 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ 931#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
932#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ 932#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
933#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ 933#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
934#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ 934#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */