diff options
author | Bryan Wu <bryan.wu@analog.com> | 2007-05-21 06:09:31 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-21 12:50:23 -0400 |
commit | 19381f024b01413d83cec1655c3fc4c9c09ae274 (patch) | |
tree | 4ba1d63900e031c97130638c2d678aaf15c3d37e /include/asm-blackfin/mach-bf533/cdefBF532.h | |
parent | c09c4e006590210001ced90d59e62182bfd396f9 (diff) |
Blackfin arch: update blackfin header files to latest one in VDSP.
a) add new processor BF52x/BF54x header files
b) update blackfin BF533/BF537/BF561 header files to latest one in VDSP.
c) scrub watchdog/rtc masks from headers as we dont need/want them (too generic and the drivers dont use them)
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Roy Huang <roy.huang@analog.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf533/cdefBF532.h')
-rw-r--r-- | include/asm-blackfin/mach-bf533/cdefBF532.h | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h index 521bdb4d297d..74f967b235e2 100644 --- a/include/asm-blackfin/mach-bf533/cdefBF532.h +++ b/include/asm-blackfin/mach-bf533/cdefBF532.h | |||
@@ -51,10 +51,6 @@ | |||
51 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | 51 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
52 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) | 52 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) |
53 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | 53 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
54 | #define bfin_read_SWRST() bfin_read16(SWRST) | ||
55 | #define bfin_write_SWRST(val) bfin_write16(SWRST,val) | ||
56 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | ||
57 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) | ||
58 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | 54 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
59 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) | 55 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) |
60 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | 56 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
@@ -78,6 +74,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
78 | } | 74 | } |
79 | 75 | ||
80 | /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ | 76 | /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ |
77 | #define bfin_read_SWRST() bfin_read16(SWRST) | ||
78 | #define bfin_write_SWRST(val) bfin_write16(SWRST,val) | ||
79 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | ||
80 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) | ||
81 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) | 81 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
82 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) | 82 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) |
83 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | 83 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) |
@@ -117,6 +117,18 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
117 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) | 117 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) |
118 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) | 118 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) |
119 | 119 | ||
120 | /* DMA Traffic controls */ | ||
121 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | ||
122 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) | ||
123 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | ||
124 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) | ||
125 | |||
126 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
127 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) | ||
128 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) | ||
129 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | ||
130 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) | ||
131 | |||
120 | /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ | 132 | /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ |
121 | #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) | 133 | #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) |
122 | #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) | 134 | #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) |
@@ -153,16 +165,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
153 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) | 165 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) |
154 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) | 166 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) |
155 | 167 | ||
156 | /* DMA Traffic controls */ | ||
157 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | ||
158 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) | ||
159 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | ||
160 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) | ||
161 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) | ||
162 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) | ||
163 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | ||
164 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) | ||
165 | |||
166 | /* DMA Controller */ | 168 | /* DMA Controller */ |
167 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | 169 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
168 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) | 170 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) |