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authorLinus Torvalds <torvalds@linux-foundation.org>2008-06-02 18:25:27 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-06-02 18:25:27 -0400
commit00e98a9992641a14ace0bbc2dfcbc4e856ac3fd3 (patch)
tree69cc9c6cd24175d704de5a50db14cdb05df3e609 /include/asm-blackfin/mach-bf533/anomaly.h
parentf365ad5fc001cbd02968a376e0aecffe52ce79e1 (diff)
parenta4ed1e41a734d77c9a83a88a8736e19b68e6a2a0 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: 8250 Serial Driver: revert extra IRQ flag definition patch Blackfin arch: update anomaly headers from toolchain trunk Blackfin arch: Remove bad and usless code Blackfin arch: Fix bug - set corret SSEL and IRQ to enable AD7877 on BF527 Blackfin arch: Fix typo. it should be _outsw_8 Blackfin arch: Cleanup no functional changes
Diffstat (limited to 'include/asm-blackfin/mach-bf533/anomaly.h')
-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h31
1 files changed, 16 insertions, 15 deletions
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index 5a6dcc5fa36c..8f7ea112fd3a 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf533/anomaly.h 2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2007 Analog Devices Inc. 5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -176,6 +176,21 @@
176#define ANOMALY_05000315 (1) 176#define ANOMALY_05000315 (1)
177/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ 177/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
178#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) 178#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
179/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
180#define ANOMALY_05000357 (1)
181/* UART Break Signal Issues */
182#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
183/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
184#define ANOMALY_05000366 (1)
185/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
186#define ANOMALY_05000371 (1)
187/* PPI Does Not Start Properly In Specific Mode */
188#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
189/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
190#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
191/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
192#define ANOMALY_05000403 (1)
193
179 194
180/* These anomalies have been "phased" out of analog.com anomaly sheets and are 195/* These anomalies have been "phased" out of analog.com anomaly sheets and are
181 * here to show running on older silicon just isn't feasible. 196 * here to show running on older silicon just isn't feasible.
@@ -249,20 +264,6 @@
249#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) 264#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
250/* Internal Voltage Regulator may not start up */ 265/* Internal Voltage Regulator may not start up */
251#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) 266#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
252/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
253#define ANOMALY_05000357 (1)
254/* UART Break Signal Issues */
255#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
256/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
257#define ANOMALY_05000366 (1)
258/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
259#define ANOMALY_05000371 (1)
260/* PPI Does Not Start Properly In Specific Mode */
261#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
262/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
263#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
264/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
265#define ANOMALY_05000403 (1)
266 267
267/* Anomalies that don't exist on this proc */ 268/* Anomalies that don't exist on this proc */
268#define ANOMALY_05000266 (0) 269#define ANOMALY_05000266 (0)