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authorMike Frysinger <michael.frysinger@analog.com>2007-07-24 03:23:20 -0400
committerBryan Wu <bryan.wu@analog.com>2007-07-24 03:23:20 -0400
commit287050fe13bf34824f03b4351002b0e2db4ee5cb (patch)
treebb51beb7fef409a36120f00c63fa1e29c967a140 /include/asm-blackfin/mach-bf533/anomaly.h
parentc6c4d7bbbb498c38afa05688dfc2784948a0c4e2 (diff)
Blackfin arch: cleanup and standardize anomaly.h file format -- no functional changes
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf533/anomaly.h')
-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h136
1 files changed, 57 insertions, 79 deletions
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index 7302f290b93d..2a63ffc250a1 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -1,31 +1,9 @@
1/* 1/*
2 * File: include/asm-blackfin/mach-bf533/anomaly.h 2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Based on: 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * Author:
5 * 4 *
6 * Created: 5 * Copyright (C) 2004-2007 Analog Devices Inc.
7 * Description: 6 * Licensed under the GPL-2 or later.
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */ 7 */
30 8
31/* This file shoule be up to date with: 9/* This file shoule be up to date with:
@@ -43,44 +21,44 @@
43#endif 21#endif
44 22
45/* Issues that are common to 0.5, 0.4, and 0.3 silicon */ 23/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
46#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \ 24#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
47 || defined(CONFIG_BF_REV_0_3)) 25 || defined(CONFIG_BF_REV_0_3))
48#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 26#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
49 slot1 and store of a P register in slot 2 is not 27 * slot1 and store of a P register in slot 2 is not
50 supported */ 28 * supported */
51#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on 29#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
52 every corresponding match */ 30 * every corresponding match */
53#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive 31#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
54 Channel DMA stops */ 32 * Channel DMA stops */
55#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR 33#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
56 registers. */ 34 * registers. */
57#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out 35#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
58 upper bits*/ 36 * upper bits*/
59#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ 37#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
60#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame 38#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
61 syncs */ 39 * syncs */
62#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not 40#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
63 functional */ 41 * functional */
64#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable 42#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
65 state */ 43 * state */
66#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */ 44#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
67#define ANOMALY_05000272 /* Certain data cache write through modes fail for 45#define ANOMALY_05000272 /* Certain data cache write through modes fail for
68 VDDint <=0.9V */ 46 * VDDint <=0.9V */
69#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ 47#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
70#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after 48#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
71 an edge is detected may clear interrupt */ 49 * an edge is detected may clear interrupt */
72#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause 50#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
73 DMA system instability */ 51 * DMA system instability */
74#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is 52#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
75 not restored */ 53 * not restored */
76#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic 54#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
77 control */ 55 * control */
78#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when 56#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
79 killed in a particular stage*/ 57 * killed in a particular stage*/
80#define ANOMALY_05000311 /* Erroneous flag pin operations under specific 58#define ANOMALY_05000311 /* Erroneous flag pin operations under specific
81 sequences */ 59 * sequences */
82#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC 60#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
83 registers are interrupted */ 61 * registers are interrupted */
84#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */ 62#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */
85#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On 63#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
86 * Next System MMR Access */ 64 * Next System MMR Access */
@@ -91,90 +69,90 @@
91/* These issues only occur on 0.3 or 0.4 BF533 */ 69/* These issues only occur on 0.3 or 0.4 BF533 */
92#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) 70#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
93#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not 71#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
94 updated at the same time. */ 72 * updated at the same time. */
95#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data 73#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
96 Cache Fill can be corrupted after or during 74 * Cache Fill can be corrupted after or during
97 Instruction DMA if certain core stalls exist */ 75 * Instruction DMA if certain core stalls exist */
98#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General 76#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
99 Purpose TX or RX modes */ 77 * Purpose TX or RX modes */
100#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by 78#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
101 preceding memory read */ 79 * preceding memory read */
102#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during 80#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
103 inactive channels in certain conditions */ 81 * inactive channels in certain conditions */
104#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag 82#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
105 situation */ 83 * situation */
106#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ 84#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
107#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ 85#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
108#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect 86#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
109 data*/ 87 * data*/
110#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate 88#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
111 Differences in certain Conditions */ 89 * Differences in certain Conditions */
112#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ 90#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
113#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to 91#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
114 hardware reset */ 92 * hardware reset */
115#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or 93#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
116 IDLE around a Change of Control causes 94 * IDLE around a Change of Control causes
117 unpredictable results */ 95 * unpredictable results */
118#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the 96#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
119 shadow of a conditional branch */ 97 * shadow of a conditional branch */
120#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware 98#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
121 errors */ 99 * errors */
122#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ 100#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
123#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event 101#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
124 interrupt not functional */ 102 * interrupt not functional */
125#define ANOMALY_05000257 /* An interrupt or exception during short Hardware 103#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
126 loops may cause the instruction fetch unit to 104 * loops may cause the instruction fetch unit to
127 malfunction */ 105 * malfunction */
128#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of 106#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
129 the ICPLB Data registers differ */ 107 * the ICPLB Data registers differ */
130#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ 108#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
131#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ 109#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
132#define ANOMALY_05000262 /* Stores to data cache may be lost */ 110#define ANOMALY_05000262 /* Stores to data cache may be lost */
133#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ 111#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
134#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE 112#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
135 instruction will cause an infinite stall in the 113 * instruction will cause an infinite stall in the
136 second to last instruction in a hardware loop */ 114 * second to last instruction in a hardware loop */
137#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on 115#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
138 SPORT external receive and transmit clocks. */ 116 * SPORT external receive and transmit clocks. */
139#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the 117#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
140 internal voltage regulator (VDDint) to increase. */ 118 * internal voltage regulator (VDDint) to increase. */
141#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the 119#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
142 internal voltage regulator (VDDint) to decrease */ 120 * internal voltage regulator (VDDint) to decrease */
143#endif /* issues only occur on 0.3 or 0.4 BF533 */ 121#endif /* issues only occur on 0.3 or 0.4 BF533 */
144 122
145/* These issues are only on 0.4 silicon */ 123/* These issues are only on 0.4 silicon */
146#if (defined(CONFIG_BF_REV_0_4)) 124#if (defined(CONFIG_BF_REV_0_4))
147#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ 125#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
148#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel 126#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
149 (TDM) */ 127 * (TDM) */
150#endif /* issues are only on 0.4 silicon */ 128#endif /* issues are only on 0.4 silicon */
151 129
152/* These issues are only on 0.3 silicon */ 130/* These issues are only on 0.3 silicon */
153#if defined(CONFIG_BF_REV_0_3) 131#if defined(CONFIG_BF_REV_0_3)
154#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with 132#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
155 External Frame Syncs */ 133 * External Frame Syncs */
156#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative 134#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
157 Instruction or Data Fetches, or by Fetches at the 135 * Instruction or Data Fetches, or by Fetches at the
158 boundary of reserved memory space */ 136 * boundary of reserved memory space */
159#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs 137#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
160 when polarity setting is changed */ 138 * when polarity setting is changed */
161#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data 139#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
162 corruption */ 140 * corruption */
163#define ANOMALY_05000199 /* DMA current address shows wrong value during carry 141#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
164 fix */ 142 * fix */
165#define ANOMALY_05000201 /* Receive frame sync not ignored during active 143#define ANOMALY_05000201 /* Receive frame sync not ignored during active
166 frames in sport MCM */ 144 * frames in sport MCM */
167#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA 145#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
168 stopping */ 146 * stopping */
169#if defined(CONFIG_BF533) 147#if defined(CONFIG_BF533)
170#define ANOMALY_05000204 /* Incorrect data read with write-through cache and 148#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
171 allocate cache lines on reads only mode */ 149 * allocate cache lines on reads only mode */
172#endif /* CONFIG_BF533 */ 150#endif /* CONFIG_BF533 */
173#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ 151#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
174#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain 152#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
175 instructions */ 153 * instructions */
176#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame 154#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
177 Sync Transmit Mode */ 155 * Sync Transmit Mode */
178#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ 156#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
179#endif /* only on 0.3 silicon */ 157#endif /* only on 0.3 silicon */
180 158