aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-bf527
diff options
context:
space:
mode:
authorMichael Hennerich <michael.hennerich@analog.com>2007-10-21 04:54:27 -0400
committerBryan Wu <bryan.wu@analog.com>2007-10-21 04:54:27 -0400
commit590031450a52c373bf72f5fb156fbcc0c78c6f2c (patch)
tree0e631bc6e8af9422635535459aaaf10fdddab357 /include/asm-blackfin/mach-bf527
parentcfa76f024f7c9e65169425804e5b32e71f66d0ee (diff)
Blackfin arch: add new processor ADSP-BF52x arch/mach support
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf527')
-rw-r--r--include/asm-blackfin/mach-bf527/anomaly.h8
-rw-r--r--include/asm-blackfin/mach-bf527/bf527.h127
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h152
-rw-r--r--include/asm-blackfin/mach-bf527/blackfin.h78
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h19
-rw-r--r--include/asm-blackfin/mach-bf527/defBF527.h4
-rw-r--r--include/asm-blackfin/mach-bf527/defBF52x_base.h9
-rw-r--r--include/asm-blackfin/mach-bf527/dma.h60
-rw-r--r--include/asm-blackfin/mach-bf527/irq.h263
-rw-r--r--include/asm-blackfin/mach-bf527/mem_init.h337
-rw-r--r--include/asm-blackfin/mach-bf527/mem_map.h98
-rw-r--r--include/asm-blackfin/mach-bf527/portmux.h205
12 files changed, 1344 insertions, 16 deletions
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
index 991db986cd4b..a89120445be6 100644
--- a/include/asm-blackfin/mach-bf527/anomaly.h
+++ b/include/asm-blackfin/mach-bf527/anomaly.h
@@ -38,4 +38,12 @@
38 38
39/* Anomalies that don't exist on this proc */ 39/* Anomalies that don't exist on this proc */
40#define ANOMALY_05000323 (0) 40#define ANOMALY_05000323 (0)
41#define ANOMALY_05000244 (0)
42#define ANOMALY_05000198 (0)
43#define ANOMALY_05000125 (0)
44#define ANOMALY_05000158 (0)
45#define ANOMALY_05000273 (0)
46#define ANOMALY_05000263 (0)
47#define ANOMALY_05000311 (0)
48#define ANOMALY_05000230 (0)
41#endif 49#endif
diff --git a/include/asm-blackfin/mach-bf527/bf527.h b/include/asm-blackfin/mach-bf527/bf527.h
new file mode 100644
index 000000000000..056eb4b9cd25
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/bf527.h
@@ -0,0 +1,127 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/bf527.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF527_H__
31#define __MACH_BF527_H__
32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54#define BFIN_DSUBBANKS 4
55#define BFIN_DWAYS 2
56#define BFIN_DLINES 64
57#define BFIN_ISUBBANKS 4
58#define BFIN_IWAYS 4
59#define BFIN_ILINES 32
60
61#define WAY0_L 0x1
62#define WAY1_L 0x2
63#define WAY01_L 0x3
64#define WAY2_L 0x4
65#define WAY02_L 0x5
66#define WAY12_L 0x6
67#define WAY012_L 0x7
68
69#define WAY3_L 0x8
70#define WAY03_L 0x9
71#define WAY13_L 0xA
72#define WAY013_L 0xB
73
74#define WAY32_L 0xC
75#define WAY320_L 0xD
76#define WAY321_L 0xE
77#define WAYALL_L 0xF
78
79#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
80
81/********************************* EBIU Settings ************************************/
82#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
83#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
84
85#ifdef CONFIG_C_AMBEN_ALL
86#define V_AMBEN AMBEN_ALL
87#endif
88#ifdef CONFIG_C_AMBEN
89#define V_AMBEN 0x0
90#endif
91#ifdef CONFIG_C_AMBEN_B0
92#define V_AMBEN AMBEN_B0
93#endif
94#ifdef CONFIG_C_AMBEN_B0_B1
95#define V_AMBEN AMBEN_B0_B1
96#endif
97#ifdef CONFIG_C_AMBEN_B0_B1_B2
98#define V_AMBEN AMBEN_B0_B1_B2
99#endif
100#ifdef CONFIG_C_AMCKEN
101#define V_AMCKEN AMCKEN
102#else
103#define V_AMCKEN 0x0
104#endif
105#ifdef CONFIG_C_CDPRIO
106#define V_CDPRIO 0x100
107#else
108#define V_CDPRIO 0x0
109#endif
110
111#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
112
113#ifdef CONFIG_BF527
114#define CPU "BF527"
115#endif
116#ifdef CONFIG_BF525
117#define CPU "BF525"
118#endif
119#ifdef CONFIG_BF522
120#define CPU "BF522"
121#endif
122#ifndef CPU
123#define CPU "UNKNOWN"
124#define CPUID 0x0
125#endif
126
127#endif /* __MACH_BF527_H__ */
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
new file mode 100644
index 000000000000..0b867e6a76c4
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -0,0 +1,152 @@
1#include <linux/serial.h>
2#include <asm/dma.h>
3#include <asm/portmux.h>
4
5#define NR_PORTS 2
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
26#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
27#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28
29#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
30#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
31#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
32#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
33#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
34#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
35
36#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
37# define CONFIG_SERIAL_BFIN_CTSRTS
38
39# ifndef CONFIG_UART0_CTS_PIN
40# define CONFIG_UART0_CTS_PIN -1
41# endif
42
43# ifndef CONFIG_UART0_RTS_PIN
44# define CONFIG_UART0_RTS_PIN -1
45# endif
46
47# ifndef CONFIG_UART1_CTS_PIN
48# define CONFIG_UART1_CTS_PIN -1
49# endif
50
51# ifndef CONFIG_UART1_RTS_PIN
52# define CONFIG_UART1_RTS_PIN -1
53# endif
54#endif
55/*
56 * The pin configuration is different from schematic
57 */
58struct bfin_serial_port {
59 struct uart_port port;
60 unsigned int old_status;
61#ifdef CONFIG_SERIAL_BFIN_DMA
62 int tx_done;
63 int tx_count;
64 struct circ_buf rx_dma_buf;
65 struct timer_list rx_dma_timer;
66 int rx_dma_nrows;
67 unsigned int tx_dma_channel;
68 unsigned int rx_dma_channel;
69 struct work_struct tx_dma_workqueue;
70#else
71 struct work_struct cts_workqueue;
72#endif
73#ifdef CONFIG_SERIAL_BFIN_CTSRTS
74 int cts_pin;
75 int rts_pin;
76#endif
77};
78
79struct bfin_serial_port bfin_serial_ports[NR_PORTS];
80struct bfin_serial_res {
81 unsigned long uart_base_addr;
82 int uart_irq;
83#ifdef CONFIG_SERIAL_BFIN_DMA
84 unsigned int uart_tx_dma_channel;
85 unsigned int uart_rx_dma_channel;
86#endif
87#ifdef CONFIG_SERIAL_BFIN_CTSRTS
88 int uart_cts_pin;
89 int uart_rts_pin;
90#endif
91};
92
93struct bfin_serial_res bfin_serial_resource[] = {
94#ifdef CONFIG_SERIAL_BFIN_UART0
95 {
96 0xFFC00400,
97 IRQ_UART0_RX,
98#ifdef CONFIG_SERIAL_BFIN_DMA
99 CH_UART0_TX,
100 CH_UART0_RX,
101#endif
102#ifdef CONFIG_BFIN_UART0_CTSRTS
103 CONFIG_UART0_CTS_PIN,
104 CONFIG_UART0_RTS_PIN,
105#endif
106 },
107#endif
108#ifdef CONFIG_SERIAL_BFIN_UART1
109 {
110 0xFFC02000,
111 IRQ_UART1_RX,
112#ifdef CONFIG_SERIAL_BFIN_DMA
113 CH_UART1_TX,
114 CH_UART1_RX,
115#endif
116#ifdef CONFIG_BFIN_UART1_CTSRTS
117 CONFIG_UART1_CTS_PIN,
118 CONFIG_UART1_RTS_PIN,
119#endif
120 },
121#endif
122};
123
124int nr_ports = ARRAY_SIZE(bfin_serial_resource);
125
126#define DRIVER_NAME "bfin-uart"
127
128static void bfin_serial_hw_init(struct bfin_serial_port *uart)
129{
130
131#ifdef CONFIG_SERIAL_BFIN_UART0
132 peripheral_request(P_UART0_TX, DRIVER_NAME);
133 peripheral_request(P_UART0_RX, DRIVER_NAME);
134#endif
135
136#ifdef CONFIG_SERIAL_BFIN_UART1
137 peripheral_request(P_UART1_TX, DRIVER_NAME);
138 peripheral_request(P_UART1_RX, DRIVER_NAME);
139#endif
140
141#ifdef CONFIG_SERIAL_BFIN_CTSRTS
142 if (uart->cts_pin >= 0) {
143 gpio_request(uart->cts_pin, DRIVER_NAME);
144 gpio_direction_input(uart->cts_pin);
145 }
146
147 if (uart->rts_pin >= 0) {
148 gpio_request(uart->rts_pin, DRIVER_NAME);
149 gpio_direction_output(uart->rts_pin);
150 }
151#endif
152}
diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h
new file mode 100644
index 000000000000..1bd07e30781c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/blackfin.h
@@ -0,0 +1,78 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF527_FAMILY
36
37#include "bf527.h"
38#include "mem_map.h"
39#include "defBF522.h"
40#include "anomaly.h"
41
42#if defined(CONFIG_BF527)
43#include "defBF527.h"
44#endif
45
46#if defined(CONFIG_BF525)
47#include "defBF525.h"
48#endif
49
50#if !defined(__ASSEMBLY__)
51#include "cdefBF522.h"
52
53#if defined(CONFIG_BF527)
54#include "cdefBF527.h"
55#endif
56
57#if defined(CONFIG_BF525)
58#include "cdefBF525.h"
59#endif
60#endif
61
62/* UART_IIR Register */
63#define STATUS(x) ((x << 1) & 0x06)
64#define STATUS_P1 0x02
65#define STATUS_P0 0x01
66
67/* DPMC*/
68#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
69#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
70#define STOPCK_OFF STOPCK
71
72/* PLL_DIV Masks */
73#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
74#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
75#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
76#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
77
78#endif
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
index 5f801a0ef797..3f4de5d9d4cb 100644
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -45,8 +45,8 @@
45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
47#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) 47#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
48#define bfin_read_CHIPID() bfin_read16(CHIPID) 48#define bfin_read_CHIPID() bfin_read32(CHIPID)
49#define bfin_write_CHIPID(val) bfin_write16(CHIPID, val) 49#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
50 50
51 51
52/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 52/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
@@ -59,9 +59,8 @@
59#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) 59#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
60#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) 60#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
61#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) 61#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
62/* legacy register name (below) provided for backwards code compatibility */ 62#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
63#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) 63#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
64#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
65 64
66#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) 65#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
67#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) 66#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
@@ -74,15 +73,13 @@
74 73
75#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) 74#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
76#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) 75#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
77/* legacy register name (below) provided for backwards code compatibility */ 76#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
78#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) 77#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
79#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
80 78
81#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) 79#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
82#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) 80#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
83/* legacy register name (below) provided for backwards code compatibility */ 81#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
84#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) 82#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
85#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
86 83
87/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ 84/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
88 85
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h
index 2be3293f9e26..82134f578f32 100644
--- a/include/asm-blackfin/mach-bf527/defBF527.h
+++ b/include/asm-blackfin/mach-bf527/defBF527.h
@@ -32,12 +32,12 @@
32#define _DEF_BF527_H 32#define _DEF_BF527_H
33 33
34/* Include all Core registers and bit definitions */ 34/* Include all Core registers and bit definitions */
35#include <def_LPBlackfin.h> 35#include <asm/mach-common/def_LPBlackfin.h>
36 36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ 37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
38 38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ 39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include <defBF52x_base.h> 40#include "defBF52x_base.h"
41 41
42/* The following are the #defines needed by ADSP-BF527 that are not in the common header */ 42/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
43/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 43/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
index b1ff67db01f8..d6c24c54699d 100644
--- a/include/asm-blackfin/mach-bf527/defBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h
@@ -52,13 +52,13 @@
52#define SYSCR 0xFFC00104 /* System Configuration Register */ 52#define SYSCR 0xFFC00104 /* System Configuration Register */
53#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ 53#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
54 54
55#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ 55#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
56#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 56#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
57#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ 57#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
58#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ 58#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
59#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ 59#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
60#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ 60#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
61#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ 61#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
62 62
63/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ 63/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
64#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ 64#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
@@ -691,6 +691,8 @@
691 691
692/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ 692/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
693/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ 693/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
694
695#if 0
694#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ 696#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
695 697
696#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ 698#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
@@ -732,6 +734,7 @@
732#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ 734#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
733#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ 735#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
734#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ 736#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
737#endif
735 738
736/* SIC_IAR0 Macros */ 739/* SIC_IAR0 Macros */
737#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ 740#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h
new file mode 100644
index 000000000000..a41627ae9134
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/dma.h
@@ -0,0 +1,60 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/dma.h
3 * based on: include/asm-blackfin/mach-bf537/dma.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * system DMA map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define MAX_BLACKFIN_DMA_CHANNEL 16
36
37#define CH_PPI 0 /* PPI receive/transmit or NFC */
38#define CH_NFC 0 /* PPI receive/transmit or NFC */
39#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
40#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
41#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
42#define CH_SPORT0_RX 3 /* SPORT0 receive */
43#define CH_SPORT0_TX 4 /* SPORT0 transmit */
44#define CH_SPORT1_RX 5 /* SPORT1 receive */
45#define CH_SPORT1_TX 6 /* SPORT1 transmit */
46#define CH_SPI 7 /* SPI transmit/receive */
47#define CH_UART0_RX 8 /* UART0 receive */
48#define CH_UART0_TX 9 /* UART0 transmit */
49#define CH_UART1_RX 10 /* UART1 receive */
50#define CH_UART1_TX 11 /* UART1 transmit */
51
52#define CH_MEM_STREAM0_DEST 12 /* TX */
53#define CH_MEM_STREAM0_SRC 13 /* RX */
54#define CH_MEM_STREAM1_DEST 14 /* TX */
55#define CH_MEM_STREAM1_SRC 15 /* RX */
56
57extern int channel2irq(unsigned int channel);
58extern struct dma_register *base_addr[];
59
60#endif
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h
new file mode 100644
index 000000000000..304f5bcfebe4
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/irq.h
@@ -0,0 +1,263 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/irq.h
3 * based on: include/asm-blackfin/mach-bf537/irq.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF527_IRQ_H_
33#define _BF527_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38 Core Emulation **
39 Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47 .....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52*/
53
54#define NR_PERI_INTS (2 * 32)
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /* Emulation */
59#define IRQ_RST 1 /* reset */
60#define IRQ_NMI 2 /* Non Maskable */
61#define IRQ_EVX 3 /* Exception */
62#define IRQ_UNUSED 4 /* - unused interrupt */
63#define IRQ_HWERR 5 /* Hardware Error */
64#define IRQ_CORETMR 6 /* Core timer */
65
66#define BFIN_IRQ(x) ((x) + 7)
67
68#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
69#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
70#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
71#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
72#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
73#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
74#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
75#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
76#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
77#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
78#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
79#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
80#define IRQ_RTC BFIN_IRQ(14) /* RTC */
81#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
82#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
83#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
84#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
85#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
86#define IRQ_TWI BFIN_IRQ(20) /* TWI */
87#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
88#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
89#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
90#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
91#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
92#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
93#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
94#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
95#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
96#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
97#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
98#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
99#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */
100#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */
101#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */
102#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */
103#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */
104#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */
105#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */
106#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */
107#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
108#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
109#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
110#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
111#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
112#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
113#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
114#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
115#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
116#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
117#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
118#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
119#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
120#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
121#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
122#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
123
124#define SYS_IRQS BFIN_IRQ(63) /* 70 */
125
126#define IRQ_PF0 71
127#define IRQ_PF1 72
128#define IRQ_PF2 73
129#define IRQ_PF3 74
130#define IRQ_PF4 75
131#define IRQ_PF5 76
132#define IRQ_PF6 77
133#define IRQ_PF7 78
134#define IRQ_PF8 79
135#define IRQ_PF9 80
136#define IRQ_PF10 81
137#define IRQ_PF11 82
138#define IRQ_PF12 83
139#define IRQ_PF13 84
140#define IRQ_PF14 85
141#define IRQ_PF15 86
142
143#define IRQ_PG0 87
144#define IRQ_PG1 88
145#define IRQ_PG2 89
146#define IRQ_PG3 90
147#define IRQ_PG4 91
148#define IRQ_PG5 92
149#define IRQ_PG6 93
150#define IRQ_PG7 94
151#define IRQ_PG8 95
152#define IRQ_PG9 96
153#define IRQ_PG10 97
154#define IRQ_PG11 98
155#define IRQ_PG12 99
156#define IRQ_PG13 100
157#define IRQ_PG14 101
158#define IRQ_PG15 102
159
160#define IRQ_PH0 103
161#define IRQ_PH1 104
162#define IRQ_PH2 105
163#define IRQ_PH3 106
164#define IRQ_PH4 107
165#define IRQ_PH5 108
166#define IRQ_PH6 109
167#define IRQ_PH7 110
168#define IRQ_PH8 111
169#define IRQ_PH9 112
170#define IRQ_PH10 113
171#define IRQ_PH11 114
172#define IRQ_PH12 115
173#define IRQ_PH13 116
174#define IRQ_PH14 117
175#define IRQ_PH15 118
176
177#define GPIO_IRQ_BASE IRQ_PF0
178
179#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
180#define NR_IRQS (IRQ_PH15+1)
181#else
182#define NR_IRQS (SYS_IRQS+1)
183#endif
184
185#define IVG7 7
186#define IVG8 8
187#define IVG9 9
188#define IVG10 10
189#define IVG11 11
190#define IVG12 12
191#define IVG13 13
192#define IVG14 14
193#define IVG15 15
194
195/* IAR0 BIT FIELDS */
196#define IRQ_PLL_WAKEUP_POS 0
197#define IRQ_DMA0_ERROR_POS 4
198#define IRQ_DMAR0_BLK_POS 8
199#define IRQ_DMAR1_BLK_POS 12
200#define IRQ_DMAR0_OVR_POS 16
201#define IRQ_DMAR1_OVR_POS 20
202#define IRQ_PPI_ERROR_POS 24
203#define IRQ_MAC_ERROR_POS 28
204
205/* IAR1 BIT FIELDS */
206#define IRQ_SPORT0_ERROR_POS 0
207#define IRQ_SPORT1_ERROR_POS 4
208#define IRQ_UART0_ERROR_POS 16
209#define IRQ_UART1_ERROR_POS 20
210#define IRQ_RTC_POS 24
211#define IRQ_PPI_POS 28
212
213/* IAR2 BIT FIELDS */
214#define IRQ_SPORT0_RX_POS 0
215#define IRQ_SPORT0_TX_POS 4
216#define IRQ_SPORT1_RX_POS 8
217#define IRQ_SPORT1_TX_POS 12
218#define IRQ_TWI_POS 16
219#define IRQ_SPI_POS 20
220#define IRQ_UART0_RX_POS 24
221#define IRQ_UART0_TX_POS 28
222
223/* IAR3 BIT FIELDS */
224#define IRQ_UART1_RX_POS 0
225#define IRQ_UART1_TX_POS 4
226#define IRQ_OPTSEC_POS 8
227#define IRQ_CNT_POS 12
228#define IRQ_MAC_RX_POS 16
229#define IRQ_PORTH_INTA_POS 20
230#define IRQ_MAC_TX_POS 24
231#define IRQ_PORTH_INTB_POS 28
232
233/* IAR4 BIT FIELDS */
234#define IRQ_TMR0_POS 0
235#define IRQ_TMR1_POS 4
236#define IRQ_TMR2_POS 8
237#define IRQ_TMR3_POS 12
238#define IRQ_TMR4_POS 16
239#define IRQ_TMR5_POS 20
240#define IRQ_TMR6_POS 24
241#define IRQ_TMR7_POS 28
242
243/* IAR5 BIT FIELDS */
244#define IRQ_PORTG_INTA_POS 0
245#define IRQ_PORTG_INTB_POS 4
246#define IRQ_MEM_DMA0_POS 8
247#define IRQ_MEM_DMA1_POS 12
248#define IRQ_WATCH_POS 16
249#define IRQ_PORTF_INTA_POS 20
250#define IRQ_PORTF_INTB_POS 24
251#define IRQ_SPI_ERROR_POS 28
252
253/* IAR6 BIT FIELDS */
254#define IRQ_NFC_ERROR_POS 0
255#define IRQ_HDMA_ERROR_POS 4
256#define IRQ_HDMA_POS 8
257#define IRQ_USB_EINT_POS 12
258#define IRQ_USB_INT0_POS 16
259#define IRQ_USB_INT1_POS 20
260#define IRQ_USB_INT2_POS 24
261#define IRQ_USB_DMA_POS 28
262
263#endif /* _BF527_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf527/mem_init.h b/include/asm-blackfin/mach-bf527/mem_init.h
new file mode 100644
index 000000000000..008ca66719e2
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/mem_init.h
@@ -0,0 +1,337 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2007 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_MT48LC32M8A2_75)
122 /*SDRAM INFORMATION: */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129 /*SDRAM INFORMATION: */
130#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132#define SDRAM_CL CL_3
133#endif
134
135#if (CONFIG_MEM_GENERIC_BOARD)
136 /*SDRAM INFORMATION: Modify this for your board */
137#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139#define SDRAM_CL CL_3
140#endif
141
142#if (CONFIG_MEM_MT48LC32M16A2TG_75)
143 /*SDRAM INFORMATION: */
144#define SDRAM_Tref 64 /* Refresh period in milliseconds */
145#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
146#define SDRAM_CL CL_3
147#endif
148
149#if (CONFIG_MEM_SIZE == 128)
150#define SDRAM_SIZE EBSZ_128
151#endif
152#if (CONFIG_MEM_SIZE == 64)
153#define SDRAM_SIZE EBSZ_64
154#endif
155#if (CONFIG_MEM_SIZE == 32)
156#define SDRAM_SIZE EBSZ_32
157#endif
158#if (CONFIG_MEM_SIZE == 16)
159#define SDRAM_SIZE EBSZ_16
160#endif
161#if (CONFIG_MEM_ADD_WIDTH == 11)
162#define SDRAM_WIDTH EBCAW_11
163#endif
164#if (CONFIG_MEM_ADD_WIDTH == 10)
165#define SDRAM_WIDTH EBCAW_10
166#endif
167#if (CONFIG_MEM_ADD_WIDTH == 9)
168#define SDRAM_WIDTH EBCAW_9
169#endif
170#if (CONFIG_MEM_ADD_WIDTH == 8)
171#define SDRAM_WIDTH EBCAW_8
172#endif
173
174#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
175
176/* Equation from section 17 (p17-46) of BF533 HRM */
177#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
178
179/* Enable SCLK Out */
180#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
181
182#if defined CONFIG_CLKIN_HALF
183#define CLKIN_HALF 1
184#else
185#define CLKIN_HALF 0
186#endif
187
188#if defined CONFIG_PLL_BYPASS
189#define PLL_BYPASS 1
190#else
191#define PLL_BYPASS 0
192#endif
193
194/***************************************Currently Not Being Used *********************************/
195#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
196#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
197#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
198#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
199#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
200
201#if (flash_EBIU_AMBCTL_TT > 3)
202#define flash_EBIU_AMBCTL0_TT B0TT_4
203#endif
204#if (flash_EBIU_AMBCTL_TT == 3)
205#define flash_EBIU_AMBCTL0_TT B0TT_3
206#endif
207#if (flash_EBIU_AMBCTL_TT == 2)
208#define flash_EBIU_AMBCTL0_TT B0TT_2
209#endif
210#if (flash_EBIU_AMBCTL_TT < 2)
211#define flash_EBIU_AMBCTL0_TT B0TT_1
212#endif
213
214#if (flash_EBIU_AMBCTL_ST > 3)
215#define flash_EBIU_AMBCTL0_ST B0ST_4
216#endif
217#if (flash_EBIU_AMBCTL_ST == 3)
218#define flash_EBIU_AMBCTL0_ST B0ST_3
219#endif
220#if (flash_EBIU_AMBCTL_ST == 2)
221#define flash_EBIU_AMBCTL0_ST B0ST_2
222#endif
223#if (flash_EBIU_AMBCTL_ST < 2)
224#define flash_EBIU_AMBCTL0_ST B0ST_1
225#endif
226
227#if (flash_EBIU_AMBCTL_HT > 2)
228#define flash_EBIU_AMBCTL0_HT B0HT_3
229#endif
230#if (flash_EBIU_AMBCTL_HT == 2)
231#define flash_EBIU_AMBCTL0_HT B0HT_2
232#endif
233#if (flash_EBIU_AMBCTL_HT == 1)
234#define flash_EBIU_AMBCTL0_HT B0HT_1
235#endif
236#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
237#define flash_EBIU_AMBCTL0_HT B0HT_0
238#endif
239#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
240#define flash_EBIU_AMBCTL0_HT B0HT_1
241#endif
242
243#if (flash_EBIU_AMBCTL_WAT > 14)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_15
245#endif
246#if (flash_EBIU_AMBCTL_WAT == 14)
247#define flash_EBIU_AMBCTL0_WAT B0WAT_14
248#endif
249#if (flash_EBIU_AMBCTL_WAT == 13)
250#define flash_EBIU_AMBCTL0_WAT B0WAT_13
251#endif
252#if (flash_EBIU_AMBCTL_WAT == 12)
253#define flash_EBIU_AMBCTL0_WAT B0WAT_12
254#endif
255#if (flash_EBIU_AMBCTL_WAT == 11)
256#define flash_EBIU_AMBCTL0_WAT B0WAT_11
257#endif
258#if (flash_EBIU_AMBCTL_WAT == 10)
259#define flash_EBIU_AMBCTL0_WAT B0WAT_10
260#endif
261#if (flash_EBIU_AMBCTL_WAT == 9)
262#define flash_EBIU_AMBCTL0_WAT B0WAT_9
263#endif
264#if (flash_EBIU_AMBCTL_WAT == 8)
265#define flash_EBIU_AMBCTL0_WAT B0WAT_8
266#endif
267#if (flash_EBIU_AMBCTL_WAT == 7)
268#define flash_EBIU_AMBCTL0_WAT B0WAT_7
269#endif
270#if (flash_EBIU_AMBCTL_WAT == 6)
271#define flash_EBIU_AMBCTL0_WAT B0WAT_6
272#endif
273#if (flash_EBIU_AMBCTL_WAT == 5)
274#define flash_EBIU_AMBCTL0_WAT B0WAT_5
275#endif
276#if (flash_EBIU_AMBCTL_WAT == 4)
277#define flash_EBIU_AMBCTL0_WAT B0WAT_4
278#endif
279#if (flash_EBIU_AMBCTL_WAT == 3)
280#define flash_EBIU_AMBCTL0_WAT B0WAT_3
281#endif
282#if (flash_EBIU_AMBCTL_WAT == 2)
283#define flash_EBIU_AMBCTL0_WAT B0WAT_2
284#endif
285#if (flash_EBIU_AMBCTL_WAT == 1)
286#define flash_EBIU_AMBCTL0_WAT B0WAT_1
287#endif
288
289#if (flash_EBIU_AMBCTL_RAT > 14)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_15
291#endif
292#if (flash_EBIU_AMBCTL_RAT == 14)
293#define flash_EBIU_AMBCTL0_RAT B0RAT_14
294#endif
295#if (flash_EBIU_AMBCTL_RAT == 13)
296#define flash_EBIU_AMBCTL0_RAT B0RAT_13
297#endif
298#if (flash_EBIU_AMBCTL_RAT == 12)
299#define flash_EBIU_AMBCTL0_RAT B0RAT_12
300#endif
301#if (flash_EBIU_AMBCTL_RAT == 11)
302#define flash_EBIU_AMBCTL0_RAT B0RAT_11
303#endif
304#if (flash_EBIU_AMBCTL_RAT == 10)
305#define flash_EBIU_AMBCTL0_RAT B0RAT_10
306#endif
307#if (flash_EBIU_AMBCTL_RAT == 9)
308#define flash_EBIU_AMBCTL0_RAT B0RAT_9
309#endif
310#if (flash_EBIU_AMBCTL_RAT == 8)
311#define flash_EBIU_AMBCTL0_RAT B0RAT_8
312#endif
313#if (flash_EBIU_AMBCTL_RAT == 7)
314#define flash_EBIU_AMBCTL0_RAT B0RAT_7
315#endif
316#if (flash_EBIU_AMBCTL_RAT == 6)
317#define flash_EBIU_AMBCTL0_RAT B0RAT_6
318#endif
319#if (flash_EBIU_AMBCTL_RAT == 5)
320#define flash_EBIU_AMBCTL0_RAT B0RAT_5
321#endif
322#if (flash_EBIU_AMBCTL_RAT == 4)
323#define flash_EBIU_AMBCTL0_RAT B0RAT_4
324#endif
325#if (flash_EBIU_AMBCTL_RAT == 3)
326#define flash_EBIU_AMBCTL0_RAT B0RAT_3
327#endif
328#if (flash_EBIU_AMBCTL_RAT == 2)
329#define flash_EBIU_AMBCTL0_RAT B0RAT_2
330#endif
331#if (flash_EBIU_AMBCTL_RAT == 1)
332#define flash_EBIU_AMBCTL0_RAT B0RAT_1
333#endif
334
335#define flash_EBIU_AMBCTL0 \
336 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
337 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
new file mode 100644
index 000000000000..c5aa20102b24
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/mem_map.h
@@ -0,0 +1,98 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/mem_map.h
3 * based on: include/asm-blackfin/mach-bf537/mem_map.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF527/5/2 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_527_H_
32#define _MEM_MAP_527_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50
51/* Level 1 Memory */
52
53/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
54
55#ifdef CONFIG_BFIN_ICACHE
56#define BFIN_ICACHESIZE (16*1024)
57#else
58#define BFIN_ICACHESIZE (0*1024)
59#endif
60
61#define L1_CODE_START 0xFFA00000
62#define L1_DATA_A_START 0xFF800000
63#define L1_DATA_B_START 0xFF900000
64
65#define L1_CODE_LENGTH 0xC000
66
67#ifdef CONFIG_BFIN_DCACHE
68
69#ifdef CONFIG_BFIN_DCACHE_BANKA
70#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
71#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
72#define L1_DATA_B_LENGTH 0x8000
73#define BFIN_DCACHESIZE (16*1024)
74#define BFIN_DSUPBANKS 1
75#else
76#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
77#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
78#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
79#define BFIN_DCACHESIZE (32*1024)
80#define BFIN_DSUPBANKS 2
81#endif
82
83#else
84#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
85#define L1_DATA_A_LENGTH 0x8000
86#define L1_DATA_B_LENGTH 0x8000
87#define BFIN_DCACHESIZE (0*1024)
88#define BFIN_DSUPBANKS 0
89#endif /*CONFIG_BFIN_DCACHE */
90
91/* Scratch Pad Memory */
92
93#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
94#define L1_SCRATCH_START 0xFFB00000
95#define L1_SCRATCH_LENGTH 0x1000
96#endif
97
98#endif /* _MEM_MAP_527_H_ */
diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h
new file mode 100644
index 000000000000..dcf001adc63c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/portmux.h
@@ -0,0 +1,205 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
5#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
6#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
7#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
8#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
9#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
10#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
11#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
12#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
13#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
14#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
15#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
16#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
17#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
18#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
19#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
20
21#if defined(CONFIG_BF527_SPORT0_PORTF)
22#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
23#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
24#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
25#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
26#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
27#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
28#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
29#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
30#elif defined(CONFIG_BF527_SPORT0_PORTG)
31#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
32#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
33#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
34#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
35#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
36#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
37#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
38#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
39#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
40#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
41#endif
42#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
43#endif
44
45#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
46#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
47#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
48#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
49#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
50#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
51#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
52#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
53
54#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
55#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
56
57#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
58#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
59
60#if defined(CONFIG_BF527_UART1_PORTF)
61#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
62#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
63#elif defined(CONFIG_BF527_UART1_PORTG)
64#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
65#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
66#endif
67
68#define P_HWAIT (P_DONTCARE)
69
70#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
71#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
72#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
73#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
74#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
75#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
76#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
77#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
78#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
79#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
80#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
81/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
82#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
83#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
84#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
85#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
86#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
87#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
88#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
89
90#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
91#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
92#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
93
94#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
95#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
96#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
97#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
98#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
99
100#if defined(CONFIG_BF527_NAND_D_PORTF)
101#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
102#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
103#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
104#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
105#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
106#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
107#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
108#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
109#elif defined(CONFIG_BF527_NAND_D_PORTH)
110#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
111#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
112#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
113#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
114#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
115#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
116#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
117#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
118#endif
119
120#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
121#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
122#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
123#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
124#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
125#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
126#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
127#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
128
129#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
130#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
131#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
132#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
133#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
134#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
135#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
136#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
137#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
138#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
139#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
140#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
141#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
142#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
143#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
144#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
145
146#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
147#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
148#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
149#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
150#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
151#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
152#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
153#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
154#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
155#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
156#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
157#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
158#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
159#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
160#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
161#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
162#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
163#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
164
165#define P_TWI0_SCL (P_DONTCARE)
166#define P_TWI0_SDA (P_DONTCARE)
167#define P_PPI0_FS1 (P_DONTCARE)
168#define P_TMR0 (P_DONTCARE)
169#define P_TMRCLK (P_DONTCARE)
170#define P_PPI0_CLK (P_DONTCARE)
171
172#define P_MII0 {\
173 P_MII0_ETxD0, \
174 P_MII0_ETxD1, \
175 P_MII0_ETxD2, \
176 P_MII0_ETxD3, \
177 P_MII0_ETxEN, \
178 P_MII0_TxCLK, \
179 P_MII0_PHYINT, \
180 P_MII0_COL, \
181 P_MII0_ERxD0, \
182 P_MII0_ERxD1, \
183 P_MII0_ERxD2, \
184 P_MII0_ERxD3, \
185 P_MII0_ERxDV, \
186 P_MII0_ERxCLK, \
187 P_MII0_ERxER, \
188 P_MII0_CRS, \
189 P_MDC, \
190 P_MDIO, 0}
191
192#define P_RMII0 {\
193 P_MII0_ETxD0, \
194 P_MII0_ETxD1, \
195 P_MII0_ETxEN, \
196 P_MII0_ERxD0, \
197 P_MII0_ERxD1, \
198 P_MII0_ERxER, \
199 P_RMII0_REF_CLK, \
200 P_RMII0_MDINT, \
201 P_RMII0_CRS_DV, \
202 P_MDC, \
203 P_MDIO, 0}
204
205#endif /* _MACH_PORTMUX_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 09:58:26 -0500