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authorBryan Wu <bryan.wu@analog.com>2007-05-21 06:09:31 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-21 12:50:23 -0400
commit19381f024b01413d83cec1655c3fc4c9c09ae274 (patch)
tree4ba1d63900e031c97130638c2d678aaf15c3d37e /include/asm-blackfin/mach-bf527
parentc09c4e006590210001ced90d59e62182bfd396f9 (diff)
Blackfin arch: update blackfin header files to latest one in VDSP.
a) add new processor BF52x/BF54x header files b) update blackfin BF533/BF537/BF561 header files to latest one in VDSP. c) scrub watchdog/rtc masks from headers as we dont need/want them (too generic and the drivers dont use them) Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf527')
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF522.h46
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF525.h461
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF527.h626
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h1187
-rw-r--r--include/asm-blackfin/mach-bf527/defBF522.h42
-rw-r--r--include/asm-blackfin/mach-bf527/defBF525.h713
-rw-r--r--include/asm-blackfin/mach-bf527/defBF527.h1089
-rw-r--r--include/asm-blackfin/mach-bf527/defBF52x_base.h2009
8 files changed, 6173 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf527/cdefBF522.h b/include/asm-blackfin/mach-bf527/cdefBF522.h
new file mode 100644
index 000000000000..52c06494b886
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF522.h
@@ -0,0 +1,46 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefbf522.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF522_H
33#define _CDEF_BF522_H
34
35/* include all Core registers and bit definitions */
36#include "defBF522.h"
37
38/* include core specific register pointer definitions */
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
42
43/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
44#include "cdefBF52x_base.h"
45
46#endif /* _CDEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF525.h b/include/asm-blackfin/mach-bf527/cdefBF525.h
new file mode 100644
index 000000000000..2cc67e4b4d86
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF525.h
@@ -0,0 +1,461 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefbf525.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF525_H
33#define _CDEF_BF525_H
34
35/* include all Core registers and bit definitions */
36#include "defBF525.h"
37
38/* include core specific register pointer definitions */
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
42
43/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
44#include "cdefBF52x_base.h"
45
46/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
47
48/* USB Control Registers */
49
50#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
51#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
52#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
53#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
54#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
55#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
56#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
57#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
58#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
59#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
60#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
61#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
62#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
63#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
64#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
65#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
66#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
67#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
68#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
69#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
70#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
71#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
72#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
73#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
74#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
75#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
76
77/* USB Packet Control Registers */
78
79#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
80#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
81#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
82#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
83#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
84#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
85#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
86#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
87#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
88#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
89#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
90#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
91#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
92#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
93#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
94#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
95#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
96#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
97#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
98#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
99#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
100#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
101#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
102#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
103#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
104#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
105
106/* USB Endpoint FIFO Registers */
107
108#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
109#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
110#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
111#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
112#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
113#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
114#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
115#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
116#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
117#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
118#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
119#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
120#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
121#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
122#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
123#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
124
125/* USB OTG Control Registers */
126
127#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
128#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
129#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
130#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
131#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
132#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
133
134/* USB Phy Control Registers */
135
136#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
137#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
138#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
139#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
140#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
141#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
142#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
143#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
144#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
145#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
146
147/* (APHY_CNTRL is for ADI usage only) */
148
149#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
150#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
151
152/* (APHY_CALIB is for ADI usage only) */
153
154#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
155#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
156
157#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
158#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
159
160/* (PHY_TEST is for ADI usage only) */
161
162#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
163#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
164
165#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
166#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
167#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
168#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
169
170/* USB Endpoint 0 Control Registers */
171
172#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
173#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
174#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
175#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
176#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
177#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
178#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
179#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
180#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
181#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
182#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
183#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
184#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
185#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
186#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
187#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
188#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
189#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
190#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
191#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
192
193/* USB Endpoint 1 Control Registers */
194
195#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
196#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
197#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
198#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
199#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
200#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
201#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
202#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
203#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
204#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
205#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
206#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
207#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
208#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
209#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
210#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
211#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
212#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
213#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
214#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
215
216/* USB Endpoint 2 Control Registers */
217
218#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
219#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
220#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
221#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
222#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
223#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
224#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
225#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
226#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
227#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
228#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
229#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
230#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
231#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
232#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
233#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
234#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
235#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
236#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
237#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
238
239/* USB Endpoint 3 Control Registers */
240
241#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
242#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
243#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
244#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
245#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
246#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
247#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
248#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
249#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
250#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
251#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
252#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
253#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
254#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
255#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
256#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
257#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
258#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
259#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
260#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
261
262/* USB Endpoint 4 Control Registers */
263
264#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
265#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
266#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
267#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
268#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
269#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
270#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
271#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
272#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
273#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
274#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
275#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
276#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
277#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
278#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
279#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
280#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
281#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
282#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
283#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
284
285/* USB Endpoint 5 Control Registers */
286
287#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
288#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
289#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
290#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
291#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
292#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
293#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
294#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
295#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
296#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
297#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
298#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
299#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
300#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
301#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
302#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
303#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
304#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
305#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
306#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
307
308/* USB Endpoint 6 Control Registers */
309
310#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
311#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
312#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
313#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
314#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
315#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
316#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
317#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
318#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
319#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
320#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
321#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
322#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
323#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
324#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
325#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
326#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
327#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
328#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
329#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
330
331/* USB Endpoint 7 Control Registers */
332
333#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
334#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
335#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
336#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
337#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
338#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
339#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
340#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
341#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
342#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
343#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
344#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
345#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
346#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
347#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
348#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
349#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
350#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
351#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
352#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
353
354#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
355#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
356
357/* USB Channel 0 Config Registers */
358
359#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
360#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
361#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
362#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
363#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
364#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
365#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
366#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
367#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
368#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
369
370/* USB Channel 1 Config Registers */
371
372#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
373#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
374#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
375#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
376#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
377#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
378#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
379#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
380#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
381#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
382
383/* USB Channel 2 Config Registers */
384
385#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
386#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
387#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
388#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
389#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
390#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
391#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
392#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
393#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
394#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
395
396/* USB Channel 3 Config Registers */
397
398#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
399#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
400#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
401#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
402#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
403#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
404#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
405#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
406#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
407#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
408
409/* USB Channel 4 Config Registers */
410
411#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
412#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
413#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
414#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
415#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
416#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
417#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
418#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
419#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
420#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
421
422/* USB Channel 5 Config Registers */
423
424#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
425#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
426#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
427#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
428#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
429#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
430#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
431#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
432#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
433#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
434
435/* USB Channel 6 Config Registers */
436
437#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
438#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
439#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
440#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
441#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
442#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
443#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
444#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
445#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
446#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
447
448/* USB Channel 7 Config Registers */
449
450#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
451#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
452#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
453#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
454#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
455#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
456#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
457#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
458#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
459#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
460
461#endif /* _CDEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF527.h b/include/asm-blackfin/mach-bf527/cdefBF527.h
new file mode 100644
index 000000000000..5bd1a8601743
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF527.h
@@ -0,0 +1,626 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefbf527.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF527_H
33#define _CDEF_BF527_H
34
35/* include all Core registers and bit definitions */
36#include "defBF527.h"
37
38/* include core specific register pointer definitions */
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
42
43/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
44#include "cdefBF52x_base.h"
45
46/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
47
48/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
49
50#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
51#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
52#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
53#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
54#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
55#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
56#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
57#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
58#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
59#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
60#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
61#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
62#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
63#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
64#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
65#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
66#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
67#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
68#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
69#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
70#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
71#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
72#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
73#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
74#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
75#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
76#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
77#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
78#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
79#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
80#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
81#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
82#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
83#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
84#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
85#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
86#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
87#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
88
89#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
90#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
91#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
92#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
93#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
94#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
95#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
96#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
97#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
98#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
99#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
100#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
101#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
102#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
103#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
104#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
105
106#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
107#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
108#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
109#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
110#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
111#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
112#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
113#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
114#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
115#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
116
117#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
118#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
119#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
120#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
121#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
122#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
123#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
124#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
125#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
126#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
127#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
128#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
129#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
130#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
131#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
132#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
133#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
134#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
135#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
136#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
137#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
138#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
139#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
140#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
141#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
142#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
143#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
144#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
145#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
146#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
147#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
148#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
149#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
150#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
151#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
152#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
153#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
154#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
155#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
156#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
157#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
158#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
159#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
160#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
161#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
162#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
163#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
164#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
165
166#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
167#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
168#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
169#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
170#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
171#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
172#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
173#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
174#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
175#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
176#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
177#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
178#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
179#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
180#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
181#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
182#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
183#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
184#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
185#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
186#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
187#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
188#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
189#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
190#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
191#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
192#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
193#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
194#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
195#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
196#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
197#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
198#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
199#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
200#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
201#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
202#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
203#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
204#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
205#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
206#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
207#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
208#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
209#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
210#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
211#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
212
213/* USB Control Registers */
214
215#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
216#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
217#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
218#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
219#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
220#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
221#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
222#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
223#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
224#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
225#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
226#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
227#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
228#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
229#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
230#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
231#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
232#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
233#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
234#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
235#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
236#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
237#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
238#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
239#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
240#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
241
242/* USB Packet Control Registers */
243
244#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
245#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
246#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
247#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
248#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
249#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
250#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
251#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
252#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
253#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
254#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
255#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
256#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
257#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
258#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
259#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
260#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
261#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
262#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
263#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
264#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
265#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
266#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
267#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
268#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
269#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
270
271/* USB Endpoint FIFO Registers */
272
273#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
274#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
275#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
276#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
277#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
278#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
279#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
280#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
281#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
282#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
283#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
284#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
285#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
286#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
287#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
288#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
289
290/* USB OTG Control Registers */
291
292#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
293#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
294#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
295#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
296#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
297#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
298
299/* USB Phy Control Registers */
300
301#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
302#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
303#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
304#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
305#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
306#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
307#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
308#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
309#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
310#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
311
312/* (APHY_CNTRL is for ADI usage only) */
313
314#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
315#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
316
317/* (APHY_CALIB is for ADI usage only) */
318
319#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
320#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
321
322#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
323#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
324
325/* (PHY_TEST is for ADI usage only) */
326
327#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
328#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
329
330#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
331#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
332#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
333#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
334
335/* USB Endpoint 0 Control Registers */
336
337#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
338#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
339#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
340#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
341#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
342#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
343#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
344#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
345#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
346#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
347#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
348#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
349#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
350#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
351#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
352#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
353#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
354#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
355#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
356#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
357
358/* USB Endpoint 1 Control Registers */
359
360#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
361#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
362#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
363#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
364#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
365#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
366#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
367#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
368#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
369#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
370#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
371#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
372#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
373#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
374#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
375#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
376#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
377#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
378#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
379#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
380
381/* USB Endpoint 2 Control Registers */
382
383#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
384#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
385#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
386#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
387#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
388#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
389#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
390#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
391#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
392#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
393#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
394#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
395#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
396#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
397#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
398#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
399#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
400#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
401#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
402#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
403
404/* USB Endpoint 3 Control Registers */
405
406#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
407#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
408#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
409#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
410#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
411#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
412#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
413#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
414#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
415#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
416#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
417#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
418#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
419#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
420#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
421#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
422#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
423#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
424#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
425#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
426
427/* USB Endpoint 4 Control Registers */
428
429#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
430#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
431#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
432#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
433#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
434#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
435#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
436#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
437#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
438#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
439#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
440#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
441#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
442#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
443#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
444#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
445#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
446#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
447#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
448#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
449
450/* USB Endpoint 5 Control Registers */
451
452#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
453#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
454#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
455#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
456#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
457#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
458#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
459#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
460#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
461#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
462#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
463#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
464#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
465#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
466#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
467#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
468#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
469#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
470#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
471#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
472
473/* USB Endpoint 6 Control Registers */
474
475#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
476#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
477#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
478#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
479#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
480#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
481#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
482#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
483#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
484#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
485#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
486#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
487#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
488#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
489#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
490#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
491#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
492#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
493#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
494#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
495
496/* USB Endpoint 7 Control Registers */
497
498#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
499#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
500#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
501#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
502#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
503#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
504#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
505#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
506#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
507#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
508#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
509#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
510#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
511#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
512#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
513#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
514#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
515#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
516#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
517#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
518
519#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
520#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
521
522/* USB Channel 0 Config Registers */
523
524#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
525#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
526#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
527#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
528#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
529#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
530#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
531#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
532#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
533#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
534
535/* USB Channel 1 Config Registers */
536
537#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
538#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
539#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
540#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
541#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
542#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
543#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
544#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
545#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
546#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
547
548/* USB Channel 2 Config Registers */
549
550#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
551#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
552#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
553#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
554#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
555#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
556#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
557#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
558#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
559#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
560
561/* USB Channel 3 Config Registers */
562
563#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
564#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
565#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
566#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
567#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
568#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
569#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
570#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
571#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
572#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
573
574/* USB Channel 4 Config Registers */
575
576#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
577#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
578#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
579#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
580#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
581#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
582#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
583#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
584#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
585#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
586
587/* USB Channel 5 Config Registers */
588
589#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
590#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
591#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
592#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
593#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
594#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
595#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
596#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
597#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
598#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
599
600/* USB Channel 6 Config Registers */
601
602#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
603#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
604#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
605#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
606#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
607#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
608#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
609#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
610#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
611#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
612
613/* USB Channel 7 Config Registers */
614
615#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
616#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
617#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
618#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
619#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
620#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
621#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
622#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
623#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
624#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
625
626#endif /* _CDEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
new file mode 100644
index 000000000000..5f801a0ef797
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -0,0 +1,1187 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefBF52x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF52X_H
32
33#include "defBF52x_base.h"
34
35/* ==== begin from cdefBF534.h ==== */
36
37/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
38#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
39#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
40#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
41#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
42#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
43#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
44#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
47#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
48#define bfin_read_CHIPID() bfin_read16(CHIPID)
49#define bfin_write_CHIPID(val) bfin_write16(CHIPID, val)
50
51
52/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
53#define bfin_read_SWRST() bfin_read16(SWRST)
54#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
55#define bfin_read_SYSCR() bfin_read16(SYSCR)
56#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
57
58#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
59#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
60#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
61#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
62/* legacy register name (below) provided for backwards code compatibility */
63#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
64#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
65
66#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
67#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
68#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
69#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
70#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
71#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
72#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
73#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
74
75#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
76#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
77/* legacy register name (below) provided for backwards code compatibility */
78#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
79#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
80
81#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
82#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
83/* legacy register name (below) provided for backwards code compatibility */
84#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
85#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
86
87/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
88
89#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
90#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
91#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
92#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
93#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
94#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
95#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
96#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
97#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
98#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
99#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
100#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
101#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
102#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
103
104/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
105#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
106#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
107#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
108#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
109#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
110#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
111
112
113/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
114#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
115#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
116#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
117#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
118#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
119#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
120#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
121#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
122#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
123#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
124#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
125#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
126#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
127#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
128
129
130/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
131#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
132#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
133#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
134#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
135#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
136#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
137#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
138#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
139#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
140#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
141#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
142#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
143#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
144#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
145#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
146#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
147#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
148#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
149#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
150#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
151#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
152#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
153#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
154#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
155
156
157/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
158#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
159#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
160#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
161#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
162#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
163#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
164#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
165#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
166#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
167#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
168#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
169#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
170#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
171#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
172
173
174/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
175#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
176#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
177#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
178#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
179#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
180#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
181#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
182#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
183
184#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
185#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
186#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
187#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
188#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
189#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
190#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
191#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
192
193#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
194#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
195#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
196#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
197#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
198#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
199#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
200#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
201
202#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
203#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
204#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
205#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
206#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
207#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
208#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
209#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
210
211#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
212#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
213#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
214#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
215#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
216#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
217#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
218#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
219
220#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
221#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
222#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
223#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
224#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
225#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
226#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
227#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
228
229#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
230#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
231#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
232#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
233#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
234#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
235#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
236#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
237
238#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
239#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
240#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
241#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
242#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
243#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
244#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
245#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
246
247#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
248#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
249#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
250#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
251#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
252#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
253
254
255/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
256#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
257#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
258#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
259#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
260#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
261#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
262#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
263#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
264#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
265#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
266#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
267#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
268#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
269#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
270#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
271#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
272#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
273#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
274#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
275#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
276#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
277#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
278#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
279#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
280#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
281#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
282#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
283#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
284#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
285#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
286#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
287#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
288#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
289#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
290
291
292/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
293#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
294#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
295#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
296#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
297#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
298#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
299#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
300#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
301#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
302#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
303#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
304#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
305#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32)
306#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val)
307#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32)
308#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val)
309#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16)
310#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val)
311#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16)
312#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val)
313#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
314#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
315#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
316#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
317#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
318#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
319#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
320#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
321#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
322#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
323#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
324#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
325#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
326#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
327#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
328#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
329#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
330#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
331#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
332#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
333#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
334#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
335#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
336#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
337#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
338#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
339#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
340#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
341#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
342#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
343#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
344#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
345
346
347/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
348#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
349#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
350#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
351#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
352#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
353#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
354#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
355#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
356#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
357#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
358#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
359#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
360#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32)
361#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val)
362#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32)
363#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val)
364#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16)
365#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val)
366#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16)
367#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val)
368#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
369#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
370#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
371#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
372#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
373#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
374#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
375#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
376#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
377#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
378#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
379#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
380#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
381#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
382#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
383#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
384#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
385#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
386#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
387#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
388#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
389#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
390#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
391#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
392#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
393#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
394#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
395#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
396#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
397#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
398#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
399#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
400
401
402/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
403#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
404#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
405#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
406#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
407#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
408#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
409#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
410#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
411#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
412#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
413#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
414#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
415#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
416#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
417
418
419/* DMA Traffic Control Registers */
420#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
421#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
422#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
423#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
424
425/* Alternate deprecated register names (below) provided for backwards code compatibility */
426#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
427#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
428#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
429#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
430
431/* DMA Controller */
432#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
433#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
434#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
435#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
436#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
437#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
438#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
439#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
440#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
441#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
442#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
443#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
444#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
445#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
446#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
447#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
448#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
449#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
450#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
451#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
452#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
453#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
454#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
455#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
456#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
457#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
458
459#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
460#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
461#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
462#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
463#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
464#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
465#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
466#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
467#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
468#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
469#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
470#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
471#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
472#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
473#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
474#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
475#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
476#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
477#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
478#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
479#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
480#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
481#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
482#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
483#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
484#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
485
486#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
487#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
488#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
489#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
490#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
491#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
492#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
493#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
494#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
495#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
496#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
497#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
498#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
499#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
500#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
501#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
502#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
503#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
504#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
505#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
506#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
507#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
508#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
509#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
510#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
511#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
512
513#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
514#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
515#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
516#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
517#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
518#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
519#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
520#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
521#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
522#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
523#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
524#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
525#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
526#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
527#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
528#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
529#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
530#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
531#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
532#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
533#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
534#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
535#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
536#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
537#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
538#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
539
540#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
541#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
542#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
543#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
544#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
545#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
546#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
547#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
548#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
549#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
550#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
551#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
552#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
553#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
554#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
555#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
556#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
557#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
558#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
559#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
560#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
561#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
562#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
563#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
564#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
565#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
566
567#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
568#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
569#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
570#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
571#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
572#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
573#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
574#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
575#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
576#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
577#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
578#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
579#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
580#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
581#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
582#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
583#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
584#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
585#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
586#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
587#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
588#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
589#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
590#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
591#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
592#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
593
594#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
595#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
596#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
597#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
598#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
599#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
600#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
601#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
602#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
603#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
604#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
605#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
606#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
607#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
608#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
609#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
610#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
611#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
612#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
613#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
614#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
615#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
616#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
617#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
618#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
619#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
620
621#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
622#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
623#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
624#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
625#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
626#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
627#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
628#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
629#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
630#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
631#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
632#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
633#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
634#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
635#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
636#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
637#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
638#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
639#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
640#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
641#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
642#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
643#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
644#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
645#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
646#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
647
648#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
649#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
650#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
651#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
652#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
653#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
654#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
655#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
656#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
657#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
658#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
659#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
660#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
661#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
662#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
663#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
664#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
665#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
666#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
667#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
668#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
669#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
670#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
671#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
672#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
673#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
674
675#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
676#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
677#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
678#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
679#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
680#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
681#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
682#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
683#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
684#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
685#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
686#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
687#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
688#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
689#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
690#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
691#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
692#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
693#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
694#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
695#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
696#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
697#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
698#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
699#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
700#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
701
702#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
703#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
704#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
705#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
706#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
707#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
708#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
709#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
710#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
711#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
712#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
713#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
714#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
715#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
716#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
717#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
718#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
719#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
720#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
721#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
722#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
723#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
724#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
725#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
726#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
727#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
728
729#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
730#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
731#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
732#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
733#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
734#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
735#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
736#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
737#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
738#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
739#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
740#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
741#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
742#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
743#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
744#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
745#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
746#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
747#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
748#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
749#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
750#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
751#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
752#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
753#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
754#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
755
756#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
757#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
758#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
759#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
760#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
761#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
762#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
763#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
764#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
765#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
766#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
767#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
768#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
769#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
770#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
771#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
772#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
773#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
774#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
775#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
776#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
777#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
778#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
779#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
780#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
781#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
782
783#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
784#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
785#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
786#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
787#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
788#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
789#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
790#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
791#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
792#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
793#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
794#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
795#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
796#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
797#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
798#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
799#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
800#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
801#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
802#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
803#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
804#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
805#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
806#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
807#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
808#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
809
810#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
811#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
812#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
813#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
814#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
815#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
816#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
817#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
818#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
819#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
820#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
821#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
822#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
823#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
824#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
825#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
826#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
827#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
828#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
829#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
830#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
831#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
832#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
833#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
834#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
835#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
836
837#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
838#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
839#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
840#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
841#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
842#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
843#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
844#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
845#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
846#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
847#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
848#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
849#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
850#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
851#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
852#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
853#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
854#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
855#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
856#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
857#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
858#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
859#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
860#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
861#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
862#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
863
864
865/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
866#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
867#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
868#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
869#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
870#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
871#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
872#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
873#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
874#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
875#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
876
877
878/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
879#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
880#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
881#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
882#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
883#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
884#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
885#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
886#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
887#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
888#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
889#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
890#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
891#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
892#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
893#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
894#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
895#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
896#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
897#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
898#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
899#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
900#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
901#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
902#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
903#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
904#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
905#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
906#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
907#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
908#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
909#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
910#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
911
912
913/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
914#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
915#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
916#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
917#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
918#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
919#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
920#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
921#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
922#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
923#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
924#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
925#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
926#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
927#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
928#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
929#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
930#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
931#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
932#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
933#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
934#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
935#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
936#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
937#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
938#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
939#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
940#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
941#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
942#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
943#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
944#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
945#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
946#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
947#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
948
949
950/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
951#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
952#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
953#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
954#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
955#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
956#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
957#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
958#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
959#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
960#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
961#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
962#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
963#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
964#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
965#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
966#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
967#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
968#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
969#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
970#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
971#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
972#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
973#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
974#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
975#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
976#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
977#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
978#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
979#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
980#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
981#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
982#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
983#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
984#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
985
986
987/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
988#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
989#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
990#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
991#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
992#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
993#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
994#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
995#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
996#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
997#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
998#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
999#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
1000#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
1001#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1002#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
1003#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1004#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
1005#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1006#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
1007#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1008#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
1009#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1010#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
1011#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1012
1013/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
1014
1015/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
1016#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1017#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
1018#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1019#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1020#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1021#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1022#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
1023#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
1024
1025
1026/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
1027#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1028#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1029#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1030#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1031#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1032#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1033#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1034#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1035#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1036#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1037#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1038#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1039#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1040#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1041
1042#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1043#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1044#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1045#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1046#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1047#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1048#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1049#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1050#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1051#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1052#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1053#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1054#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1055#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1056
1057/* ==== end from cdefBF534.h ==== */
1058
1059/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
1060
1061#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
1062#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
1063#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
1064#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
1065#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
1066#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
1067
1068#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
1069#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1070#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
1071#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1072#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1073#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1074#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1075#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1076#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1077#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1078#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1079#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1080#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
1081#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
1082#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
1083#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
1084#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
1085#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
1086#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1087#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1088#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1089#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1090#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1091#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1092
1093/* HOST Port Registers */
1094
1095#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1096#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1097#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1098#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1099#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1100#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1101
1102/* Counter Registers */
1103
1104#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1105#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1106#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1107#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1108#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1109#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1110#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1111#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1112#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1113#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1114#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1115#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1116#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1117#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1118#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1119#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1120
1121/* OTP/FUSE Registers */
1122
1123#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
1124#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
1125#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
1126#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
1127#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
1128#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
1129#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
1130#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
1131
1132/* Security Registers */
1133
1134#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1135#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1136#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1137#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1138#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1139#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1140
1141/* OTP Read/Write Data Buffer Registers */
1142
1143#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
1144#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
1145#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
1146#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
1147#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
1148#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
1149#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
1150#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
1151
1152/* NFC Registers */
1153
1154#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1155#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1156#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1157#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1158#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1159#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1160#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1161#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1162#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1163#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1164#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1165#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1166#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1167#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1168#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1169#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1170#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1171#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1172#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1173#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1174#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1175#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1176#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1177#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1178#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1179#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1180#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1181#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1182#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1183#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1184#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1185#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1186
1187#endif /* _CDEF_BF52X_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF522.h b/include/asm-blackfin/mach-bf527/defBF522.h
new file mode 100644
index 000000000000..9671d8f2c5ef
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF522.h
@@ -0,0 +1,42 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF522.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF522_H
32#define _DEF_BF522_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include "defBF52x_base.h"
41
42#endif /* _DEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF525.h b/include/asm-blackfin/mach-bf527/defBF525.h
new file mode 100644
index 000000000000..6a375a084acc
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF525.h
@@ -0,0 +1,713 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF525.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF525_H
32#define _DEF_BF525_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include "defBF52x_base.h"
41
42/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
43
44/* USB Control Registers */
45
46#define USB_FADDR 0xffc03800 /* Function address register */
47#define USB_POWER 0xffc03804 /* Power management register */
48#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
49#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
50#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
51#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
52#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
53#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
54#define USB_FRAME 0xffc03820 /* USB frame number */
55#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
56#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
57#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
58#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
59
60/* USB Packet Control Registers */
61
62#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
63#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
64#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
65#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
66#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
67#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
68#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
69#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
70#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
71#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
72#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
73#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
74#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
75
76/* USB Endpoint FIFO Registers */
77
78#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
79#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
80#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
81#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
82#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
83#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
84#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
85#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
86
87/* USB OTG Control Registers */
88
89#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
90#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
91#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
92
93/* USB Phy Control Registers */
94
95#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
96#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
97#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
98#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
99#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
100
101/* (APHY_CNTRL is for ADI usage only) */
102
103#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
104
105/* (APHY_CALIB is for ADI usage only) */
106
107#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
108
109#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
110
111/* (PHY_TEST is for ADI usage only) */
112
113#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
114
115#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
116#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
117
118/* USB Endpoint 0 Control Registers */
119
120#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
121#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
122#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
123#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
124#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
125#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
126#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
127#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
128#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
129#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
130
131/* USB Endpoint 1 Control Registers */
132
133#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
134#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
135#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
136#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
137#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
138#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
139#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
140#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
141#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
142#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
143
144/* USB Endpoint 2 Control Registers */
145
146#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
147#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
148#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
149#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
150#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
151#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
152#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
153#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
154#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
155#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
156
157/* USB Endpoint 3 Control Registers */
158
159#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
160#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
161#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
162#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
163#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
164#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
165#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
166#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
167#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
168#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
169
170/* USB Endpoint 4 Control Registers */
171
172#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
173#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
174#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
175#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
176#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
177#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
178#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
179#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
180#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
181#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
182
183/* USB Endpoint 5 Control Registers */
184
185#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
186#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
187#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
188#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
189#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
190#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
191#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
192#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
193#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
194#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
195
196/* USB Endpoint 6 Control Registers */
197
198#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
199#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
200#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
201#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
202#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
203#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
204#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
205#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
206#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
207#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
208
209/* USB Endpoint 7 Control Registers */
210
211#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
212#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
213#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
214#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
215#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
216#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
217#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
218#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
219#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
220#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
221
222#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
223
224/* USB Channel 0 Config Registers */
225
226#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
227#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
228#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
229#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
230#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
231
232/* USB Channel 1 Config Registers */
233
234#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
235#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
236#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
237#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
238#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
239
240/* USB Channel 2 Config Registers */
241
242#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
243#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
244#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
245#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
246#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
247
248/* USB Channel 3 Config Registers */
249
250#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
251#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
252#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
253#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
254#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
255
256/* USB Channel 4 Config Registers */
257
258#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
259#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
260#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
261#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
262#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
263
264/* USB Channel 5 Config Registers */
265
266#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
267#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
268#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
269#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
270#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
271
272/* USB Channel 6 Config Registers */
273
274#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
275#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
276#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
277#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
278#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
279
280/* USB Channel 7 Config Registers */
281
282#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
283#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
284#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
285#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
286#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
287
288/* Bit masks for USB_FADDR */
289
290#define FUNCTION_ADDRESS 0x7f /* Function address */
291
292/* Bit masks for USB_POWER */
293
294#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
295#define nENABLE_SUSPENDM 0x0
296#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
297#define nSUSPEND_MODE 0x0
298#define RESUME_MODE 0x4 /* DMA Mode */
299#define nRESUME_MODE 0x0
300#define RESET 0x8 /* Reset indicator */
301#define nRESET 0x0
302#define HS_MODE 0x10 /* High Speed mode indicator */
303#define nHS_MODE 0x0
304#define HS_ENABLE 0x20 /* high Speed Enable */
305#define nHS_ENABLE 0x0
306#define SOFT_CONN 0x40 /* Soft connect */
307#define nSOFT_CONN 0x0
308#define ISO_UPDATE 0x80 /* Isochronous update */
309#define nISO_UPDATE 0x0
310
311/* Bit masks for USB_INTRTX */
312
313#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
314#define nEP0_TX 0x0
315#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
316#define nEP1_TX 0x0
317#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
318#define nEP2_TX 0x0
319#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
320#define nEP3_TX 0x0
321#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
322#define nEP4_TX 0x0
323#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
324#define nEP5_TX 0x0
325#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
326#define nEP6_TX 0x0
327#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
328#define nEP7_TX 0x0
329
330/* Bit masks for USB_INTRRX */
331
332#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
333#define nEP1_RX 0x0
334#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
335#define nEP2_RX 0x0
336#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
337#define nEP3_RX 0x0
338#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
339#define nEP4_RX 0x0
340#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
341#define nEP5_RX 0x0
342#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
343#define nEP6_RX 0x0
344#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
345#define nEP7_RX 0x0
346
347/* Bit masks for USB_INTRTXE */
348
349#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
350#define nEP0_TX_E 0x0
351#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
352#define nEP1_TX_E 0x0
353#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
354#define nEP2_TX_E 0x0
355#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
356#define nEP3_TX_E 0x0
357#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
358#define nEP4_TX_E 0x0
359#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
360#define nEP5_TX_E 0x0
361#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
362#define nEP6_TX_E 0x0
363#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
364#define nEP7_TX_E 0x0
365
366/* Bit masks for USB_INTRRXE */
367
368#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
369#define nEP1_RX_E 0x0
370#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
371#define nEP2_RX_E 0x0
372#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
373#define nEP3_RX_E 0x0
374#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
375#define nEP4_RX_E 0x0
376#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
377#define nEP5_RX_E 0x0
378#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
379#define nEP6_RX_E 0x0
380#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
381#define nEP7_RX_E 0x0
382
383/* Bit masks for USB_INTRUSB */
384
385#define SUSPEND_B 0x1 /* Suspend indicator */
386#define nSUSPEND_B 0x0
387#define RESUME_B 0x2 /* Resume indicator */
388#define nRESUME_B 0x0
389#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
390#define nRESET_OR_BABLE_B 0x0
391#define SOF_B 0x8 /* Start of frame */
392#define nSOF_B 0x0
393#define CONN_B 0x10 /* Connection indicator */
394#define nCONN_B 0x0
395#define DISCON_B 0x20 /* Disconnect indicator */
396#define nDISCON_B 0x0
397#define SESSION_REQ_B 0x40 /* Session Request */
398#define nSESSION_REQ_B 0x0
399#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
400#define nVBUS_ERROR_B 0x0
401
402/* Bit masks for USB_INTRUSBE */
403
404#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
405#define nSUSPEND_BE 0x0
406#define RESUME_BE 0x2 /* Resume indicator int enable */
407#define nRESUME_BE 0x0
408#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
409#define nRESET_OR_BABLE_BE 0x0
410#define SOF_BE 0x8 /* Start of frame int enable */
411#define nSOF_BE 0x0
412#define CONN_BE 0x10 /* Connection indicator int enable */
413#define nCONN_BE 0x0
414#define DISCON_BE 0x20 /* Disconnect indicator int enable */
415#define nDISCON_BE 0x0
416#define SESSION_REQ_BE 0x40 /* Session Request int enable */
417#define nSESSION_REQ_BE 0x0
418#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
419#define nVBUS_ERROR_BE 0x0
420
421/* Bit masks for USB_FRAME */
422
423#define FRAME_NUMBER 0x7ff /* Frame number */
424
425/* Bit masks for USB_INDEX */
426
427#define SELECTED_ENDPOINT 0xf /* selected endpoint */
428
429/* Bit masks for USB_GLOBAL_CTL */
430
431#define GLOBAL_ENA 0x1 /* enables USB module */
432#define nGLOBAL_ENA 0x0
433#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
434#define nEP1_TX_ENA 0x0
435#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
436#define nEP2_TX_ENA 0x0
437#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
438#define nEP3_TX_ENA 0x0
439#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
440#define nEP4_TX_ENA 0x0
441#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
442#define nEP5_TX_ENA 0x0
443#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
444#define nEP6_TX_ENA 0x0
445#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
446#define nEP7_TX_ENA 0x0
447#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
448#define nEP1_RX_ENA 0x0
449#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
450#define nEP2_RX_ENA 0x0
451#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
452#define nEP3_RX_ENA 0x0
453#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
454#define nEP4_RX_ENA 0x0
455#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
456#define nEP5_RX_ENA 0x0
457#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
458#define nEP6_RX_ENA 0x0
459#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
460#define nEP7_RX_ENA 0x0
461
462/* Bit masks for USB_OTG_DEV_CTL */
463
464#define SESSION 0x1 /* session indicator */
465#define nSESSION 0x0
466#define HOST_REQ 0x2 /* Host negotiation request */
467#define nHOST_REQ 0x0
468#define HOST_MODE 0x4 /* indicates USBDRC is a host */
469#define nHOST_MODE 0x0
470#define VBUS0 0x8 /* Vbus level indicator[0] */
471#define nVBUS0 0x0
472#define VBUS1 0x10 /* Vbus level indicator[1] */
473#define nVBUS1 0x0
474#define LSDEV 0x20 /* Low-speed indicator */
475#define nLSDEV 0x0
476#define FSDEV 0x40 /* Full or High-speed indicator */
477#define nFSDEV 0x0
478#define B_DEVICE 0x80 /* A' or 'B' device indicator */
479#define nB_DEVICE 0x0
480
481/* Bit masks for USB_OTG_VBUS_IRQ */
482
483#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
484#define nDRIVE_VBUS_ON 0x0
485#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
486#define nDRIVE_VBUS_OFF 0x0
487#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
488#define nCHRG_VBUS_START 0x0
489#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
490#define nCHRG_VBUS_END 0x0
491#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
492#define nDISCHRG_VBUS_START 0x0
493#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
494#define nDISCHRG_VBUS_END 0x0
495
496/* Bit masks for USB_OTG_VBUS_MASK */
497
498#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
499#define nDRIVE_VBUS_ON_ENA 0x0
500#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
501#define nDRIVE_VBUS_OFF_ENA 0x0
502#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
503#define nCHRG_VBUS_START_ENA 0x0
504#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
505#define nCHRG_VBUS_END_ENA 0x0
506#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
507#define nDISCHRG_VBUS_START_ENA 0x0
508#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
509#define nDISCHRG_VBUS_END_ENA 0x0
510
511/* Bit masks for USB_CSR0 */
512
513#define RXPKTRDY 0x1 /* data packet receive indicator */
514#define nRXPKTRDY 0x0
515#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
516#define nTXPKTRDY 0x0
517#define STALL_SENT 0x4 /* STALL handshake sent */
518#define nSTALL_SENT 0x0
519#define DATAEND 0x8 /* Data end indicator */
520#define nDATAEND 0x0
521#define SETUPEND 0x10 /* Setup end */
522#define nSETUPEND 0x0
523#define SENDSTALL 0x20 /* Send STALL handshake */
524#define nSENDSTALL 0x0
525#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
526#define nSERVICED_RXPKTRDY 0x0
527#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
528#define nSERVICED_SETUPEND 0x0
529#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
530#define nFLUSHFIFO 0x0
531#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
532#define nSTALL_RECEIVED_H 0x0
533#define SETUPPKT_H 0x8 /* send Setup token host mode */
534#define nSETUPPKT_H 0x0
535#define ERROR_H 0x10 /* timeout error indicator host mode */
536#define nERROR_H 0x0
537#define REQPKT_H 0x20 /* Request an IN transaction host mode */
538#define nREQPKT_H 0x0
539#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
540#define nSTATUSPKT_H 0x0
541#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
542#define nNAK_TIMEOUT_H 0x0
543
544/* Bit masks for USB_COUNT0 */
545
546#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
547
548/* Bit masks for USB_NAKLIMIT0 */
549
550#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
551
552/* Bit masks for USB_TX_MAX_PACKET */
553
554#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
555
556/* Bit masks for USB_RX_MAX_PACKET */
557
558#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
559
560/* Bit masks for USB_TXCSR */
561
562#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
563#define nTXPKTRDY_T 0x0
564#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
565#define nFIFO_NOT_EMPTY_T 0x0
566#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
567#define nUNDERRUN_T 0x0
568#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
569#define nFLUSHFIFO_T 0x0
570#define STALL_SEND_T 0x10 /* issue a Stall handshake */
571#define nSTALL_SEND_T 0x0
572#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
573#define nSTALL_SENT_T 0x0
574#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
575#define nCLEAR_DATATOGGLE_T 0x0
576#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
577#define nINCOMPTX_T 0x0
578#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
579#define nDMAREQMODE_T 0x0
580#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
581#define nFORCE_DATATOGGLE_T 0x0
582#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
583#define nDMAREQ_ENA_T 0x0
584#define ISO_T 0x4000 /* enable Isochronous transfers */
585#define nISO_T 0x0
586#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
587#define nAUTOSET_T 0x0
588#define ERROR_TH 0x4 /* error condition host mode */
589#define nERROR_TH 0x0
590#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
591#define nSTALL_RECEIVED_TH 0x0
592#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
593#define nNAK_TIMEOUT_TH 0x0
594
595/* Bit masks for USB_TXCOUNT */
596
597#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
598
599/* Bit masks for USB_RXCSR */
600
601#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
602#define nRXPKTRDY_R 0x0
603#define FIFO_FULL_R 0x2 /* FIFO not empty */
604#define nFIFO_FULL_R 0x0
605#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
606#define nOVERRUN_R 0x0
607#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
608#define nDATAERROR_R 0x0
609#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
610#define nFLUSHFIFO_R 0x0
611#define STALL_SEND_R 0x20 /* issue a Stall handshake */
612#define nSTALL_SEND_R 0x0
613#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
614#define nSTALL_SENT_R 0x0
615#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
616#define nCLEAR_DATATOGGLE_R 0x0
617#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
618#define nINCOMPRX_R 0x0
619#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
620#define nDMAREQMODE_R 0x0
621#define DISNYET_R 0x1000 /* disable Nyet handshakes */
622#define nDISNYET_R 0x0
623#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
624#define nDMAREQ_ENA_R 0x0
625#define ISO_R 0x4000 /* enable Isochronous transfers */
626#define nISO_R 0x0
627#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
628#define nAUTOCLEAR_R 0x0
629#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
630#define nERROR_RH 0x0
631#define REQPKT_RH 0x20 /* request an IN transaction host mode */
632#define nREQPKT_RH 0x0
633#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
634#define nSTALL_RECEIVED_RH 0x0
635#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
636#define nINCOMPRX_RH 0x0
637#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
638#define nDMAREQMODE_RH 0x0
639#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
640#define nAUTOREQ_RH 0x0
641
642/* Bit masks for USB_RXCOUNT */
643
644#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
645
646/* Bit masks for USB_TXTYPE */
647
648#define TARGET_EP_NO_T 0xf /* EP number */
649#define PROTOCOL_T 0xc /* transfer type */
650
651/* Bit masks for USB_TXINTERVAL */
652
653#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
654
655/* Bit masks for USB_RXTYPE */
656
657#define TARGET_EP_NO_R 0xf /* EP number */
658#define PROTOCOL_R 0xc /* transfer type */
659
660/* Bit masks for USB_RXINTERVAL */
661
662#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
663
664/* Bit masks for USB_DMA_INTERRUPT */
665
666#define DMA0_INT 0x1 /* DMA0 pending interrupt */
667#define nDMA0_INT 0x0
668#define DMA1_INT 0x2 /* DMA1 pending interrupt */
669#define nDMA1_INT 0x0
670#define DMA2_INT 0x4 /* DMA2 pending interrupt */
671#define nDMA2_INT 0x0
672#define DMA3_INT 0x8 /* DMA3 pending interrupt */
673#define nDMA3_INT 0x0
674#define DMA4_INT 0x10 /* DMA4 pending interrupt */
675#define nDMA4_INT 0x0
676#define DMA5_INT 0x20 /* DMA5 pending interrupt */
677#define nDMA5_INT 0x0
678#define DMA6_INT 0x40 /* DMA6 pending interrupt */
679#define nDMA6_INT 0x0
680#define DMA7_INT 0x80 /* DMA7 pending interrupt */
681#define nDMA7_INT 0x0
682
683/* Bit masks for USB_DMAxCONTROL */
684
685#define DMA_ENA 0x1 /* DMA enable */
686#define nDMA_ENA 0x0
687#define DIRECTION 0x2 /* direction of DMA transfer */
688#define nDIRECTION 0x0
689#define MODE 0x4 /* DMA Bus error */
690#define nMODE 0x0
691#define INT_ENA 0x8 /* Interrupt enable */
692#define nINT_ENA 0x0
693#define EPNUM 0xf0 /* EP number */
694#define BUSERROR 0x100 /* DMA Bus error */
695#define nBUSERROR 0x0
696
697/* Bit masks for USB_DMAxADDRHIGH */
698
699#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
700
701/* Bit masks for USB_DMAxADDRLOW */
702
703#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
704
705/* Bit masks for USB_DMAxCOUNTHIGH */
706
707#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
708
709/* Bit masks for USB_DMAxCOUNTLOW */
710
711#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
712
713#endif /* _DEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h
new file mode 100644
index 000000000000..2be3293f9e26
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF527.h
@@ -0,0 +1,1089 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF527.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF527_H
32#define _DEF_BF527_H
33
34/* Include all Core registers and bit definitions */
35#include <def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include <defBF52x_base.h>
41
42/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
43/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
44
45#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
46#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
47#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
48#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
49#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
50#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
51#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
52#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
53#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
54#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
55#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
56#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
57#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
58#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
59#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
60#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
61#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
62#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
63#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
64
65#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
66#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
67#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
68#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
69#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
70#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
71#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
72#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
73
74#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
75#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
76#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
77#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
78#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
79
80#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
81#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
82#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
83#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
84#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
85#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
86#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
87#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
88#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
89#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
90#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
91#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
92#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
93#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
94#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
95#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
96#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
97#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
98#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
99#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
100#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
101#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
102#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
103#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
104
105#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
106#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
107#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
108#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
109#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
110#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
111#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
112#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
113#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
114#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
115#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
116#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
117#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
118#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
119#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
120#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
121#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
122#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
123#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
124#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
125#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
126#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
127#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
128
129/* Listing for IEEE-Supported Count Registers */
130
131#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
132#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
133#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
134#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
135#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
136#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
137#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
138#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
139#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
140#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
141#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
142#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
143#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
144#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
145#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
146#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
147#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
148#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
149#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
150#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
151#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
152#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
153#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
154#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
155
156#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
157#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
158#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
159#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
160#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
161#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
162#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
163#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
164#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
165#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
166#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
167#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
168#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
169#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
170#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
171#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
172#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
173#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
174#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
175#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
176#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
177#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
178#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
179
180/***********************************************************************************
181** System MMR Register Bits And Macros
182**
183** Disclaimer: All macros are intended to make C and Assembly code more readable.
184** Use these macros carefully, as any that do left shifts for field
185** depositing will result in the lower order bits being destroyed. Any
186** macro that shifts left to properly position the bit-field should be
187** used as part of an OR to initialize a register and NOT as a dynamic
188** modifier UNLESS the lower order bits are saved and ORed back in when
189** the macro is used.
190*************************************************************************************/
191
192/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
193
194/* EMAC_OPMODE Masks */
195
196#define RE 0x00000001 /* Receiver Enable */
197#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
198#define HU 0x00000010 /* Hash Filter Unicast Address */
199#define HM 0x00000020 /* Hash Filter Multicast Address */
200#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
201#define PR 0x00000080 /* Promiscuous Mode Enable */
202#define IFE 0x00000100 /* Inverse Filtering Enable */
203#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
204#define PBF 0x00000400 /* Pass Bad Frames Enable */
205#define PSF 0x00000800 /* Pass Short Frames Enable */
206#define RAF 0x00001000 /* Receive-All Mode */
207#define TE 0x00010000 /* Transmitter Enable */
208#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
209#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
210#define DC 0x00080000 /* Deferral Check */
211#define BOLMT 0x00300000 /* Back-Off Limit */
212#define BOLMT_10 0x00000000 /* 10-bit range */
213#define BOLMT_8 0x00100000 /* 8-bit range */
214#define BOLMT_4 0x00200000 /* 4-bit range */
215#define BOLMT_1 0x00300000 /* 1-bit range */
216#define DRTY 0x00400000 /* Disable TX Retry On Collision */
217#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
218#define RMII 0x01000000 /* RMII/MII* Mode */
219#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
220#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
221#define LB 0x08000000 /* Internal Loopback Enable */
222#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
223
224/* EMAC_STAADD Masks */
225
226#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
227#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
228#define STADISPRE 0x00000004 /* Disable Preamble Generation */
229#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
230#define REGAD 0x000007C0 /* STA Register Address */
231#define PHYAD 0x0000F800 /* PHY Device Address */
232
233#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
234#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
235
236/* EMAC_STADAT Mask */
237
238#define STADATA 0x0000FFFF /* Station Management Data */
239
240/* EMAC_FLC Masks */
241
242#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
243#define FLCE 0x00000002 /* Flow Control Enable */
244#define PCF 0x00000004 /* Pass Control Frames */
245#define BKPRSEN 0x00000008 /* Enable Backpressure */
246#define FLCPAUSE 0xFFFF0000 /* Pause Time */
247
248#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
249
250/* EMAC_WKUP_CTL Masks */
251
252#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
253#define MPKE 0x00000002 /* Magic Packet Enable */
254#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
255#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
256#define MPKS 0x00000020 /* Magic Packet Received Status */
257#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
258
259/* EMAC_WKUP_FFCMD Masks */
260
261#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
262#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
263#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
264#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
265#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
266#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
267#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
268#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
269
270/* EMAC_WKUP_FFOFF Masks */
271
272#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
273#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
274#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
275#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
276
277#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
278#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
279#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
280#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
281/* Set ALL Offsets */
282#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
283
284/* EMAC_WKUP_FFCRC0 Masks */
285
286#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
287#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
288
289#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
290#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
291
292/* EMAC_WKUP_FFCRC1 Masks */
293
294#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
295#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
296
297#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
298#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
299
300/* EMAC_SYSCTL Masks */
301
302#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
303#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
304#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
305#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
306
307#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
308
309/* EMAC_SYSTAT Masks */
310
311#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
312#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
313#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
314#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
315#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
316#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
317#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
318#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
319
320/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
321
322#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
323#define RX_COMP 0x00001000 /* RX Frame Complete */
324#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
325#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
326#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
327#define RX_CRC 0x00010000 /* RX Frame CRC Error */
328#define RX_LEN 0x00020000 /* RX Frame Length Error */
329#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
330#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
331#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
332#define RX_PHY 0x00200000 /* RX Frame PHY Error */
333#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
334#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
335#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
336#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
337#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
338#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
339#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
340#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
341#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
342#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
343
344/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
345
346#define TX_COMP 0x00000001 /* TX Frame Complete */
347#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
348#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
349#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
350#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
351#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
352#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
353#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
354#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
355#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
356#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
357#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
358#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
359#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
360#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
361
362/* EMAC_MMC_CTL Masks */
363#define RSTC 0x00000001 /* Reset All Counters */
364#define CROLL 0x00000002 /* Counter Roll-Over Enable */
365#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
366#define MMCE 0x00000008 /* Enable MMC Counter Operation */
367
368/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
369#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
370#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
371#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
372#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
373#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
374#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
375#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
376#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
377#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
378#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
379#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
380#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
381#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
382#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
383#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
384#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
385#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
386#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
387#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
388#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
389#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
390#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
391#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
392#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
393
394/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
395
396#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
397#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
398#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
399#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
400#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
401#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
402#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
403#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
404#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
405#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
406#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
407#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
408#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
409#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
410#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
411#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
412#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
413#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
414#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
415#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
416#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
417#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
418#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
419
420/* USB Control Registers */
421
422#define USB_FADDR 0xffc03800 /* Function address register */
423#define USB_POWER 0xffc03804 /* Power management register */
424#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
425#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
426#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
427#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
428#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
429#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
430#define USB_FRAME 0xffc03820 /* USB frame number */
431#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
432#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
433#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
434#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
435
436/* USB Packet Control Registers */
437
438#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
439#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
440#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
441#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
442#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
443#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
444#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
445#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
446#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
447#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
448#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
449#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
450#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
451
452/* USB Endpoint FIFO Registers */
453
454#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
455#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
456#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
457#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
458#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
459#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
460#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
461#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
462
463/* USB OTG Control Registers */
464
465#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
466#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
467#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
468
469/* USB Phy Control Registers */
470
471#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
472#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
473#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
474#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
475#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
476
477/* (APHY_CNTRL is for ADI usage only) */
478
479#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
480
481/* (APHY_CALIB is for ADI usage only) */
482
483#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
484
485#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
486
487/* (PHY_TEST is for ADI usage only) */
488
489#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
490
491#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
492#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
493
494/* USB Endpoint 0 Control Registers */
495
496#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
497#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
498#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
499#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
500#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
501#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
502#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
503#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
504#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
505#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
506
507/* USB Endpoint 1 Control Registers */
508
509#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
510#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
511#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
512#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
513#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
514#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
515#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
516#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
517#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
518#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
519
520/* USB Endpoint 2 Control Registers */
521
522#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
523#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
524#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
525#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
526#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
527#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
528#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
529#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
530#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
531#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
532
533/* USB Endpoint 3 Control Registers */
534
535#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
536#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
537#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
538#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
539#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
540#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
541#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
542#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
543#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
544#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
545
546/* USB Endpoint 4 Control Registers */
547
548#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
549#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
550#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
551#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
552#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
553#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
554#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
555#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
556#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
557#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
558
559/* USB Endpoint 5 Control Registers */
560
561#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
562#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
563#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
564#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
565#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
566#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
567#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
568#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
569#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
570#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
571
572/* USB Endpoint 6 Control Registers */
573
574#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
575#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
576#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
577#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
578#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
579#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
580#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
581#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
582#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
583#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
584
585/* USB Endpoint 7 Control Registers */
586
587#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
588#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
589#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
590#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
591#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
592#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
593#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
594#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
595#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
596#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
597
598#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
599
600/* USB Channel 0 Config Registers */
601
602#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
603#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
604#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
605#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
606#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
607
608/* USB Channel 1 Config Registers */
609
610#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
611#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
612#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
613#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
614#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
615
616/* USB Channel 2 Config Registers */
617
618#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
619#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
620#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
621#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
622#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
623
624/* USB Channel 3 Config Registers */
625
626#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
627#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
628#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
629#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
630#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
631
632/* USB Channel 4 Config Registers */
633
634#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
635#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
636#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
637#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
638#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
639
640/* USB Channel 5 Config Registers */
641
642#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
643#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
644#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
645#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
646#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
647
648/* USB Channel 6 Config Registers */
649
650#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
651#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
652#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
653#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
654#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
655
656/* USB Channel 7 Config Registers */
657
658#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
659#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
660#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
661#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
662#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
663
664/* Bit masks for USB_FADDR */
665
666#define FUNCTION_ADDRESS 0x7f /* Function address */
667
668/* Bit masks for USB_POWER */
669
670#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
671#define nENABLE_SUSPENDM 0x0
672#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
673#define nSUSPEND_MODE 0x0
674#define RESUME_MODE 0x4 /* DMA Mode */
675#define nRESUME_MODE 0x0
676#define RESET 0x8 /* Reset indicator */
677#define nRESET 0x0
678#define HS_MODE 0x10 /* High Speed mode indicator */
679#define nHS_MODE 0x0
680#define HS_ENABLE 0x20 /* high Speed Enable */
681#define nHS_ENABLE 0x0
682#define SOFT_CONN 0x40 /* Soft connect */
683#define nSOFT_CONN 0x0
684#define ISO_UPDATE 0x80 /* Isochronous update */
685#define nISO_UPDATE 0x0
686
687/* Bit masks for USB_INTRTX */
688
689#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
690#define nEP0_TX 0x0
691#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
692#define nEP1_TX 0x0
693#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
694#define nEP2_TX 0x0
695#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
696#define nEP3_TX 0x0
697#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
698#define nEP4_TX 0x0
699#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
700#define nEP5_TX 0x0
701#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
702#define nEP6_TX 0x0
703#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
704#define nEP7_TX 0x0
705
706/* Bit masks for USB_INTRRX */
707
708#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
709#define nEP1_RX 0x0
710#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
711#define nEP2_RX 0x0
712#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
713#define nEP3_RX 0x0
714#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
715#define nEP4_RX 0x0
716#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
717#define nEP5_RX 0x0
718#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
719#define nEP6_RX 0x0
720#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
721#define nEP7_RX 0x0
722
723/* Bit masks for USB_INTRTXE */
724
725#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
726#define nEP0_TX_E 0x0
727#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
728#define nEP1_TX_E 0x0
729#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
730#define nEP2_TX_E 0x0
731#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
732#define nEP3_TX_E 0x0
733#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
734#define nEP4_TX_E 0x0
735#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
736#define nEP5_TX_E 0x0
737#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
738#define nEP6_TX_E 0x0
739#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
740#define nEP7_TX_E 0x0
741
742/* Bit masks for USB_INTRRXE */
743
744#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
745#define nEP1_RX_E 0x0
746#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
747#define nEP2_RX_E 0x0
748#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
749#define nEP3_RX_E 0x0
750#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
751#define nEP4_RX_E 0x0
752#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
753#define nEP5_RX_E 0x0
754#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
755#define nEP6_RX_E 0x0
756#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
757#define nEP7_RX_E 0x0
758
759/* Bit masks for USB_INTRUSB */
760
761#define SUSPEND_B 0x1 /* Suspend indicator */
762#define nSUSPEND_B 0x0
763#define RESUME_B 0x2 /* Resume indicator */
764#define nRESUME_B 0x0
765#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
766#define nRESET_OR_BABLE_B 0x0
767#define SOF_B 0x8 /* Start of frame */
768#define nSOF_B 0x0
769#define CONN_B 0x10 /* Connection indicator */
770#define nCONN_B 0x0
771#define DISCON_B 0x20 /* Disconnect indicator */
772#define nDISCON_B 0x0
773#define SESSION_REQ_B 0x40 /* Session Request */
774#define nSESSION_REQ_B 0x0
775#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
776#define nVBUS_ERROR_B 0x0
777
778/* Bit masks for USB_INTRUSBE */
779
780#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
781#define nSUSPEND_BE 0x0
782#define RESUME_BE 0x2 /* Resume indicator int enable */
783#define nRESUME_BE 0x0
784#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
785#define nRESET_OR_BABLE_BE 0x0
786#define SOF_BE 0x8 /* Start of frame int enable */
787#define nSOF_BE 0x0
788#define CONN_BE 0x10 /* Connection indicator int enable */
789#define nCONN_BE 0x0
790#define DISCON_BE 0x20 /* Disconnect indicator int enable */
791#define nDISCON_BE 0x0
792#define SESSION_REQ_BE 0x40 /* Session Request int enable */
793#define nSESSION_REQ_BE 0x0
794#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
795#define nVBUS_ERROR_BE 0x0
796
797/* Bit masks for USB_FRAME */
798
799#define FRAME_NUMBER 0x7ff /* Frame number */
800
801/* Bit masks for USB_INDEX */
802
803#define SELECTED_ENDPOINT 0xf /* selected endpoint */
804
805/* Bit masks for USB_GLOBAL_CTL */
806
807#define GLOBAL_ENA 0x1 /* enables USB module */
808#define nGLOBAL_ENA 0x0
809#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
810#define nEP1_TX_ENA 0x0
811#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
812#define nEP2_TX_ENA 0x0
813#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
814#define nEP3_TX_ENA 0x0
815#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
816#define nEP4_TX_ENA 0x0
817#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
818#define nEP5_TX_ENA 0x0
819#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
820#define nEP6_TX_ENA 0x0
821#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
822#define nEP7_TX_ENA 0x0
823#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
824#define nEP1_RX_ENA 0x0
825#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
826#define nEP2_RX_ENA 0x0
827#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
828#define nEP3_RX_ENA 0x0
829#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
830#define nEP4_RX_ENA 0x0
831#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
832#define nEP5_RX_ENA 0x0
833#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
834#define nEP6_RX_ENA 0x0
835#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
836#define nEP7_RX_ENA 0x0
837
838/* Bit masks for USB_OTG_DEV_CTL */
839
840#define SESSION 0x1 /* session indicator */
841#define nSESSION 0x0
842#define HOST_REQ 0x2 /* Host negotiation request */
843#define nHOST_REQ 0x0
844#define HOST_MODE 0x4 /* indicates USBDRC is a host */
845#define nHOST_MODE 0x0
846#define VBUS0 0x8 /* Vbus level indicator[0] */
847#define nVBUS0 0x0
848#define VBUS1 0x10 /* Vbus level indicator[1] */
849#define nVBUS1 0x0
850#define LSDEV 0x20 /* Low-speed indicator */
851#define nLSDEV 0x0
852#define FSDEV 0x40 /* Full or High-speed indicator */
853#define nFSDEV 0x0
854#define B_DEVICE 0x80 /* A' or 'B' device indicator */
855#define nB_DEVICE 0x0
856
857/* Bit masks for USB_OTG_VBUS_IRQ */
858
859#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
860#define nDRIVE_VBUS_ON 0x0
861#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
862#define nDRIVE_VBUS_OFF 0x0
863#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
864#define nCHRG_VBUS_START 0x0
865#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
866#define nCHRG_VBUS_END 0x0
867#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
868#define nDISCHRG_VBUS_START 0x0
869#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
870#define nDISCHRG_VBUS_END 0x0
871
872/* Bit masks for USB_OTG_VBUS_MASK */
873
874#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
875#define nDRIVE_VBUS_ON_ENA 0x0
876#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
877#define nDRIVE_VBUS_OFF_ENA 0x0
878#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
879#define nCHRG_VBUS_START_ENA 0x0
880#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
881#define nCHRG_VBUS_END_ENA 0x0
882#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
883#define nDISCHRG_VBUS_START_ENA 0x0
884#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
885#define nDISCHRG_VBUS_END_ENA 0x0
886
887/* Bit masks for USB_CSR0 */
888
889#define RXPKTRDY 0x1 /* data packet receive indicator */
890#define nRXPKTRDY 0x0
891#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
892#define nTXPKTRDY 0x0
893#define STALL_SENT 0x4 /* STALL handshake sent */
894#define nSTALL_SENT 0x0
895#define DATAEND 0x8 /* Data end indicator */
896#define nDATAEND 0x0
897#define SETUPEND 0x10 /* Setup end */
898#define nSETUPEND 0x0
899#define SENDSTALL 0x20 /* Send STALL handshake */
900#define nSENDSTALL 0x0
901#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
902#define nSERVICED_RXPKTRDY 0x0
903#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
904#define nSERVICED_SETUPEND 0x0
905#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
906#define nFLUSHFIFO 0x0
907#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
908#define nSTALL_RECEIVED_H 0x0
909#define SETUPPKT_H 0x8 /* send Setup token host mode */
910#define nSETUPPKT_H 0x0
911#define ERROR_H 0x10 /* timeout error indicator host mode */
912#define nERROR_H 0x0
913#define REQPKT_H 0x20 /* Request an IN transaction host mode */
914#define nREQPKT_H 0x0
915#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
916#define nSTATUSPKT_H 0x0
917#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
918#define nNAK_TIMEOUT_H 0x0
919
920/* Bit masks for USB_COUNT0 */
921
922#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
923
924/* Bit masks for USB_NAKLIMIT0 */
925
926#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
927
928/* Bit masks for USB_TX_MAX_PACKET */
929
930#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
931
932/* Bit masks for USB_RX_MAX_PACKET */
933
934#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
935
936/* Bit masks for USB_TXCSR */
937
938#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
939#define nTXPKTRDY_T 0x0
940#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
941#define nFIFO_NOT_EMPTY_T 0x0
942#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
943#define nUNDERRUN_T 0x0
944#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
945#define nFLUSHFIFO_T 0x0
946#define STALL_SEND_T 0x10 /* issue a Stall handshake */
947#define nSTALL_SEND_T 0x0
948#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
949#define nSTALL_SENT_T 0x0
950#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
951#define nCLEAR_DATATOGGLE_T 0x0
952#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
953#define nINCOMPTX_T 0x0
954#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
955#define nDMAREQMODE_T 0x0
956#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
957#define nFORCE_DATATOGGLE_T 0x0
958#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
959#define nDMAREQ_ENA_T 0x0
960#define ISO_T 0x4000 /* enable Isochronous transfers */
961#define nISO_T 0x0
962#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
963#define nAUTOSET_T 0x0
964#define ERROR_TH 0x4 /* error condition host mode */
965#define nERROR_TH 0x0
966#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
967#define nSTALL_RECEIVED_TH 0x0
968#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
969#define nNAK_TIMEOUT_TH 0x0
970
971/* Bit masks for USB_TXCOUNT */
972
973#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
974
975/* Bit masks for USB_RXCSR */
976
977#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
978#define nRXPKTRDY_R 0x0
979#define FIFO_FULL_R 0x2 /* FIFO not empty */
980#define nFIFO_FULL_R 0x0
981#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
982#define nOVERRUN_R 0x0
983#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
984#define nDATAERROR_R 0x0
985#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
986#define nFLUSHFIFO_R 0x0
987#define STALL_SEND_R 0x20 /* issue a Stall handshake */
988#define nSTALL_SEND_R 0x0
989#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
990#define nSTALL_SENT_R 0x0
991#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
992#define nCLEAR_DATATOGGLE_R 0x0
993#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
994#define nINCOMPRX_R 0x0
995#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
996#define nDMAREQMODE_R 0x0
997#define DISNYET_R 0x1000 /* disable Nyet handshakes */
998#define nDISNYET_R 0x0
999#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1000#define nDMAREQ_ENA_R 0x0
1001#define ISO_R 0x4000 /* enable Isochronous transfers */
1002#define nISO_R 0x0
1003#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1004#define nAUTOCLEAR_R 0x0
1005#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1006#define nERROR_RH 0x0
1007#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1008#define nREQPKT_RH 0x0
1009#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1010#define nSTALL_RECEIVED_RH 0x0
1011#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1012#define nINCOMPRX_RH 0x0
1013#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1014#define nDMAREQMODE_RH 0x0
1015#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1016#define nAUTOREQ_RH 0x0
1017
1018/* Bit masks for USB_RXCOUNT */
1019
1020#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1021
1022/* Bit masks for USB_TXTYPE */
1023
1024#define TARGET_EP_NO_T 0xf /* EP number */
1025#define PROTOCOL_T 0xc /* transfer type */
1026
1027/* Bit masks for USB_TXINTERVAL */
1028
1029#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1030
1031/* Bit masks for USB_RXTYPE */
1032
1033#define TARGET_EP_NO_R 0xf /* EP number */
1034#define PROTOCOL_R 0xc /* transfer type */
1035
1036/* Bit masks for USB_RXINTERVAL */
1037
1038#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1039
1040/* Bit masks for USB_DMA_INTERRUPT */
1041
1042#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1043#define nDMA0_INT 0x0
1044#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1045#define nDMA1_INT 0x0
1046#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1047#define nDMA2_INT 0x0
1048#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1049#define nDMA3_INT 0x0
1050#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1051#define nDMA4_INT 0x0
1052#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1053#define nDMA5_INT 0x0
1054#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1055#define nDMA6_INT 0x0
1056#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1057#define nDMA7_INT 0x0
1058
1059/* Bit masks for USB_DMAxCONTROL */
1060
1061#define DMA_ENA 0x1 /* DMA enable */
1062#define nDMA_ENA 0x0
1063#define DIRECTION 0x2 /* direction of DMA transfer */
1064#define nDIRECTION 0x0
1065#define MODE 0x4 /* DMA Bus error */
1066#define nMODE 0x0
1067#define INT_ENA 0x8 /* Interrupt enable */
1068#define nINT_ENA 0x0
1069#define EPNUM 0xf0 /* EP number */
1070#define BUSERROR 0x100 /* DMA Bus error */
1071#define nBUSERROR 0x0
1072
1073/* Bit masks for USB_DMAxADDRHIGH */
1074
1075#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1076
1077/* Bit masks for USB_DMAxADDRLOW */
1078
1079#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1080
1081/* Bit masks for USB_DMAxCOUNTHIGH */
1082
1083#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1084
1085/* Bit masks for USB_DMAxCOUNTLOW */
1086
1087#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1088
1089#endif /* _DEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
new file mode 100644
index 000000000000..0b2fb5036ed0
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h
@@ -0,0 +1,2009 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF52x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF52X_H
32#define _DEF_BF52X_H
33
34
35/* ************************************************************** */
36/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
37/* ************************************************************** */
38
39/* ==== begin from defBF534.h ==== */
40
41/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
42#define PLL_CTL 0xFFC00000 /* PLL Control Register */
43#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
44#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
45#define PLL_STAT 0xFFC0000C /* PLL Status Register */
46#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
47#define CHIPID 0xFFC00014 /* Device ID Register */
48
49
50/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
51#define SWRST 0xFFC00100 /* Software Reset Register */
52#define SYSCR 0xFFC00104 /* System Configuration Register */
53#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
54
55#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
56#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
57#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
58#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
59#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
60#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
61#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
62
63/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
64#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
65#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
66#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
67#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
68#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
69#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
70#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
71
72
73/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
74#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
75#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
76#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
77
78
79/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
80#define RTC_STAT 0xFFC00300 /* RTC Status Register */
81#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
82#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
83#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
84#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
85#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
86#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
87
88
89/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
90#define UART0_THR 0xFFC00400 /* Transmit Holding register */
91#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
92#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
93#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
94#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
95#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
96#define UART0_LCR 0xFFC0040C /* Line Control Register */
97#define UART0_MCR 0xFFC00410 /* Modem Control Register */
98#define UART0_LSR 0xFFC00414 /* Line Status Register */
99#define UART0_MSR 0xFFC00418 /* Modem Status Register */
100#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
101#define UART0_GCTL 0xFFC00424 /* Global Control Register */
102
103
104/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
105#define SPI_CTL 0xFFC00500 /* SPI Control Register */
106#define SPI_FLG 0xFFC00504 /* SPI Flag register */
107#define SPI_STAT 0xFFC00508 /* SPI Status register */
108#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
109#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
110#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
111#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
112
113
114/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
115#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
116#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
117#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
118#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
119
120#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
121#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
122#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
123#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
124
125#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
126#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
127#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
128#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
129
130#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
131#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
132#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
133#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
134
135#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
136#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
137#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
138#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
139
140#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
141#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
142#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
143#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
144
145#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
146#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
147#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
148#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
149
150#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
151#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
152#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
153#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
154
155#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
156#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
157#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
158
159
160/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
161#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
162#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
163#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
164#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
165#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
166#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
167#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
168#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
169#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
170#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
171#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
172#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
173#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
174#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
175#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
176#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
177#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
178
179
180/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
181#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
182#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
183#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
184#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
185#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
186#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
187#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
188#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
189#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
190#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
191#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
192#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
193#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
194#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
195#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
196#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
197#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
198#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
199#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
200#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
201#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
202#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
203
204
205/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
206#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
207#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
208#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
209#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
210#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
211#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
212#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
213#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
214#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
215#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
216#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
217#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
218#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
219#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
220#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
221#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
222#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
223#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
224#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
225#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
226#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
227#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
228
229
230/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
231#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
232#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
233#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
234#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
235#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
236#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
237#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
238
239
240/* DMA Traffic Control Registers */
241#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
242#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
243
244/* Alternate deprecated register names (below) provided for backwards code compatibility */
245#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
246#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
247
248/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
249#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
250#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
251#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
252#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
253#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
254#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
255#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
256#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
257#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
258#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
259#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
260#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
261#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
262
263#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
264#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
265#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
266#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
267#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
268#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
269#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
270#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
271#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
272#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
273#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
274#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
275#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
276
277#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
278#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
279#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
280#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
281#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
282#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
283#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
284#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
285#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
286#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
287#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
288#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
289#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
290
291#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
292#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
293#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
294#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
295#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
296#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
297#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
298#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
299#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
300#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
301#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
302#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
303#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
304
305#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
306#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
307#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
308#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
309#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
310#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
311#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
312#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
313#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
314#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
315#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
316#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
317#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
318
319#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
320#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
321#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
322#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
323#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
324#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
325#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
326#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
327#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
328#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
329#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
330#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
331#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
332
333#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
334#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
335#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
336#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
337#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
338#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
339#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
340#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
341#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
342#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
343#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
344#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
345#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
346
347#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
348#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
349#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
350#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
351#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
352#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
353#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
354#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
355#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
356#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
357#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
358#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
359#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
360
361#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
362#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
363#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
364#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
365#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
366#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
367#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
368#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
369#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
370#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
371#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
372#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
373#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
374
375#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
376#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
377#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
378#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
379#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
380#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
381#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
382#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
383#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
384#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
385#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
386#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
387#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
388
389#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
390#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
391#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
392#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
393#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
394#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
395#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
396#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
397#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
398#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
399#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
400#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
401#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
402
403#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
404#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
405#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
406#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
407#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
408#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
409#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
410#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
411#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
412#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
413#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
414#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
415#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
416
417#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
418#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
419#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
420#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
421#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
422#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
423#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
424#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
425#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
426#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
427#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
428#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
429#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
430
431#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
432#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
433#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
434#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
435#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
436#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
437#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
438#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
439#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
440#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
441#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
442#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
443#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
444
445#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
446#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
447#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
448#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
449#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
450#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
451#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
452#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
453#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
454#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
455#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
456#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
457#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
458
459#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
460#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
461#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
462#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
463#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
464#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
465#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
466#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
467#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
468#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
469#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
470#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
471#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
472
473
474/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
475#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
476#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
477#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
478#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
479#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
480
481
482/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
483#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
484#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
485#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
486#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
487#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
488#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
489#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
490#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
491#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
492#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
493#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
494#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
495#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
496#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
497#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
498#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
499
500
501/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
502#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
503#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
504#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
505#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
506#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
507#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
508#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
509#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
510#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
511#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
512#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
513#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
514#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
515#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
516#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
517#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
518#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
519
520
521/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
522#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
523#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
524#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
525#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
526#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
527#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
528#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
529#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
530#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
531#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
532#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
533#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
534#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
535#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
536#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
537#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
538#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
539
540
541/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
542#define UART1_THR 0xFFC02000 /* Transmit Holding register */
543#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
544#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
545#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
546#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
547#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
548#define UART1_LCR 0xFFC0200C /* Line Control Register */
549#define UART1_MCR 0xFFC02010 /* Modem Control Register */
550#define UART1_LSR 0xFFC02014 /* Line Status Register */
551#define UART1_MSR 0xFFC02018 /* Modem Status Register */
552#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
553#define UART1_GCTL 0xFFC02024 /* Global Control Register */
554
555
556/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
557
558/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
559#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
560#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
561#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
562#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
563
564
565/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
566#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
567#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
568#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
569#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
570#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
571#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
572#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
573
574#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
575#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
576#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
577#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
578#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
579#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
580#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
581
582/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
583#define PORTF_MUX 0xFFC03210 /* Port F mux control */
584#define PORTG_MUX 0xFFC03214 /* Port G mux control */
585#define PORTH_MUX 0xFFC03218 /* Port H mux control */
586#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
587#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
588#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
589#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
590#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
591#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
592#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
593#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
594#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
595#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
596#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
597#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
598
599
600/***********************************************************************************
601** System MMR Register Bits And Macros
602**
603** Disclaimer: All macros are intended to make C and Assembly code more readable.
604** Use these macros carefully, as any that do left shifts for field
605** depositing will result in the lower order bits being destroyed. Any
606** macro that shifts left to properly position the bit-field should be
607** used as part of an OR to initialize a register and NOT as a dynamic
608** modifier UNLESS the lower order bits are saved and ORed back in when
609** the macro is used.
610*************************************************************************************/
611/*
612** ********************* PLL AND RESET MASKS ****************************************/
613/* PLL_CTL Masks */
614#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
615#define PLL_OFF 0x0002 /* PLL Not Powered */
616#define STOPCK 0x0008 /* Core Clock Off */
617#define PDWN 0x0020 /* Enter Deep Sleep Mode */
618#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
619#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
620#define BYPASS 0x0100 /* Bypass the PLL */
621#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
622/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
623#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
624
625/* PLL_DIV Masks */
626#define SSEL 0x000F /* System Select */
627#define CSEL 0x0030 /* Core Select */
628#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
629#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
630#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
631#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
632/* PLL_DIV Macros */
633#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
634
635/* VR_CTL Masks */
636#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
637#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
638#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
639#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
640#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
641
642#define GAIN 0x000C /* Voltage Level Gain */
643#define GAIN_5 0x0000 /* GAIN = 5 */
644#define GAIN_10 0x0004 /* GAIN = 10 */
645#define GAIN_20 0x0008 /* GAIN = 20 */
646#define GAIN_50 0x000C /* GAIN = 50 */
647
648#define VLEV 0x00F0 /* Internal Voltage Level */
649#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
650#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
651#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
652#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
653#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
654#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
655#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
656#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
657#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
658#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
659
660#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
661#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
662#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
663#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
664#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
665#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
666
667/* PLL_STAT Masks */
668#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
669#define FULL_ON 0x0002 /* Processor In Full On Mode */
670#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
671#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
672
673/* CHIPID Masks */
674#define CHIPID_VERSION 0xF0000000
675#define CHIPID_FAMILY 0x0FFFF000
676#define CHIPID_MANUFACTURE 0x00000FFE
677
678/* SWRST Masks */
679#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
680#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
681#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
682#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
683#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
684
685/* SYSCR Masks */
686#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
687#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
688
689
690/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
691/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
692#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
693
694#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
695#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
696#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
697#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
698#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
699#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
700#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
701
702#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
703#define IRQ_TWI 0x00000200 /* TWI Interrupt */
704#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
705#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
706#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
707#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
708#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
709#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
710
711#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
712#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
713#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
714#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
715#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
716#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
717#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
718#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
719#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
720#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
721
722#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
723#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
724#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
725#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
726#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
727#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
728#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
729#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
730#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
731#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
732#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
733
734/* SIC_IAR0 Macros */
735#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
736#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
737#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
738#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
739#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
740#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
741#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
742#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
743
744/* SIC_IAR1 Macros */
745#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
746#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
747#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
748#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
749#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
750#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
751#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
752#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
753
754/* SIC_IAR2 Macros */
755#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
756#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
757#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
758#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
759#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
760#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
761#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
762#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
763
764/* SIC_IAR3 Macros */
765#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
766#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
767#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
768#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
769#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
770#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
771#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
772#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
773
774
775/* SIC_IMASK Masks */
776#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
777#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
778#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
779#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
780
781/* SIC_IWR Masks */
782#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
783#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
784#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
785#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
786
787
788/* ********* WATCHDOG TIMER MASKS ******************** */
789
790/* Watchdog Timer WDOG_CTL Register Masks */
791
792#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
793#define WDEV_RESET 0x0000 /* generate reset event on roll over */
794#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
795#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
796#define WDEV_NONE 0x0006 /* no event on roll over */
797#define WDEN 0x0FF0 /* enable watchdog */
798#define WDDIS 0x0AD0 /* disable watchdog */
799#define WDRO 0x8000 /* watchdog rolled over latch */
800
801/* depreciated WDOG_CTL Register Masks for legacy code */
802
803
804#define ICTL WDEV
805#define ENABLE_RESET WDEV_RESET
806#define WDOG_RESET WDEV_RESET
807#define ENABLE_NMI WDEV_NMI
808#define WDOG_NMI WDEV_NMI
809#define ENABLE_GPI WDEV_GPI
810#define WDOG_GPI WDEV_GPI
811#define DISABLE_EVT WDEV_NONE
812#define WDOG_NONE WDEV_NONE
813
814#define TMR_EN WDEN
815#define TMR_DIS WDDIS
816#define TRO WDRO
817#define ICTL_P0 0x01
818 #define ICTL_P1 0x02
819#define TRO_P 0x0F
820
821
822
823/* *************** REAL TIME CLOCK MASKS **************************/
824/* RTC_STAT and RTC_ALARM Masks */
825#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
826#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
827#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
828#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
829
830/* RTC_ALARM Macro z=day y=hr x=min w=sec */
831#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
832
833/* RTC_ICTL and RTC_ISTAT Masks */
834#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
835#define ALARM 0x0002 /* Alarm Interrupt Enable */
836#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
837#define MINUTE 0x0008 /* Minutes Interrupt Enable */
838#define HOUR 0x0010 /* Hours Interrupt Enable */
839#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
840#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
841#define WRITE_PENDING 0x4000 /* Write Pending Status */
842#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
843
844/* RTC_FAST / RTC_PREN Mask */
845#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
846
847
848/* ************** UART CONTROLLER MASKS *************************/
849/* UARTx_LCR Masks */
850#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
851#define STB 0x04 /* Stop Bits */
852#define PEN 0x08 /* Parity Enable */
853#define EPS 0x10 /* Even Parity Select */
854#define STP 0x20 /* Stick Parity */
855#define SB 0x40 /* Set Break */
856#define DLAB 0x80 /* Divisor Latch Access */
857
858/* UARTx_MCR Mask */
859#define LOOP_ENA 0x10 /* Loopback Mode Enable */
860#define LOOP_ENA_P 0x04
861
862/* UARTx_LSR Masks */
863#define DR 0x01 /* Data Ready */
864#define OE 0x02 /* Overrun Error */
865#define PE 0x04 /* Parity Error */
866#define FE 0x08 /* Framing Error */
867#define BI 0x10 /* Break Interrupt */
868#define THRE 0x20 /* THR Empty */
869#define TEMT 0x40 /* TSR and UART_THR Empty */
870
871/* UARTx_IER Masks */
872#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
873#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
874#define ELSI 0x04 /* Enable RX Status Interrupt */
875
876/* UARTx_IIR Masks */
877#define NINT 0x01 /* Pending Interrupt */
878#define IIR_TX_READY 0x02 /* UART_THR empty */
879#define IIR_RX_READY 0x04 /* Receive data ready */
880#define IIR_LINE_CHANGE 0x06 /* Receive line status */
881#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
882
883/* UARTx_GCTL Masks */
884#define UCEN 0x01 /* Enable UARTx Clocks */
885#define IREN 0x02 /* Enable IrDA Mode */
886#define TPOLC 0x04 /* IrDA TX Polarity Change */
887#define RPOLC 0x08 /* IrDA RX Polarity Change */
888#define FPE 0x10 /* Force Parity Error On Transmit */
889#define FFE 0x20 /* Force Framing Error On Transmit */
890
891
892/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
893/* SPI_CTL Masks */
894#define TIMOD 0x0003 /* Transfer Initiate Mode */
895#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
896#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
897#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
898#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
899#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
900#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
901#define PSSE 0x0010 /* Slave-Select Input Enable */
902#define EMISO 0x0020 /* Enable MISO As Output */
903#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
904#define LSBF 0x0200 /* LSB First */
905#define CPHA 0x0400 /* Clock Phase */
906#define CPOL 0x0800 /* Clock Polarity */
907#define MSTR 0x1000 /* Master/Slave* */
908#define WOM 0x2000 /* Write Open Drain Master */
909#define SPE 0x4000 /* SPI Enable */
910
911/* SPI_FLG Masks */
912#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
913#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
914#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
915#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
916#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
917#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
918#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
919#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
920#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
921#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
922#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
923#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
924#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
925#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
926
927/* SPI_STAT Masks */
928#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
929#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
930#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
931#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
932#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
933#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
934#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
935
936
937/* **************** GENERAL PURPOSE TIMER MASKS **********************/
938/* TIMER_ENABLE Masks */
939#define TIMEN0 0x0001 /* Enable Timer 0 */
940#define TIMEN1 0x0002 /* Enable Timer 1 */
941#define TIMEN2 0x0004 /* Enable Timer 2 */
942#define TIMEN3 0x0008 /* Enable Timer 3 */
943#define TIMEN4 0x0010 /* Enable Timer 4 */
944#define TIMEN5 0x0020 /* Enable Timer 5 */
945#define TIMEN6 0x0040 /* Enable Timer 6 */
946#define TIMEN7 0x0080 /* Enable Timer 7 */
947
948/* TIMER_DISABLE Masks */
949#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
950#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
951#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
952#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
953#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
954#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
955#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
956#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
957
958/* TIMER_STATUS Masks */
959#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
960#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
961#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
962#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
963#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
964#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
965#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
966#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
967#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
968#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
969#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
970#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
971#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
972#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
973#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
974#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
975#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
976#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
977#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
978#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
979#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
980#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
981#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
982#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
983
984/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
985#define TOVL_ERR0 TOVF_ERR0
986#define TOVL_ERR1 TOVF_ERR1
987#define TOVL_ERR2 TOVF_ERR2
988#define TOVL_ERR3 TOVF_ERR3
989#define TOVL_ERR4 TOVF_ERR4
990#define TOVL_ERR5 TOVF_ERR5
991#define TOVL_ERR6 TOVF_ERR6
992#define TOVL_ERR7 TOVF_ERR7
993
994/* TIMERx_CONFIG Masks */
995#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
996#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
997#define EXT_CLK 0x0003 /* External Clock Mode */
998#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
999#define PERIOD_CNT 0x0008 /* Period Count */
1000#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
1001#define TIN_SEL 0x0020 /* Timer Input Select */
1002#define OUT_DIS 0x0040 /* Output Pad Disable */
1003#define CLK_SEL 0x0080 /* Timer Clock Select */
1004#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1005#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1006#define ERR_TYP 0xC000 /* Error Type */
1007
1008
1009/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1010/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1011/* Port F Masks */
1012#define PF0 0x0001
1013#define PF1 0x0002
1014#define PF2 0x0004
1015#define PF3 0x0008
1016#define PF4 0x0010
1017#define PF5 0x0020
1018#define PF6 0x0040
1019#define PF7 0x0080
1020#define PF8 0x0100
1021#define PF9 0x0200
1022#define PF10 0x0400
1023#define PF11 0x0800
1024#define PF12 0x1000
1025#define PF13 0x2000
1026#define PF14 0x4000
1027#define PF15 0x8000
1028
1029/* Port G Masks */
1030#define PG0 0x0001
1031#define PG1 0x0002
1032#define PG2 0x0004
1033#define PG3 0x0008
1034#define PG4 0x0010
1035#define PG5 0x0020
1036#define PG6 0x0040
1037#define PG7 0x0080
1038#define PG8 0x0100
1039#define PG9 0x0200
1040#define PG10 0x0400
1041#define PG11 0x0800
1042#define PG12 0x1000
1043#define PG13 0x2000
1044#define PG14 0x4000
1045#define PG15 0x8000
1046
1047/* Port H Masks */
1048#define PH0 0x0001
1049#define PH1 0x0002
1050#define PH2 0x0004
1051#define PH3 0x0008
1052#define PH4 0x0010
1053#define PH5 0x0020
1054#define PH6 0x0040
1055#define PH7 0x0080
1056#define PH8 0x0100
1057#define PH9 0x0200
1058#define PH10 0x0400
1059#define PH11 0x0800
1060#define PH12 0x1000
1061#define PH13 0x2000
1062#define PH14 0x4000
1063#define PH15 0x8000
1064
1065
1066/* ******************* SERIAL PORT MASKS **************************************/
1067/* SPORTx_TCR1 Masks */
1068#define TSPEN 0x0001 /* Transmit Enable */
1069#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1070#define DTYPE_NORM 0x0004 /* Data Format Normal */
1071#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1072#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1073#define TLSBIT 0x0010 /* Transmit Bit Order */
1074#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1075#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1076#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1077#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1078#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1079#define TCKFE 0x4000 /* Clock Falling Edge Select */
1080
1081/* SPORTx_TCR2 Masks and Macro */
1082#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1083#define TXSE 0x0100 /* TX Secondary Enable */
1084#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1085#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1086
1087/* SPORTx_RCR1 Masks */
1088#define RSPEN 0x0001 /* Receive Enable */
1089#define IRCLK 0x0002 /* Internal Receive Clock Select */
1090#define DTYPE_NORM 0x0004 /* Data Format Normal */
1091#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1092#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1093#define RLSBIT 0x0010 /* Receive Bit Order */
1094#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1095#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1096#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1097#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1098#define RCKFE 0x4000 /* Clock Falling Edge Select */
1099
1100/* SPORTx_RCR2 Masks */
1101#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1102#define RXSE 0x0100 /* RX Secondary Enable */
1103#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1104#define RRFST 0x0400 /* Right-First Data Order */
1105
1106/* SPORTx_STAT Masks */
1107#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1108#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1109#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1110#define TXF 0x0008 /* Transmit FIFO Full Status */
1111#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1112#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1113#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1114
1115/* SPORTx_MCMC1 Macros */
1116#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1117
1118/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1119#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1120
1121/* SPORTx_MCMC2 Masks */
1122#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1123#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1124#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1125#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1126#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1127#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1128#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1129#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1130#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1131#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1132#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1133#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1134#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1135#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1136#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1137#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1138#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1139#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1140#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1141#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1142#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1143#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1144#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1145
1146
1147/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1148/* EBIU_AMGCTL Masks */
1149#define AMCKEN 0x0001 /* Enable CLKOUT */
1150#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1151#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1152#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1153#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1154#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1155
1156/* EBIU_AMBCTL0 Masks */
1157#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1158#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1159#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1160#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1161#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1162#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1163#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1164#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1165#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1166#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1167#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1168#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1169#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1170#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1171#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1172#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1173#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1174#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1175#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1176#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1177#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1178#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1179#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1180#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1181#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1182#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1183#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1184#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1185#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1186#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1187#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1188#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1189#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1190#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1191#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1192#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1193#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1194#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1195#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1196#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1197#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1198#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1199#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1200#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1201
1202#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1203#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1204#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1205#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1206#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1207#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1208#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1209#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1210#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1211#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1212#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1213#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1214#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1215#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1216#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1217#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1218#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1219#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1220#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1221#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1222#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1223#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1224#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1225#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1226#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1227#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1228#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1229#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1230#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1231#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1232#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1233#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1234#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1235#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1236#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1237#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1238#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1239#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1240#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1241#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1242#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1243#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1244#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1245#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1246
1247/* EBIU_AMBCTL1 Masks */
1248#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1249#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1250#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1251#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1252#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1253#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1254#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1255#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1256#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1257#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1258#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1259#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1260#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1261#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1262#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1263#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1264#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1265#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1266#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1267#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1268#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1269#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1270#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1271#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1272#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1273#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1274#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1275#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1276#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1277#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1278#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1279#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1280#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1281#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1282#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1283#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1284#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1285#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1286#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1287#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1288#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1289#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1290#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1291#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1292
1293#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1294#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1295#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1296#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1297#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1298#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1299#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1300#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1301#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1302#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1303#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1304#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1305#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1306#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1307#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1308#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1309#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1310#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1311#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1312#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1313#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1314#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1315#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1316#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1317#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1318#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1319#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1320#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1321#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1322#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1323#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1324#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1325#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1326#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1327#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1328#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1329#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1330#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1331#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1332#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1333#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1334#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1335#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1336#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1337
1338
1339/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1340/* EBIU_SDGCTL Masks */
1341#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1342#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1343#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1344#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1345#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1346#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1347#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1348#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1349#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1350#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1351#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1352#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1353#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1354#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1355#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1356#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1357#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1358#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1359#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1360#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1361#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1362#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1363#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1364#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1365#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1366#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1367#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1368#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1369#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1370#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1371#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1372#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1373#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1374#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1375#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1376#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1377#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1378#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1379#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1380#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1381#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1382#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1383#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1384#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1385#define EMREN 0x10000000 /* Extended Mode Register Enable */
1386#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1387#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1388
1389/* EBIU_SDBCTL Masks */
1390#define EBE 0x0001 /* Enable SDRAM External Bank */
1391#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1392#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1393#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1394#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1395#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1396#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1397#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1398#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1399#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1400#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1401
1402/* EBIU_SDSTAT Masks */
1403#define SDCI 0x0001 /* SDRAM Controller Idle */
1404#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1405#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1406#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1407#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1408#define BGSTAT 0x0020 /* Bus Grant Status */
1409
1410
1411/* ************************** DMA CONTROLLER MASKS ********************************/
1412/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1413#define DMAEN 0x0001 /* DMA Channel Enable */
1414#define WNR 0x0002 /* Channel Direction (W/R*) */
1415#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1416#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1417#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1418#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1419#define RESTART 0x0020 /* DMA Buffer Clear */
1420#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1421#define DI_EN 0x0080 /* Data Interrupt Enable */
1422#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1423#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1424#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1425#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1426#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1427#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1428#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1429#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1430#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1431#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1432#define NDSIZE 0x0900 /* Next Descriptor Size */
1433#define DMAFLOW 0x7000 /* Flow Control */
1434#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1435#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1436#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1437#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1438#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1439
1440/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1441#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1442#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1443#define PMAP_PPI 0x0000 /* PPI Port DMA */
1444#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1445#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1446#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1447#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1448#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1449#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1450#define PMAP_SPI 0x7000 /* SPI Port DMA */
1451#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1452#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1453#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1454#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1455
1456/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1457#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1458#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1459#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1460#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1461
1462
1463/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1464/* PPI_CONTROL Masks */
1465#define PORT_EN 0x0001 /* PPI Port Enable */
1466#define PORT_DIR 0x0002 /* PPI Port Direction */
1467#define XFR_TYPE 0x000C /* PPI Transfer Type */
1468#define PORT_CFG 0x0030 /* PPI Port Configuration */
1469#define FLD_SEL 0x0040 /* PPI Active Field Select */
1470#define PACK_EN 0x0080 /* PPI Packing Mode */
1471#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1472#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1473#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1474#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1475#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1476#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1477#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1478#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1479#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1480#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1481#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1482#define DLENGTH 0x3800 /* PPI Data Length */
1483#define POLC 0x4000 /* PPI Clock Polarity */
1484#define POLS 0x8000 /* PPI Frame Sync Polarity */
1485
1486/* PPI_STATUS Masks */
1487#define FLD 0x0400 /* Field Indicator */
1488#define FT_ERR 0x0800 /* Frame Track Error */
1489#define OVR 0x1000 /* FIFO Overflow Error */
1490#define UNDR 0x2000 /* FIFO Underrun Error */
1491#define ERR_DET 0x4000 /* Error Detected Indicator */
1492#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1493
1494
1495/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1496/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1497#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1498#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1499
1500/* TWI_PRESCALE Masks */
1501#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1502#define TWI_ENA 0x0080 /* TWI Enable */
1503#define SCCB 0x0200 /* SCCB Compatibility Enable */
1504
1505/* TWI_SLAVE_CTRL Masks */
1506#define SEN 0x0001 /* Slave Enable */
1507#define SADD_LEN 0x0002 /* Slave Address Length */
1508#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1509#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1510#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1511
1512/* TWI_SLAVE_STAT Masks */
1513#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1514#define GCALL 0x0002 /* General Call Indicator */
1515
1516/* TWI_MASTER_CTRL Masks */
1517#define MEN 0x0001 /* Master Mode Enable */
1518#define MADD_LEN 0x0002 /* Master Address Length */
1519#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1520#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1521#define STOP 0x0010 /* Issue Stop Condition */
1522#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1523#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1524#define SDAOVR 0x4000 /* Serial Data Override */
1525#define SCLOVR 0x8000 /* Serial Clock Override */
1526
1527/* TWI_MASTER_STAT Masks */
1528#define MPROG 0x0001 /* Master Transfer In Progress */
1529#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1530#define ANAK 0x0004 /* Address Not Acknowledged */
1531#define DNAK 0x0008 /* Data Not Acknowledged */
1532#define BUFRDERR 0x0010 /* Buffer Read Error */
1533#define BUFWRERR 0x0020 /* Buffer Write Error */
1534#define SDASEN 0x0040 /* Serial Data Sense */
1535#define SCLSEN 0x0080 /* Serial Clock Sense */
1536#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1537
1538/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1539#define SINIT 0x0001 /* Slave Transfer Initiated */
1540#define SCOMP 0x0002 /* Slave Transfer Complete */
1541#define SERR 0x0004 /* Slave Transfer Error */
1542#define SOVF 0x0008 /* Slave Overflow */
1543#define MCOMP 0x0010 /* Master Transfer Complete */
1544#define MERR 0x0020 /* Master Transfer Error */
1545#define XMTSERV 0x0040 /* Transmit FIFO Service */
1546#define RCVSERV 0x0080 /* Receive FIFO Service */
1547
1548/* TWI_FIFO_CTRL Masks */
1549#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1550#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1551#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1552#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1553
1554/* TWI_FIFO_STAT Masks */
1555#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1556#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1557#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1558#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1559
1560#define RCVSTAT 0x000C /* Receive FIFO Status */
1561#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1562#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1563#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1564
1565
1566/* Omit CAN masks from defBF534.h */
1567
1568/* ******************* PIN CONTROL REGISTER MASKS ************************/
1569/* PORT_MUX Masks */
1570#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1571#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1572#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1573
1574#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1575#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1576#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1577#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1578
1579#define PFDE 0x0008 /* Port F DMA Request Enable */
1580#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1581#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1582
1583#define PFTE 0x0010 /* Port F Timer Enable */
1584#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1585#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1586
1587#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1588#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1589#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1590
1591#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1592#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1593#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1594
1595#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1596#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1597#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1598
1599#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1600#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1601#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1602
1603#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1604#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1605#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1606
1607#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1608#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1609#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1610
1611#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1612#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1613#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1614
1615
1616/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1617/* HDMAx_CTL Masks */
1618#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1619#define REP 0x0002 /* HDMA Request Polarity */
1620#define UTE 0x0004 /* Urgency Threshold Enable */
1621#define OIE 0x0010 /* Overflow Interrupt Enable */
1622#define BDIE 0x0020 /* Block Done Interrupt Enable */
1623#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1624#define DRQ 0x0300 /* HDMA Request Type */
1625#define DRQ_NONE 0x0000 /* No Request */
1626#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1627#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1628#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1629#define RBC 0x1000 /* Reload BCNT With IBCNT */
1630#define PS 0x2000 /* HDMA Pin Status */
1631#define OI 0x4000 /* Overflow Interrupt Generated */
1632#define BDI 0x8000 /* Block Done Interrupt Generated */
1633
1634/* entry addresses of the user-callable Boot ROM functions */
1635
1636#define _BOOTROM_RESET 0xEF000000
1637#define _BOOTROM_FINAL_INIT 0xEF000002
1638#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1639#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1640#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1641#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1642#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1643#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1644#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1645
1646/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1647#define PGDE_UART PFDE_UART
1648#define PGDE_DMA PFDE_DMA
1649#define CKELOW SCKELOW
1650
1651/* ==== end from defBF534.h ==== */
1652
1653/* HOST Port Registers */
1654
1655#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1656#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1657#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1658
1659/* Counter Registers */
1660
1661#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1662#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1663#define CNT_STATUS 0xffc03508 /* Status Register */
1664#define CNT_COMMAND 0xffc0350c /* Command Register */
1665#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1666#define CNT_COUNTER 0xffc03514 /* Counter Register */
1667#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1668#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1669
1670/* OTP/FUSE Registers */
1671
1672#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1673#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1674#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1675#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1676
1677/* Security Registers */
1678
1679#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1680#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1681#define SECURE_STATUS 0xffc03628 /* Secure Status */
1682
1683/* OTP Read/Write Data Buffer Registers */
1684
1685#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1686#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1687#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1688#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1689
1690/* NFC Registers */
1691
1692#define NFC_CTL 0xffc03700 /* NAND Control Register */
1693#define NFC_STAT 0xffc03704 /* NAND Status Register */
1694#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
1695#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
1696#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
1697#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
1698#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
1699#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
1700#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
1701#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
1702#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
1703#define NFC_READ 0xffc0372c /* NAND Read Data Register */
1704#define NFC_ADDR 0xffc03740 /* NAND Address Register */
1705#define NFC_CMD 0xffc03744 /* NAND Command Register */
1706#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1707#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1708
1709/* ********************************************************** */
1710/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1711/* and MULTI BIT READ MACROS */
1712/* ********************************************************** */
1713
1714/* Bit masks for HOST_CONTROL */
1715
1716#define HOST_EN 0x1 /* Host Enable */
1717#define nHOST_EN 0x0
1718#define HOST_END 0x2 /* Host Endianess */
1719#define nHOST_END 0x0
1720#define DATA_SIZE 0x4 /* Data Size */
1721#define nDATA_SIZE 0x0
1722#define HOST_RST 0x8 /* Host Reset */
1723#define nHOST_RST 0x0
1724#define HRDY_OVR 0x20 /* Host Ready Override */
1725#define nHRDY_OVR 0x0
1726#define INT_MODE 0x40 /* Interrupt Mode */
1727#define nINT_MODE 0x0
1728#define BT_EN 0x80 /* Bus Timeout Enable */
1729#define nBT_EN 0x0
1730#define EHW 0x100 /* Enable Host Write */
1731#define nEHW 0x0
1732#define EHR 0x200 /* Enable Host Read */
1733#define nEHR 0x0
1734#define BDR 0x400 /* Burst DMA Requests */
1735#define nBDR 0x0
1736
1737/* Bit masks for HOST_STATUS */
1738
1739#define READY 0x1 /* DMA Ready */
1740#define nREADY 0x0
1741#define FIFOFULL 0x2 /* FIFO Full */
1742#define nFIFOFULL 0x0
1743#define FIFOEMPTY 0x4 /* FIFO Empty */
1744#define nFIFOEMPTY 0x0
1745#define COMPLETE 0x8 /* DMA Complete */
1746#define nCOMPLETE 0x0
1747#define HSHK 0x10 /* Host Handshake */
1748#define nHSHK 0x0
1749#define TIMEOUT 0x20 /* Host Timeout */
1750#define nTIMEOUT 0x0
1751#define HIRQ 0x40 /* Host Interrupt Request */
1752#define nHIRQ 0x0
1753#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1754#define nALLOW_CNFG 0x0
1755#define DMA_DIR 0x100 /* DMA Direction */
1756#define nDMA_DIR 0x0
1757#define BTE 0x200 /* Bus Timeout Enabled */
1758#define nBTE 0x0
1759#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1760#define nHOSTRD_DONE 0x0
1761
1762/* Bit masks for HOST_TIMEOUT */
1763
1764#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1765
1766/* Bit masks for CNT_CONFIG */
1767
1768#define CNTE 0x1 /* Counter Enable */
1769#define nCNTE 0x0
1770#define DEBE 0x2 /* Debounce Enable */
1771#define nDEBE 0x0
1772#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1773#define nCDGINV 0x0
1774#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1775#define nCUDINV 0x0
1776#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1777#define nCZMINV 0x0
1778#define CNTMODE 0x700 /* Counter Operating Mode */
1779#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1780#define nZMZC 0x0
1781#define BNDMODE 0x3000 /* Boundary register Mode */
1782#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1783#define nINPDIS 0x0
1784
1785/* Bit masks for CNT_IMASK */
1786
1787#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1788#define nICIE 0x0
1789#define UCIE 0x2 /* Up count Interrupt Enable */
1790#define nUCIE 0x0
1791#define DCIE 0x4 /* Down count Interrupt Enable */
1792#define nDCIE 0x0
1793#define MINCIE 0x8 /* Min Count Interrupt Enable */
1794#define nMINCIE 0x0
1795#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1796#define nMAXCIE 0x0
1797#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1798#define nCOV31IE 0x0
1799#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1800#define nCOV15IE 0x0
1801#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1802#define nCZEROIE 0x0
1803#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1804#define nCZMIE 0x0
1805#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1806#define nCZMEIE 0x0
1807#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1808#define nCZMZIE 0x0
1809
1810/* Bit masks for CNT_STATUS */
1811
1812#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1813#define nICII 0x0
1814#define UCII 0x2 /* Up count Interrupt Identifier */
1815#define nUCII 0x0
1816#define DCII 0x4 /* Down count Interrupt Identifier */
1817#define nDCII 0x0
1818#define MINCII 0x8 /* Min Count Interrupt Identifier */
1819#define nMINCII 0x0
1820#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1821#define nMAXCII 0x0
1822#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1823#define nCOV31II 0x0
1824#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1825#define nCOV15II 0x0
1826#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1827#define nCZEROII 0x0
1828#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1829#define nCZMII 0x0
1830#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1831#define nCZMEII 0x0
1832#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1833#define nCZMZII 0x0
1834
1835/* Bit masks for CNT_COMMAND */
1836
1837#define W1LCNT 0xf /* Load Counter Register */
1838#define W1LMIN 0xf0 /* Load Min Register */
1839#define W1LMAX 0xf00 /* Load Max Register */
1840#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1841#define nW1ZMONCE 0x0
1842
1843/* Bit masks for CNT_DEBOUNCE */
1844
1845#define DPRESCALE 0xf /* Load Counter Register */
1846
1847/* Bit masks for OTP_CONTROL */
1848
1849#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
1850#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
1851#define nFIEN 0x0
1852#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
1853#define nFTESTDEC 0x0
1854#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
1855#define nFWRTEST 0x0
1856#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
1857#define nFRDEN 0x0
1858#define FWREN 0x8000 /* OTP/Fuse Write Enable */
1859#define nFWREN 0x0
1860
1861/* Bit masks for OTP_BEN */
1862
1863#define FBEN 0xffff /* OTP/Fuse Byte Enable */
1864
1865/* Bit masks for OTP_STATUS */
1866
1867#define FCOMP 0x1 /* OTP/Fuse Access Complete */
1868#define nFCOMP 0x0
1869#define FERROR 0x2 /* OTP/Fuse Access Error */
1870#define nFERROR 0x0
1871#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
1872#define nMMRGLOAD 0x0
1873#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
1874#define nMMRGLOCK 0x0
1875#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
1876#define nFPGMEN 0x0
1877
1878/* Bit masks for OTP_TIMING */
1879
1880#define USECDIV 0xff /* Micro Second Divider */
1881#define READACC 0x7f00 /* Read Access Time */
1882#define CPUMPRL 0x38000 /* Charge Pump Release Time */
1883#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
1884#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
1885#define PGMTIME 0xff000000 /* Program Time */
1886
1887/* Bit masks for SECURE_SYSSWT */
1888
1889#define EMUDABL 0x1 /* Emulation Disable. */
1890#define nEMUDABL 0x0
1891#define RSTDABL 0x2 /* Reset Disable */
1892#define nRSTDABL 0x0
1893#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1894#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1895#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1896#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1897#define nDMA0OVR 0x0
1898#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1899#define nDMA1OVR 0x0
1900#define EMUOVR 0x4000 /* Emulation Override */
1901#define nEMUOVR 0x0
1902#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1903#define nOTPSEN 0x0
1904#define L2DABL 0x70000 /* L2 Memory Disable. */
1905
1906/* Bit masks for SECURE_CONTROL */
1907
1908#define SECURE0 0x1 /* SECURE 0 */
1909#define nSECURE0 0x0
1910#define SECURE1 0x2 /* SECURE 1 */
1911#define nSECURE1 0x0
1912#define SECURE2 0x4 /* SECURE 2 */
1913#define nSECURE2 0x0
1914#define SECURE3 0x8 /* SECURE 3 */
1915#define nSECURE3 0x0
1916
1917/* Bit masks for SECURE_STATUS */
1918
1919#define SECMODE 0x3 /* Secured Mode Control State */
1920#define NMI 0x4 /* Non Maskable Interrupt */
1921#define nNMI 0x0
1922#define AFVALID 0x8 /* Authentication Firmware Valid */
1923#define nAFVALID 0x0
1924#define AFEXIT 0x10 /* Authentication Firmware Exit */
1925#define nAFEXIT 0x0
1926#define SECSTAT 0xe0 /* Secure Status */
1927
1928/* Bit masks for NFC_CTL */
1929
1930#define WR_DLY 0xf /* Write Strobe Delay */
1931#define RD_DLY 0xf0 /* Read Strobe Delay */
1932#define NWIDTH 0x100 /* NAND Data Width */
1933#define nNWIDTH 0x0
1934#define PG_SIZE 0x200 /* Page Size */
1935#define nPG_SIZE 0x0
1936
1937/* Bit masks for NFC_STAT */
1938
1939#define NBUSY 0x1 /* Not Busy */
1940#define nNBUSY 0x0
1941#define WB_FULL 0x2 /* Write Buffer Full */
1942#define nWB_FULL 0x0
1943#define PG_WR_STAT 0x4 /* Page Write Pending */
1944#define nPG_WR_STAT 0x0
1945#define PG_RD_STAT 0x8 /* Page Read Pending */
1946#define nPG_RD_STAT 0x0
1947#define WB_EMPTY 0x10 /* Write Buffer Empty */
1948#define nWB_EMPTY 0x0
1949
1950/* Bit masks for NFC_IRQSTAT */
1951
1952#define NBUSYIRQ 0x1 /* Not Busy IRQ */
1953#define nNBUSYIRQ 0x0
1954#define WB_OVF 0x2 /* Write Buffer Overflow */
1955#define nWB_OVF 0x0
1956#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
1957#define nWB_EDGE 0x0
1958#define RD_RDY 0x8 /* Read Data Ready */
1959#define nRD_RDY 0x0
1960#define WR_DONE 0x10 /* Page Write Done */
1961#define nWR_DONE 0x0
1962
1963/* Bit masks for NFC_IRQMASK */
1964
1965#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
1966#define nMASK_BUSYIRQ 0x0
1967#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
1968#define nMASK_WBOVF 0x0
1969#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
1970#define nMASK_WBEMPTY 0x0
1971#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
1972#define nMASK_RDRDY 0x0
1973#define MASK_WRDONE 0x10 /* Mask Write Done */
1974#define nMASK_WRDONE 0x0
1975
1976/* Bit masks for NFC_RST */
1977
1978#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
1979#define nECC_RST 0x0
1980
1981/* Bit masks for NFC_PGCTL */
1982
1983#define PG_RD_START 0x1 /* Page Read Start */
1984#define nPG_RD_START 0x0
1985#define PG_WR_START 0x2 /* Page Write Start */
1986#define nPG_WR_START 0x0
1987
1988/* Bit masks for NFC_ECC0 */
1989
1990#define ECC0 0x7ff /* Parity Calculation Result0 */
1991
1992/* Bit masks for NFC_ECC1 */
1993
1994#define ECC1 0x7ff /* Parity Calculation Result1 */
1995
1996/* Bit masks for NFC_ECC2 */
1997
1998#define ECC2 0x7ff /* Parity Calculation Result2 */
1999
2000/* Bit masks for NFC_ECC3 */
2001
2002#define ECC3 0x7ff /* Parity Calculation Result3 */
2003
2004/* Bit masks for NFC_COUNT */
2005
2006#define ECCCNT 0x3ff /* Transfer Count */
2007
2008
2009#endif /* _DEF_BF52X_H */
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