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authorMichael Hennerich <michael.hennerich@analog.com>2008-04-23 19:32:41 -0400
committerBryan Wu <cooloney@kernel.org>2008-04-23 19:32:41 -0400
commita81501af19830ff43688781edad7e9c0cbd668af (patch)
tree856be99eb74bfc5e6cf20369b633107d8d4170f6 /include/asm-blackfin/mach-bf527
parent4bea8b20fded93871c872bb4a0d7c23345318184 (diff)
[Blackfin] arch: Prevent potential Core Hang situation
If the new value written to the PLL_CTL or VR_CTL register is the same as the previous value, the PLL wake-up will occur immediately (PLL is already locked), but the core and system clock will be bypassed for the PLL_LOCKCNT duration. For this interval, code will execute at the CLKIN rate instead of at the expected CCLK rate. Software should guard against this condition by comparing the current value to the new value before writing the new value. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf527')
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h57
1 files changed, 55 insertions, 2 deletions
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
index 50e14e7da3ee..9dbdbec8ea1b 100644
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -29,18 +29,71 @@
29 */ 29 */
30 30
31#ifndef _CDEF_BF52X_H 31#ifndef _CDEF_BF52X_H
32#define _CDEF_BF52X_H
33
34#include <asm/system.h>
35#include <asm/blackfin.h>
32 36
33#include "defBF52x_base.h" 37#include "defBF52x_base.h"
34 38
39/* Include core specific register pointer definitions */
40#include <asm/mach-common/cdef_LPBlackfin.h>
41
35/* ==== begin from cdefBF534.h ==== */ 42/* ==== begin from cdefBF534.h ==== */
36 43
37/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 44/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
38#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
39#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) 46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
60 bfin_write32(SIC_IWR1, 0);
61
62 bfin_write16(PLL_CTL, val);
63 SSYNC();
64 asm("IDLE;");
65
66 bfin_write32(SIC_IWR0, iwr0);
67 bfin_write32(SIC_IWR1, iwr1);
68 local_irq_restore(flags);
69}
40#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 70#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
41#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 71#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
42#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 72#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
43#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) 73/* Writing to VR_CTL initiates a PLL relock sequence. */
74static __inline__ void bfin_write_VR_CTL(unsigned int val)
75{
76 unsigned long flags, iwr0, iwr1;
77
78 if (val == bfin_read_VR_CTL())
79 return;
80
81 local_irq_save(flags);
82 /* Enable the PLL Wakeup bit in SIC IWR */
83 iwr0 = bfin_read32(SIC_IWR0);
84 iwr1 = bfin_read32(SIC_IWR1);
85 /* Only allow PPL Wakeup) */
86 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
87 bfin_write32(SIC_IWR1, 0);
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR0, iwr0);
94 bfin_write32(SIC_IWR1, iwr1);
95 local_irq_restore(flags);
96}
44#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 97#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 98#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 99#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)