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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-07-26 18:04:59 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-07-26 18:04:59 -0400
commitd9ecdb282c91952796b7542c4f57fd6de6948d7b (patch)
treefd4de7923968afa7d2981fb037e2255fc2cfa1e1 /include/asm-blackfin/mach-bf527/defBF527.h
parent4ef584ba84125b67c17b5aded38e7783cd8cdef0 (diff)
parent1d1f8b377c48e5aeddaea52eba74cc0539f088cd (diff)
Merge branch 'for_rmk_13' of git://git.mnementh.co.uk/linux-2.6-im
Diffstat (limited to 'include/asm-blackfin/mach-bf527/defBF527.h')
-rw-r--r--include/asm-blackfin/mach-bf527/defBF527.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h
index 82134f578f32..f1a70db70cb8 100644
--- a/include/asm-blackfin/mach-bf527/defBF527.h
+++ b/include/asm-blackfin/mach-bf527/defBF527.h
@@ -302,6 +302,7 @@
302#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ 302#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
303#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ 303#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
304#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ 304#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
305#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
305#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ 306#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
306 307
307#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ 308#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */