diff options
author | David Woodhouse <David.Woodhouse@intel.com> | 2008-09-01 06:32:13 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2008-09-01 06:32:13 -0400 |
commit | 9d7548d4ca3c52ecb58f098a32b0756cdf8f96ee (patch) | |
tree | 651f7058bbaa2d8b2855286380d614afcf505118 /include/asm-blackfin/mach-bf527/defBF527.h | |
parent | 31db6e9ea1dbdcf66b8227b4f7035dee1b1dd8c0 (diff) | |
parent | bef69ea0dcce574a425feb0a5aa4c63dd108b9a6 (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-blackfin/mach-bf527/defBF527.h')
-rw-r--r-- | include/asm-blackfin/mach-bf527/defBF527.h | 1090 |
1 files changed, 0 insertions, 1090 deletions
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h deleted file mode 100644 index f1a70db70cb8..000000000000 --- a/include/asm-blackfin/mach-bf527/defBF527.h +++ /dev/null | |||
@@ -1,1090 +0,0 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf527/defBF527.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License as published by | ||
17 | * the Free Software Foundation; either version 2, or (at your option) | ||
18 | * any later version. | ||
19 | * | ||
20 | * This program is distributed in the hope that it will be useful, | ||
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
23 | * GNU General Public License for more details. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License | ||
26 | * along with this program; see the file COPYING. | ||
27 | * If not, write to the Free Software Foundation, | ||
28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
29 | */ | ||
30 | |||
31 | #ifndef _DEF_BF527_H | ||
32 | #define _DEF_BF527_H | ||
33 | |||
34 | /* Include all Core registers and bit definitions */ | ||
35 | #include <asm/mach-common/def_LPBlackfin.h> | ||
36 | |||
37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ | ||
38 | |||
39 | /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ | ||
40 | #include "defBF52x_base.h" | ||
41 | |||
42 | /* The following are the #defines needed by ADSP-BF527 that are not in the common header */ | ||
43 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | ||
44 | |||
45 | #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ | ||
46 | #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ | ||
47 | #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ | ||
48 | #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ | ||
49 | #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ | ||
50 | #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ | ||
51 | #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ | ||
52 | #define EMAC_FLC 0xFFC0301C /* Flow Control Register */ | ||
53 | #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ | ||
54 | #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ | ||
55 | #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ | ||
56 | #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ | ||
57 | #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ | ||
58 | #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ | ||
59 | #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ | ||
60 | #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ | ||
61 | #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ | ||
62 | #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ | ||
63 | #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ | ||
64 | |||
65 | #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ | ||
66 | #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ | ||
67 | #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ | ||
68 | #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ | ||
69 | #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ | ||
70 | #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ | ||
71 | #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ | ||
72 | #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ | ||
73 | |||
74 | #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ | ||
75 | #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ | ||
76 | #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ | ||
77 | #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ | ||
78 | #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ | ||
79 | |||
80 | #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ | ||
81 | #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ | ||
82 | #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ | ||
83 | #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ | ||
84 | #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ | ||
85 | #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ | ||
86 | #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ | ||
87 | #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ | ||
88 | #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ | ||
89 | #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ | ||
90 | #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ | ||
91 | #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ | ||
92 | #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ | ||
93 | #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ | ||
94 | #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ | ||
95 | #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ | ||
96 | #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ | ||
97 | #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
98 | #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ | ||
99 | #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ | ||
100 | #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
101 | #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
102 | #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
103 | #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
104 | |||
105 | #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ | ||
106 | #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ | ||
107 | #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ | ||
108 | #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ | ||
109 | #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ | ||
110 | #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ | ||
111 | #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ | ||
112 | #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ | ||
113 | #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ | ||
114 | #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ | ||
115 | #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ | ||
116 | #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ | ||
117 | #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ | ||
118 | #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ | ||
119 | #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ | ||
120 | #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ | ||
121 | #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ | ||
122 | #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | ||
123 | #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
124 | #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
125 | #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
126 | #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
127 | #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ | ||
128 | |||
129 | /* Listing for IEEE-Supported Count Registers */ | ||
130 | |||
131 | #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ | ||
132 | #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ | ||
133 | #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ | ||
134 | #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ | ||
135 | #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ | ||
136 | #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ | ||
137 | #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ | ||
138 | #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ | ||
139 | #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ | ||
140 | #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ | ||
141 | #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ | ||
142 | #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ | ||
143 | #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ | ||
144 | #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ | ||
145 | #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ | ||
146 | #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ | ||
147 | #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ | ||
148 | #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
149 | #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ | ||
150 | #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ | ||
151 | #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
152 | #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
153 | #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
154 | #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
155 | |||
156 | #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ | ||
157 | #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ | ||
158 | #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ | ||
159 | #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ | ||
160 | #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ | ||
161 | #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ | ||
162 | #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ | ||
163 | #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ | ||
164 | #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ | ||
165 | #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ | ||
166 | #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ | ||
167 | #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ | ||
168 | #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ | ||
169 | #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ | ||
170 | #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ | ||
171 | #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ | ||
172 | #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ | ||
173 | #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | ||
174 | #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
175 | #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
176 | #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
177 | #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
178 | #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ | ||
179 | |||
180 | /*********************************************************************************** | ||
181 | ** System MMR Register Bits And Macros | ||
182 | ** | ||
183 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | ||
184 | ** Use these macros carefully, as any that do left shifts for field | ||
185 | ** depositing will result in the lower order bits being destroyed. Any | ||
186 | ** macro that shifts left to properly position the bit-field should be | ||
187 | ** used as part of an OR to initialize a register and NOT as a dynamic | ||
188 | ** modifier UNLESS the lower order bits are saved and ORed back in when | ||
189 | ** the macro is used. | ||
190 | *************************************************************************************/ | ||
191 | |||
192 | /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ | ||
193 | |||
194 | /* EMAC_OPMODE Masks */ | ||
195 | |||
196 | #define RE 0x00000001 /* Receiver Enable */ | ||
197 | #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ | ||
198 | #define HU 0x00000010 /* Hash Filter Unicast Address */ | ||
199 | #define HM 0x00000020 /* Hash Filter Multicast Address */ | ||
200 | #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ | ||
201 | #define PR 0x00000080 /* Promiscuous Mode Enable */ | ||
202 | #define IFE 0x00000100 /* Inverse Filtering Enable */ | ||
203 | #define DBF 0x00000200 /* Disable Broadcast Frame Reception */ | ||
204 | #define PBF 0x00000400 /* Pass Bad Frames Enable */ | ||
205 | #define PSF 0x00000800 /* Pass Short Frames Enable */ | ||
206 | #define RAF 0x00001000 /* Receive-All Mode */ | ||
207 | #define TE 0x00010000 /* Transmitter Enable */ | ||
208 | #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ | ||
209 | #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ | ||
210 | #define DC 0x00080000 /* Deferral Check */ | ||
211 | #define BOLMT 0x00300000 /* Back-Off Limit */ | ||
212 | #define BOLMT_10 0x00000000 /* 10-bit range */ | ||
213 | #define BOLMT_8 0x00100000 /* 8-bit range */ | ||
214 | #define BOLMT_4 0x00200000 /* 4-bit range */ | ||
215 | #define BOLMT_1 0x00300000 /* 1-bit range */ | ||
216 | #define DRTY 0x00400000 /* Disable TX Retry On Collision */ | ||
217 | #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ | ||
218 | #define RMII 0x01000000 /* RMII/MII* Mode */ | ||
219 | #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ | ||
220 | #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ | ||
221 | #define LB 0x08000000 /* Internal Loopback Enable */ | ||
222 | #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ | ||
223 | |||
224 | /* EMAC_STAADD Masks */ | ||
225 | |||
226 | #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ | ||
227 | #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ | ||
228 | #define STADISPRE 0x00000004 /* Disable Preamble Generation */ | ||
229 | #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ | ||
230 | #define REGAD 0x000007C0 /* STA Register Address */ | ||
231 | #define PHYAD 0x0000F800 /* PHY Device Address */ | ||
232 | |||
233 | #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ | ||
234 | #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ | ||
235 | |||
236 | /* EMAC_STADAT Mask */ | ||
237 | |||
238 | #define STADATA 0x0000FFFF /* Station Management Data */ | ||
239 | |||
240 | /* EMAC_FLC Masks */ | ||
241 | |||
242 | #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ | ||
243 | #define FLCE 0x00000002 /* Flow Control Enable */ | ||
244 | #define PCF 0x00000004 /* Pass Control Frames */ | ||
245 | #define BKPRSEN 0x00000008 /* Enable Backpressure */ | ||
246 | #define FLCPAUSE 0xFFFF0000 /* Pause Time */ | ||
247 | |||
248 | #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ | ||
249 | |||
250 | /* EMAC_WKUP_CTL Masks */ | ||
251 | |||
252 | #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ | ||
253 | #define MPKE 0x00000002 /* Magic Packet Enable */ | ||
254 | #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ | ||
255 | #define GUWKE 0x00000008 /* Global Unicast Wake Enable */ | ||
256 | #define MPKS 0x00000020 /* Magic Packet Received Status */ | ||
257 | #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ | ||
258 | |||
259 | /* EMAC_WKUP_FFCMD Masks */ | ||
260 | |||
261 | #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ | ||
262 | #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ | ||
263 | #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ | ||
264 | #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ | ||
265 | #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ | ||
266 | #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ | ||
267 | #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ | ||
268 | #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ | ||
269 | |||
270 | /* EMAC_WKUP_FFOFF Masks */ | ||
271 | |||
272 | #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ | ||
273 | #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ | ||
274 | #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ | ||
275 | #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ | ||
276 | |||
277 | #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ | ||
278 | #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ | ||
279 | #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ | ||
280 | #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ | ||
281 | /* Set ALL Offsets */ | ||
282 | #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) | ||
283 | |||
284 | /* EMAC_WKUP_FFCRC0 Masks */ | ||
285 | |||
286 | #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ | ||
287 | #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ | ||
288 | |||
289 | #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ | ||
290 | #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ | ||
291 | |||
292 | /* EMAC_WKUP_FFCRC1 Masks */ | ||
293 | |||
294 | #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ | ||
295 | #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ | ||
296 | |||
297 | #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ | ||
298 | #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ | ||
299 | |||
300 | /* EMAC_SYSCTL Masks */ | ||
301 | |||
302 | #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ | ||
303 | #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ | ||
304 | #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ | ||
305 | #define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ | ||
306 | #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ | ||
307 | |||
308 | #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ | ||
309 | |||
310 | /* EMAC_SYSTAT Masks */ | ||
311 | |||
312 | #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ | ||
313 | #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ | ||
314 | #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ | ||
315 | #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ | ||
316 | #define WAKEDET 0x00000010 /* Wake-Up Detected Status */ | ||
317 | #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ | ||
318 | #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ | ||
319 | #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ | ||
320 | |||
321 | /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ | ||
322 | |||
323 | #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ | ||
324 | #define RX_COMP 0x00001000 /* RX Frame Complete */ | ||
325 | #define RX_OK 0x00002000 /* RX Frame Received With No Errors */ | ||
326 | #define RX_LONG 0x00004000 /* RX Frame Too Long Error */ | ||
327 | #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ | ||
328 | #define RX_CRC 0x00010000 /* RX Frame CRC Error */ | ||
329 | #define RX_LEN 0x00020000 /* RX Frame Length Error */ | ||
330 | #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ | ||
331 | #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ | ||
332 | #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ | ||
333 | #define RX_PHY 0x00200000 /* RX Frame PHY Error */ | ||
334 | #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ | ||
335 | #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ | ||
336 | #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ | ||
337 | #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ | ||
338 | #define RX_CTL 0x04000000 /* RX Control Frame Indicator */ | ||
339 | #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ | ||
340 | #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ | ||
341 | #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ | ||
342 | #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ | ||
343 | #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ | ||
344 | |||
345 | /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ | ||
346 | |||
347 | #define TX_COMP 0x00000001 /* TX Frame Complete */ | ||
348 | #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ | ||
349 | #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ | ||
350 | #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ | ||
351 | #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ | ||
352 | #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ | ||
353 | #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ | ||
354 | #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ | ||
355 | #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ | ||
356 | #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ | ||
357 | #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ | ||
358 | #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ | ||
359 | #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ | ||
360 | #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ | ||
361 | #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ | ||
362 | |||
363 | /* EMAC_MMC_CTL Masks */ | ||
364 | #define RSTC 0x00000001 /* Reset All Counters */ | ||
365 | #define CROLL 0x00000002 /* Counter Roll-Over Enable */ | ||
366 | #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ | ||
367 | #define MMCE 0x00000008 /* Enable MMC Counter Operation */ | ||
368 | |||
369 | /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ | ||
370 | #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ | ||
371 | #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ | ||
372 | #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ | ||
373 | #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ | ||
374 | #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ | ||
375 | #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ | ||
376 | #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ | ||
377 | #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ | ||
378 | #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ | ||
379 | #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ | ||
380 | #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ | ||
381 | #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ | ||
382 | #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ | ||
383 | #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ | ||
384 | #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ | ||
385 | #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ | ||
386 | #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ | ||
387 | #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ | ||
388 | #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ | ||
389 | #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ | ||
390 | #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ | ||
391 | #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ | ||
392 | #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ | ||
393 | #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ | ||
394 | |||
395 | /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ | ||
396 | |||
397 | #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ | ||
398 | #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ | ||
399 | #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ | ||
400 | #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ | ||
401 | #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ | ||
402 | #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ | ||
403 | #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ | ||
404 | #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ | ||
405 | #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ | ||
406 | #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ | ||
407 | #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ | ||
408 | #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ | ||
409 | #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ | ||
410 | #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ | ||
411 | #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ | ||
412 | #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ | ||
413 | #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ | ||
414 | #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ | ||
415 | #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ | ||
416 | #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ | ||
417 | #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ | ||
418 | #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ | ||
419 | #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ | ||
420 | |||
421 | /* USB Control Registers */ | ||
422 | |||
423 | #define USB_FADDR 0xffc03800 /* Function address register */ | ||
424 | #define USB_POWER 0xffc03804 /* Power management register */ | ||
425 | #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ | ||
426 | #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ | ||
427 | #define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ | ||
428 | #define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ | ||
429 | #define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ | ||
430 | #define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ | ||
431 | #define USB_FRAME 0xffc03820 /* USB frame number */ | ||
432 | #define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ | ||
433 | #define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ | ||
434 | #define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ | ||
435 | #define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ | ||
436 | |||
437 | /* USB Packet Control Registers */ | ||
438 | |||
439 | #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ | ||
440 | #define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | ||
441 | #define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | ||
442 | #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ | ||
443 | #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ | ||
444 | #define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | ||
445 | #define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | ||
446 | #define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ | ||
447 | #define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | ||
448 | #define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | ||
449 | #define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ | ||
450 | #define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ | ||
451 | #define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ | ||
452 | |||
453 | /* USB Endpoint FIFO Registers */ | ||
454 | |||
455 | #define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ | ||
456 | #define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ | ||
457 | #define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ | ||
458 | #define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ | ||
459 | #define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ | ||
460 | #define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ | ||
461 | #define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ | ||
462 | #define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ | ||
463 | |||
464 | /* USB OTG Control Registers */ | ||
465 | |||
466 | #define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ | ||
467 | #define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ | ||
468 | #define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ | ||
469 | |||
470 | /* USB Phy Control Registers */ | ||
471 | |||
472 | #define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ | ||
473 | #define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ | ||
474 | #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ | ||
475 | #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ | ||
476 | #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ | ||
477 | |||
478 | /* (APHY_CNTRL is for ADI usage only) */ | ||
479 | |||
480 | #define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ | ||
481 | |||
482 | /* (APHY_CALIB is for ADI usage only) */ | ||
483 | |||
484 | #define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ | ||
485 | |||
486 | #define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ | ||
487 | |||
488 | /* (PHY_TEST is for ADI usage only) */ | ||
489 | |||
490 | #define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ | ||
491 | |||
492 | #define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ | ||
493 | #define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ | ||
494 | |||
495 | /* USB Endpoint 0 Control Registers */ | ||
496 | |||
497 | #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ | ||
498 | #define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ | ||
499 | #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ | ||
500 | #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ | ||
501 | #define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ | ||
502 | #define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ | ||
503 | #define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ | ||
504 | #define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ | ||
505 | #define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ | ||
506 | #define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ | ||
507 | |||
508 | /* USB Endpoint 1 Control Registers */ | ||
509 | |||
510 | #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ | ||
511 | #define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ | ||
512 | #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ | ||
513 | #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ | ||
514 | #define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ | ||
515 | #define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ | ||
516 | #define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ | ||
517 | #define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ | ||
518 | #define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ | ||
519 | #define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ | ||
520 | |||
521 | /* USB Endpoint 2 Control Registers */ | ||
522 | |||
523 | #define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ | ||
524 | #define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ | ||
525 | #define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ | ||
526 | #define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ | ||
527 | #define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ | ||
528 | #define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ | ||
529 | #define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ | ||
530 | #define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ | ||
531 | #define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ | ||
532 | #define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ | ||
533 | |||
534 | /* USB Endpoint 3 Control Registers */ | ||
535 | |||
536 | #define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ | ||
537 | #define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ | ||
538 | #define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ | ||
539 | #define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ | ||
540 | #define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ | ||
541 | #define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ | ||
542 | #define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ | ||
543 | #define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ | ||
544 | #define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ | ||
545 | #define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ | ||
546 | |||
547 | /* USB Endpoint 4 Control Registers */ | ||
548 | |||
549 | #define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ | ||
550 | #define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ | ||
551 | #define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ | ||
552 | #define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ | ||
553 | #define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ | ||
554 | #define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ | ||
555 | #define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ | ||
556 | #define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ | ||
557 | #define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ | ||
558 | #define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ | ||
559 | |||
560 | /* USB Endpoint 5 Control Registers */ | ||
561 | |||
562 | #define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ | ||
563 | #define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ | ||
564 | #define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ | ||
565 | #define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ | ||
566 | #define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ | ||
567 | #define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ | ||
568 | #define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ | ||
569 | #define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ | ||
570 | #define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ | ||
571 | #define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ | ||
572 | |||
573 | /* USB Endpoint 6 Control Registers */ | ||
574 | |||
575 | #define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ | ||
576 | #define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ | ||
577 | #define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ | ||
578 | #define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ | ||
579 | #define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ | ||
580 | #define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ | ||
581 | #define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ | ||
582 | #define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ | ||
583 | #define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ | ||
584 | #define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ | ||
585 | |||
586 | /* USB Endpoint 7 Control Registers */ | ||
587 | |||
588 | #define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ | ||
589 | #define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ | ||
590 | #define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ | ||
591 | #define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ | ||
592 | #define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ | ||
593 | #define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ | ||
594 | #define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ | ||
595 | #define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ | ||
596 | #define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ | ||
597 | #define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ | ||
598 | |||
599 | #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ | ||
600 | |||
601 | /* USB Channel 0 Config Registers */ | ||
602 | |||
603 | #define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ | ||
604 | #define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ | ||
605 | #define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ | ||
606 | #define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ | ||
607 | #define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ | ||
608 | |||
609 | /* USB Channel 1 Config Registers */ | ||
610 | |||
611 | #define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ | ||
612 | #define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ | ||
613 | #define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ | ||
614 | #define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ | ||
615 | #define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ | ||
616 | |||
617 | /* USB Channel 2 Config Registers */ | ||
618 | |||
619 | #define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ | ||
620 | #define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ | ||
621 | #define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ | ||
622 | #define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ | ||
623 | #define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ | ||
624 | |||
625 | /* USB Channel 3 Config Registers */ | ||
626 | |||
627 | #define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ | ||
628 | #define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ | ||
629 | #define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ | ||
630 | #define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ | ||
631 | #define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ | ||
632 | |||
633 | /* USB Channel 4 Config Registers */ | ||
634 | |||
635 | #define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ | ||
636 | #define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ | ||
637 | #define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ | ||
638 | #define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ | ||
639 | #define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ | ||
640 | |||
641 | /* USB Channel 5 Config Registers */ | ||
642 | |||
643 | #define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ | ||
644 | #define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ | ||
645 | #define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ | ||
646 | #define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ | ||
647 | #define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ | ||
648 | |||
649 | /* USB Channel 6 Config Registers */ | ||
650 | |||
651 | #define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ | ||
652 | #define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ | ||
653 | #define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ | ||
654 | #define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ | ||
655 | #define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ | ||
656 | |||
657 | /* USB Channel 7 Config Registers */ | ||
658 | |||
659 | #define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ | ||
660 | #define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ | ||
661 | #define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ | ||
662 | #define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ | ||
663 | #define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ | ||
664 | |||
665 | /* Bit masks for USB_FADDR */ | ||
666 | |||
667 | #define FUNCTION_ADDRESS 0x7f /* Function address */ | ||
668 | |||
669 | /* Bit masks for USB_POWER */ | ||
670 | |||
671 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | ||
672 | #define nENABLE_SUSPENDM 0x0 | ||
673 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | ||
674 | #define nSUSPEND_MODE 0x0 | ||
675 | #define RESUME_MODE 0x4 /* DMA Mode */ | ||
676 | #define nRESUME_MODE 0x0 | ||
677 | #define RESET 0x8 /* Reset indicator */ | ||
678 | #define nRESET 0x0 | ||
679 | #define HS_MODE 0x10 /* High Speed mode indicator */ | ||
680 | #define nHS_MODE 0x0 | ||
681 | #define HS_ENABLE 0x20 /* high Speed Enable */ | ||
682 | #define nHS_ENABLE 0x0 | ||
683 | #define SOFT_CONN 0x40 /* Soft connect */ | ||
684 | #define nSOFT_CONN 0x0 | ||
685 | #define ISO_UPDATE 0x80 /* Isochronous update */ | ||
686 | #define nISO_UPDATE 0x0 | ||
687 | |||
688 | /* Bit masks for USB_INTRTX */ | ||
689 | |||
690 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | ||
691 | #define nEP0_TX 0x0 | ||
692 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | ||
693 | #define nEP1_TX 0x0 | ||
694 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | ||
695 | #define nEP2_TX 0x0 | ||
696 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | ||
697 | #define nEP3_TX 0x0 | ||
698 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | ||
699 | #define nEP4_TX 0x0 | ||
700 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | ||
701 | #define nEP5_TX 0x0 | ||
702 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | ||
703 | #define nEP6_TX 0x0 | ||
704 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | ||
705 | #define nEP7_TX 0x0 | ||
706 | |||
707 | /* Bit masks for USB_INTRRX */ | ||
708 | |||
709 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | ||
710 | #define nEP1_RX 0x0 | ||
711 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | ||
712 | #define nEP2_RX 0x0 | ||
713 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | ||
714 | #define nEP3_RX 0x0 | ||
715 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | ||
716 | #define nEP4_RX 0x0 | ||
717 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | ||
718 | #define nEP5_RX 0x0 | ||
719 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | ||
720 | #define nEP6_RX 0x0 | ||
721 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | ||
722 | #define nEP7_RX 0x0 | ||
723 | |||
724 | /* Bit masks for USB_INTRTXE */ | ||
725 | |||
726 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | ||
727 | #define nEP0_TX_E 0x0 | ||
728 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | ||
729 | #define nEP1_TX_E 0x0 | ||
730 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | ||
731 | #define nEP2_TX_E 0x0 | ||
732 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | ||
733 | #define nEP3_TX_E 0x0 | ||
734 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | ||
735 | #define nEP4_TX_E 0x0 | ||
736 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | ||
737 | #define nEP5_TX_E 0x0 | ||
738 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | ||
739 | #define nEP6_TX_E 0x0 | ||
740 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | ||
741 | #define nEP7_TX_E 0x0 | ||
742 | |||
743 | /* Bit masks for USB_INTRRXE */ | ||
744 | |||
745 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | ||
746 | #define nEP1_RX_E 0x0 | ||
747 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | ||
748 | #define nEP2_RX_E 0x0 | ||
749 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | ||
750 | #define nEP3_RX_E 0x0 | ||
751 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | ||
752 | #define nEP4_RX_E 0x0 | ||
753 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | ||
754 | #define nEP5_RX_E 0x0 | ||
755 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | ||
756 | #define nEP6_RX_E 0x0 | ||
757 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | ||
758 | #define nEP7_RX_E 0x0 | ||
759 | |||
760 | /* Bit masks for USB_INTRUSB */ | ||
761 | |||
762 | #define SUSPEND_B 0x1 /* Suspend indicator */ | ||
763 | #define nSUSPEND_B 0x0 | ||
764 | #define RESUME_B 0x2 /* Resume indicator */ | ||
765 | #define nRESUME_B 0x0 | ||
766 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | ||
767 | #define nRESET_OR_BABLE_B 0x0 | ||
768 | #define SOF_B 0x8 /* Start of frame */ | ||
769 | #define nSOF_B 0x0 | ||
770 | #define CONN_B 0x10 /* Connection indicator */ | ||
771 | #define nCONN_B 0x0 | ||
772 | #define DISCON_B 0x20 /* Disconnect indicator */ | ||
773 | #define nDISCON_B 0x0 | ||
774 | #define SESSION_REQ_B 0x40 /* Session Request */ | ||
775 | #define nSESSION_REQ_B 0x0 | ||
776 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | ||
777 | #define nVBUS_ERROR_B 0x0 | ||
778 | |||
779 | /* Bit masks for USB_INTRUSBE */ | ||
780 | |||
781 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | ||
782 | #define nSUSPEND_BE 0x0 | ||
783 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | ||
784 | #define nRESUME_BE 0x0 | ||
785 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | ||
786 | #define nRESET_OR_BABLE_BE 0x0 | ||
787 | #define SOF_BE 0x8 /* Start of frame int enable */ | ||
788 | #define nSOF_BE 0x0 | ||
789 | #define CONN_BE 0x10 /* Connection indicator int enable */ | ||
790 | #define nCONN_BE 0x0 | ||
791 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | ||
792 | #define nDISCON_BE 0x0 | ||
793 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | ||
794 | #define nSESSION_REQ_BE 0x0 | ||
795 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | ||
796 | #define nVBUS_ERROR_BE 0x0 | ||
797 | |||
798 | /* Bit masks for USB_FRAME */ | ||
799 | |||
800 | #define FRAME_NUMBER 0x7ff /* Frame number */ | ||
801 | |||
802 | /* Bit masks for USB_INDEX */ | ||
803 | |||
804 | #define SELECTED_ENDPOINT 0xf /* selected endpoint */ | ||
805 | |||
806 | /* Bit masks for USB_GLOBAL_CTL */ | ||
807 | |||
808 | #define GLOBAL_ENA 0x1 /* enables USB module */ | ||
809 | #define nGLOBAL_ENA 0x0 | ||
810 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | ||
811 | #define nEP1_TX_ENA 0x0 | ||
812 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | ||
813 | #define nEP2_TX_ENA 0x0 | ||
814 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | ||
815 | #define nEP3_TX_ENA 0x0 | ||
816 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | ||
817 | #define nEP4_TX_ENA 0x0 | ||
818 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | ||
819 | #define nEP5_TX_ENA 0x0 | ||
820 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | ||
821 | #define nEP6_TX_ENA 0x0 | ||
822 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | ||
823 | #define nEP7_TX_ENA 0x0 | ||
824 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | ||
825 | #define nEP1_RX_ENA 0x0 | ||
826 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | ||
827 | #define nEP2_RX_ENA 0x0 | ||
828 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | ||
829 | #define nEP3_RX_ENA 0x0 | ||
830 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | ||
831 | #define nEP4_RX_ENA 0x0 | ||
832 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | ||
833 | #define nEP5_RX_ENA 0x0 | ||
834 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | ||
835 | #define nEP6_RX_ENA 0x0 | ||
836 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | ||
837 | #define nEP7_RX_ENA 0x0 | ||
838 | |||
839 | /* Bit masks for USB_OTG_DEV_CTL */ | ||
840 | |||
841 | #define SESSION 0x1 /* session indicator */ | ||
842 | #define nSESSION 0x0 | ||
843 | #define HOST_REQ 0x2 /* Host negotiation request */ | ||
844 | #define nHOST_REQ 0x0 | ||
845 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | ||
846 | #define nHOST_MODE 0x0 | ||
847 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | ||
848 | #define nVBUS0 0x0 | ||
849 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | ||
850 | #define nVBUS1 0x0 | ||
851 | #define LSDEV 0x20 /* Low-speed indicator */ | ||
852 | #define nLSDEV 0x0 | ||
853 | #define FSDEV 0x40 /* Full or High-speed indicator */ | ||
854 | #define nFSDEV 0x0 | ||
855 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | ||
856 | #define nB_DEVICE 0x0 | ||
857 | |||
858 | /* Bit masks for USB_OTG_VBUS_IRQ */ | ||
859 | |||
860 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | ||
861 | #define nDRIVE_VBUS_ON 0x0 | ||
862 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | ||
863 | #define nDRIVE_VBUS_OFF 0x0 | ||
864 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | ||
865 | #define nCHRG_VBUS_START 0x0 | ||
866 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | ||
867 | #define nCHRG_VBUS_END 0x0 | ||
868 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | ||
869 | #define nDISCHRG_VBUS_START 0x0 | ||
870 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | ||
871 | #define nDISCHRG_VBUS_END 0x0 | ||
872 | |||
873 | /* Bit masks for USB_OTG_VBUS_MASK */ | ||
874 | |||
875 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | ||
876 | #define nDRIVE_VBUS_ON_ENA 0x0 | ||
877 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | ||
878 | #define nDRIVE_VBUS_OFF_ENA 0x0 | ||
879 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | ||
880 | #define nCHRG_VBUS_START_ENA 0x0 | ||
881 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | ||
882 | #define nCHRG_VBUS_END_ENA 0x0 | ||
883 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | ||
884 | #define nDISCHRG_VBUS_START_ENA 0x0 | ||
885 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | ||
886 | #define nDISCHRG_VBUS_END_ENA 0x0 | ||
887 | |||
888 | /* Bit masks for USB_CSR0 */ | ||
889 | |||
890 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | ||
891 | #define nRXPKTRDY 0x0 | ||
892 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | ||
893 | #define nTXPKTRDY 0x0 | ||
894 | #define STALL_SENT 0x4 /* STALL handshake sent */ | ||
895 | #define nSTALL_SENT 0x0 | ||
896 | #define DATAEND 0x8 /* Data end indicator */ | ||
897 | #define nDATAEND 0x0 | ||
898 | #define SETUPEND 0x10 /* Setup end */ | ||
899 | #define nSETUPEND 0x0 | ||
900 | #define SENDSTALL 0x20 /* Send STALL handshake */ | ||
901 | #define nSENDSTALL 0x0 | ||
902 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | ||
903 | #define nSERVICED_RXPKTRDY 0x0 | ||
904 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | ||
905 | #define nSERVICED_SETUPEND 0x0 | ||
906 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | ||
907 | #define nFLUSHFIFO 0x0 | ||
908 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | ||
909 | #define nSTALL_RECEIVED_H 0x0 | ||
910 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | ||
911 | #define nSETUPPKT_H 0x0 | ||
912 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | ||
913 | #define nERROR_H 0x0 | ||
914 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | ||
915 | #define nREQPKT_H 0x0 | ||
916 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | ||
917 | #define nSTATUSPKT_H 0x0 | ||
918 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | ||
919 | #define nNAK_TIMEOUT_H 0x0 | ||
920 | |||
921 | /* Bit masks for USB_COUNT0 */ | ||
922 | |||
923 | #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ | ||
924 | |||
925 | /* Bit masks for USB_NAKLIMIT0 */ | ||
926 | |||
927 | #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ | ||
928 | |||
929 | /* Bit masks for USB_TX_MAX_PACKET */ | ||
930 | |||
931 | #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ | ||
932 | |||
933 | /* Bit masks for USB_RX_MAX_PACKET */ | ||
934 | |||
935 | #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ | ||
936 | |||
937 | /* Bit masks for USB_TXCSR */ | ||
938 | |||
939 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | ||
940 | #define nTXPKTRDY_T 0x0 | ||
941 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | ||
942 | #define nFIFO_NOT_EMPTY_T 0x0 | ||
943 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | ||
944 | #define nUNDERRUN_T 0x0 | ||
945 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | ||
946 | #define nFLUSHFIFO_T 0x0 | ||
947 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | ||
948 | #define nSTALL_SEND_T 0x0 | ||
949 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | ||
950 | #define nSTALL_SENT_T 0x0 | ||
951 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | ||
952 | #define nCLEAR_DATATOGGLE_T 0x0 | ||
953 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | ||
954 | #define nINCOMPTX_T 0x0 | ||
955 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | ||
956 | #define nDMAREQMODE_T 0x0 | ||
957 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | ||
958 | #define nFORCE_DATATOGGLE_T 0x0 | ||
959 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | ||
960 | #define nDMAREQ_ENA_T 0x0 | ||
961 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | ||
962 | #define nISO_T 0x0 | ||
963 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | ||
964 | #define nAUTOSET_T 0x0 | ||
965 | #define ERROR_TH 0x4 /* error condition host mode */ | ||
966 | #define nERROR_TH 0x0 | ||
967 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | ||
968 | #define nSTALL_RECEIVED_TH 0x0 | ||
969 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | ||
970 | #define nNAK_TIMEOUT_TH 0x0 | ||
971 | |||
972 | /* Bit masks for USB_TXCOUNT */ | ||
973 | |||
974 | #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ | ||
975 | |||
976 | /* Bit masks for USB_RXCSR */ | ||
977 | |||
978 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | ||
979 | #define nRXPKTRDY_R 0x0 | ||
980 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | ||
981 | #define nFIFO_FULL_R 0x0 | ||
982 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | ||
983 | #define nOVERRUN_R 0x0 | ||
984 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | ||
985 | #define nDATAERROR_R 0x0 | ||
986 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | ||
987 | #define nFLUSHFIFO_R 0x0 | ||
988 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | ||
989 | #define nSTALL_SEND_R 0x0 | ||
990 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | ||
991 | #define nSTALL_SENT_R 0x0 | ||
992 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | ||
993 | #define nCLEAR_DATATOGGLE_R 0x0 | ||
994 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | ||
995 | #define nINCOMPRX_R 0x0 | ||
996 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | ||
997 | #define nDMAREQMODE_R 0x0 | ||
998 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | ||
999 | #define nDISNYET_R 0x0 | ||
1000 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | ||
1001 | #define nDMAREQ_ENA_R 0x0 | ||
1002 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | ||
1003 | #define nISO_R 0x0 | ||
1004 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | ||
1005 | #define nAUTOCLEAR_R 0x0 | ||
1006 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | ||
1007 | #define nERROR_RH 0x0 | ||
1008 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | ||
1009 | #define nREQPKT_RH 0x0 | ||
1010 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | ||
1011 | #define nSTALL_RECEIVED_RH 0x0 | ||
1012 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | ||
1013 | #define nINCOMPRX_RH 0x0 | ||
1014 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | ||
1015 | #define nDMAREQMODE_RH 0x0 | ||
1016 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | ||
1017 | #define nAUTOREQ_RH 0x0 | ||
1018 | |||
1019 | /* Bit masks for USB_RXCOUNT */ | ||
1020 | |||
1021 | #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ | ||
1022 | |||
1023 | /* Bit masks for USB_TXTYPE */ | ||
1024 | |||
1025 | #define TARGET_EP_NO_T 0xf /* EP number */ | ||
1026 | #define PROTOCOL_T 0xc /* transfer type */ | ||
1027 | |||
1028 | /* Bit masks for USB_TXINTERVAL */ | ||
1029 | |||
1030 | #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ | ||
1031 | |||
1032 | /* Bit masks for USB_RXTYPE */ | ||
1033 | |||
1034 | #define TARGET_EP_NO_R 0xf /* EP number */ | ||
1035 | #define PROTOCOL_R 0xc /* transfer type */ | ||
1036 | |||
1037 | /* Bit masks for USB_RXINTERVAL */ | ||
1038 | |||
1039 | #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ | ||
1040 | |||
1041 | /* Bit masks for USB_DMA_INTERRUPT */ | ||
1042 | |||
1043 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | ||
1044 | #define nDMA0_INT 0x0 | ||
1045 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | ||
1046 | #define nDMA1_INT 0x0 | ||
1047 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | ||
1048 | #define nDMA2_INT 0x0 | ||
1049 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | ||
1050 | #define nDMA3_INT 0x0 | ||
1051 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | ||
1052 | #define nDMA4_INT 0x0 | ||
1053 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | ||
1054 | #define nDMA5_INT 0x0 | ||
1055 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | ||
1056 | #define nDMA6_INT 0x0 | ||
1057 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | ||
1058 | #define nDMA7_INT 0x0 | ||
1059 | |||
1060 | /* Bit masks for USB_DMAxCONTROL */ | ||
1061 | |||
1062 | #define DMA_ENA 0x1 /* DMA enable */ | ||
1063 | #define nDMA_ENA 0x0 | ||
1064 | #define DIRECTION 0x2 /* direction of DMA transfer */ | ||
1065 | #define nDIRECTION 0x0 | ||
1066 | #define MODE 0x4 /* DMA Bus error */ | ||
1067 | #define nMODE 0x0 | ||
1068 | #define INT_ENA 0x8 /* Interrupt enable */ | ||
1069 | #define nINT_ENA 0x0 | ||
1070 | #define EPNUM 0xf0 /* EP number */ | ||
1071 | #define BUSERROR 0x100 /* DMA Bus error */ | ||
1072 | #define nBUSERROR 0x0 | ||
1073 | |||
1074 | /* Bit masks for USB_DMAxADDRHIGH */ | ||
1075 | |||
1076 | #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ | ||
1077 | |||
1078 | /* Bit masks for USB_DMAxADDRLOW */ | ||
1079 | |||
1080 | #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ | ||
1081 | |||
1082 | /* Bit masks for USB_DMAxCOUNTHIGH */ | ||
1083 | |||
1084 | #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ | ||
1085 | |||
1086 | /* Bit masks for USB_DMAxCOUNTLOW */ | ||
1087 | |||
1088 | #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ | ||
1089 | |||
1090 | #endif /* _DEF_BF527_H */ | ||