diff options
author | Bernd Schmidt <bernd.schmidt@analog.com> | 2007-07-12 04:25:29 -0400 |
---|---|---|
committer | Bryan Wu <bryan.wu@analog.com> | 2007-07-12 04:25:29 -0400 |
commit | 29440a2b4cd37e32dfe0fa60ef1665775b24dab1 (patch) | |
tree | 1b7bd1c1793feba0719f04de2eb68e418498e827 /include/asm-blackfin/cplbinit.h | |
parent | 474f1a667d4bd40b6dcacc6870b70f4d2ba4e155 (diff) |
Blackfin arch: Start untangling the CPLB handling code.
- Move cache initialization to C from assembly.
- Move anomaly workaround for writing [ID]MEM_CONTROL to assembly, so
that we don't have to mess around with .align directives in C source.
- Fix a bug where bfin_write_DMEM_CONTROL would write to IMEM_CONTROL
- Break out CPLB related code from kernel/setup.c into their own file.
- Don't define variables in header files, only declare them.
Signed-off-by: Bernd Schmidt <bernd.schmidt@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/cplbinit.h')
-rw-r--r-- | include/asm-blackfin/cplbinit.h | 133 |
1 files changed, 13 insertions, 120 deletions
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h index e14ea397cdbb..bec6ecdf1bdb 100644 --- a/include/asm-blackfin/cplbinit.h +++ b/include/asm-blackfin/cplbinit.h | |||
@@ -57,8 +57,8 @@ struct cplb_tab { | |||
57 | u16 size; | 57 | u16 size; |
58 | }; | 58 | }; |
59 | 59 | ||
60 | u_long icplb_table[MAX_CPLBS+1]; | 60 | extern u_long icplb_table[MAX_CPLBS+1]; |
61 | u_long dcplb_table[MAX_CPLBS+1]; | 61 | extern u_long dcplb_table[MAX_CPLBS+1]; |
62 | 62 | ||
63 | /* Till here we are discussing about the static memory management model. | 63 | /* Till here we are discussing about the static memory management model. |
64 | * However, the operating envoronments commonly define more CPLB | 64 | * However, the operating envoronments commonly define more CPLB |
@@ -70,134 +70,27 @@ u_long dcplb_table[MAX_CPLBS+1]; | |||
70 | */ | 70 | */ |
71 | 71 | ||
72 | #ifdef CONFIG_CPLB_SWITCH_TAB_L1 | 72 | #ifdef CONFIG_CPLB_SWITCH_TAB_L1 |
73 | u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); | 73 | extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); |
74 | u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); | 74 | extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); |
75 | 75 | ||
76 | #ifdef CONFIG_CPLB_INFO | 76 | #ifdef CONFIG_CPLB_INFO |
77 | u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); | 77 | extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); |
78 | u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); | 78 | extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); |
79 | #endif /* CONFIG_CPLB_INFO */ | 79 | #endif /* CONFIG_CPLB_INFO */ |
80 | 80 | ||
81 | #else | 81 | #else |
82 | 82 | ||
83 | u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; | 83 | extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; |
84 | u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; | 84 | extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; |
85 | 85 | ||
86 | #ifdef CONFIG_CPLB_INFO | 86 | #ifdef CONFIG_CPLB_INFO |
87 | u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; | 87 | extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; |
88 | u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; | 88 | extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; |
89 | #endif /* CONFIG_CPLB_INFO */ | 89 | #endif /* CONFIG_CPLB_INFO */ |
90 | 90 | ||
91 | #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/ | 91 | #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/ |
92 | 92 | ||
93 | struct s_cplb { | 93 | extern unsigned long reserved_mem_dcache_on; |
94 | struct cplb_tab init_i; | 94 | extern unsigned long reserved_mem_icache_on; |
95 | struct cplb_tab init_d; | ||
96 | struct cplb_tab switch_i; | ||
97 | struct cplb_tab switch_d; | ||
98 | }; | ||
99 | 95 | ||
100 | #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) | 96 | extern void generate_cpl_tables(void); |
101 | static struct cplb_desc cplb_data[] = { | ||
102 | { | ||
103 | .start = 0, | ||
104 | .end = SIZE_1K, | ||
105 | .psize = SIZE_1K, | ||
106 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, | ||
107 | .i_conf = SDRAM_OOPS, | ||
108 | .d_conf = SDRAM_OOPS, | ||
109 | #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO) | ||
110 | .valid = 1, | ||
111 | #else | ||
112 | .valid = 0, | ||
113 | #endif | ||
114 | .name = "ZERO Pointer Saveguard", | ||
115 | }, | ||
116 | { | ||
117 | .start = L1_CODE_START, | ||
118 | .end = L1_CODE_START + L1_CODE_LENGTH, | ||
119 | .psize = SIZE_4M, | ||
120 | .attr = INITIAL_T | SWITCH_T | I_CPLB, | ||
121 | .i_conf = L1_IMEMORY, | ||
122 | .d_conf = 0, | ||
123 | .valid = 1, | ||
124 | .name = "L1 I-Memory", | ||
125 | }, | ||
126 | { | ||
127 | .start = L1_DATA_A_START, | ||
128 | .end = L1_DATA_B_START + L1_DATA_B_LENGTH, | ||
129 | .psize = SIZE_4M, | ||
130 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | ||
131 | .i_conf = 0, | ||
132 | .d_conf = L1_DMEMORY, | ||
133 | #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0)) | ||
134 | .valid = 1, | ||
135 | #else | ||
136 | .valid = 0, | ||
137 | #endif | ||
138 | .name = "L1 D-Memory", | ||
139 | }, | ||
140 | { | ||
141 | .start = 0, | ||
142 | .end = 0, /* dynamic */ | ||
143 | .psize = 0, | ||
144 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, | ||
145 | .i_conf = SDRAM_IGENERIC, | ||
146 | .d_conf = SDRAM_DGENERIC, | ||
147 | .valid = 1, | ||
148 | .name = "SDRAM Kernel", | ||
149 | }, | ||
150 | { | ||
151 | .start = 0, /* dynamic */ | ||
152 | .end = 0, /* dynamic */ | ||
153 | .psize = 0, | ||
154 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | ||
155 | .i_conf = SDRAM_IGENERIC, | ||
156 | .d_conf = SDRAM_DNON_CHBL, | ||
157 | .valid = 1, | ||
158 | .name = "SDRAM RAM MTD", | ||
159 | }, | ||
160 | { | ||
161 | .start = 0, /* dynamic */ | ||
162 | .end = 0, /* dynamic */ | ||
163 | .psize = SIZE_1M, | ||
164 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | ||
165 | .d_conf = SDRAM_DNON_CHBL, | ||
166 | .valid = 1,//(DMA_UNCACHED_REGION > 0), | ||
167 | .name = "SDRAM Uncached DMA ZONE", | ||
168 | }, | ||
169 | { | ||
170 | .start = 0, /* dynamic */ | ||
171 | .end = 0, /* dynamic */ | ||
172 | .psize = 0, | ||
173 | .attr = SWITCH_T | D_CPLB, | ||
174 | .i_conf = 0, /* dynamic */ | ||
175 | .d_conf = 0, /* dynamic */ | ||
176 | .valid = 1, | ||
177 | .name = "SDRAM Reserved Memory", | ||
178 | }, | ||
179 | { | ||
180 | .start = ASYNC_BANK0_BASE, | ||
181 | .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE, | ||
182 | .psize = 0, | ||
183 | .attr = SWITCH_T | D_CPLB, | ||
184 | .d_conf = SDRAM_EBIU, | ||
185 | .valid = 1, | ||
186 | .name = "ASYNC Memory", | ||
187 | }, | ||
188 | { | ||
189 | #if defined(CONFIG_BF561) | ||
190 | .start = L2_SRAM, | ||
191 | .end = L2_SRAM_END, | ||
192 | .psize = SIZE_1M, | ||
193 | .attr = SWITCH_T | D_CPLB, | ||
194 | .i_conf = L2_MEMORY, | ||
195 | .d_conf = L2_MEMORY, | ||
196 | .valid = 1, | ||
197 | #else | ||
198 | .valid = 0, | ||
199 | #endif | ||
200 | .name = "L2 Memory", | ||
201 | } | ||
202 | }; | ||
203 | #endif | ||