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authorLinus Torvalds <torvalds@linux-foundation.org>2008-08-28 15:34:01 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-08-28 15:34:01 -0400
commit604a2785a8482cad4d63202465133c720db5eda7 (patch)
treee2f510a8a54d7d4443cb52f3a0be46f527ebb779 /include/asm-blackfin/cache.h
parent66833d5f3934a19d0988b7d0de58149bfd7a5884 (diff)
parentd310fb4bb73629840430cb13cb282915e49fef4b (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: Blackfin arch: Fix PM building on BF52x: No ROTWE on BF52x, add USBWE Blackfin arch: sram: use 'unsigned long' for irqflags Blackfin arch: let PCI depend on BROKEN Blackfin arch: move include/asm-blackfin header files to arch/blackfin Blackfin arch: fix bug - MPU crashes under stress Blackfin arch: Fix bug - when to rmmod the L1_module, it stucks and then reboot the board. Blackfin arch: dont actually need to muck with EMAC_SYSTAT for BF52x for demuxing Blackfin arch: Add MTD Partitions for MTD_DATAFLASH, increase max SPI SCLK
Diffstat (limited to 'include/asm-blackfin/cache.h')
-rw-r--r--include/asm-blackfin/cache.h29
1 files changed, 0 insertions, 29 deletions
diff --git a/include/asm-blackfin/cache.h b/include/asm-blackfin/cache.h
deleted file mode 100644
index 023d72133b5a..000000000000
--- a/include/asm-blackfin/cache.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * include/asm-blackfin/cache.h
3 */
4#ifndef __ARCH_BLACKFIN_CACHE_H
5#define __ARCH_BLACKFIN_CACHE_H
6
7/*
8 * Bytes per L1 cache line
9 * Blackfin loads 32 bytes for cache
10 */
11#define L1_CACHE_SHIFT 5
12#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
13#define SMP_CACHE_BYTES L1_CACHE_BYTES
14
15/*
16 * Put cacheline_aliged data to L1 data memory
17 */
18#ifdef CONFIG_CACHELINE_ALIGNED_L1
19#define __cacheline_aligned \
20 __attribute__((__aligned__(L1_CACHE_BYTES), \
21 __section__(".data_l1.cacheline_aligned")))
22#endif
23
24/*
25 * largest L1 which this arch supports
26 */
27#define L1_CACHE_SHIFT_MAX 5
28
29#endif