[PATCH] avr32 architecture

This adds support for the Atmel AVR32 architecture as well as the AT32AP7000
CPU and the AT32STK1000 development board.

AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for
cost-sensitive embedded applications, with particular emphasis on low power
consumption and high code density.  The AVR32 architecture is not binary
compatible with earlier 8-bit AVR architectures.

The AVR32 architecture, including the instruction set, is described by the
AVR32 Architecture Manual, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf

The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture.  It
features a 7-stage pipeline, 16KB instruction and data caches and a full
Memory Management Unit.  It also comes with a large set of integrated
peripherals, many of which are shared with the AT91 ARM-based controllers from
Atmel.

Full data sheet is available from

http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf

while the CPU core implementation including caches and MMU is documented by
the AVR32 AP Technical Reference, available from

http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf

Information about the AT32STK1000 development board can be found at

http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918

including a BSP CD image with an earlier version of this patch, development
tools (binaries and source/patches) and a root filesystem image suitable for
booting from SD card.

Alternatively, there's a preliminary "getting started" guide available at
http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links
to the sources and patches you will need in order to set up a cross-compiling
environment for avr32-linux.

This patch, as well as the other patches included with the BSP and the
toolchain patches, is actively supported by Atmel Corporation.

[dmccr@us.ibm.com: Fix more pxx_page macro locations]
[bunk@stusta.de: fix `make defconfig']
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 154 insertions, 0 deletions

diff --git a/include/asm-avr32/ptrace.h b/include/asm-avr32/ptrace.h
new file mode 100644
index 000000000000..60f0f19a81f1
--- /dev/null
+++ b/include/asm-avr32/ptrace.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_AVR32_PTRACE_H
+#define __ASM_AVR32_PTRACE_H
+
+#define PTRACE_GETREGS          12
+#define PTRACE_SETREGS          13
+
+/*
+ * Status Register bits
+ */
+#define SR_H            0x40000000
+#define SR_R            0x20000000
+#define SR_J            0x10000000
+#define SR_DM           0x08000000
+#define SR_D            0x04000000
+#define MODE_NMI        0x01c00000
+#define MODE_EXCEPTION  0x01800000
+#define MODE_INT3       0x01400000
+#define MODE_INT2       0x01000000
+#define MODE_INT1       0x00c00000
+#define MODE_INT0       0x00800000
+#define MODE_SUPERVISOR 0x00400000
+#define MODE_USER       0x00000000
+#define MODE_MASK       0x01c00000
+#define SR_EM           0x00200000
+#define SR_I3M          0x00100000
+#define SR_I2M          0x00080000
+#define SR_I1M          0x00040000
+#define SR_I0M          0x00020000
+#define SR_GM           0x00010000
+
+#define SR_H_BIT        30
+#define SR_R_BIT        29
+#define SR_J_BIT        28
+#define SR_DM_BIT       27
+#define SR_D_BIT        26
+#define MODE_SHIFT      22
+#define SR_EM_BIT       21
+#define SR_I3M_BIT      20
+#define SR_I2M_BIT      19
+#define SR_I1M_BIT      18
+#define SR_I0M_BIT      17
+#define SR_GM_BIT       16
+
+/* The user-visible part */
+#define SR_L            0x00000020
+#define SR_Q            0x00000010
+#define SR_V            0x00000008
+#define SR_N            0x00000004
+#define SR_Z            0x00000002
+#define SR_C            0x00000001
+
+#define SR_L_BIT        5
+#define SR_Q_BIT        4
+#define SR_V_BIT        3
+#define SR_N_BIT        2
+#define SR_Z_BIT        1
+#define SR_C_BIT        0
+
+/*
+ * The order is defined by the stmts instruction. r0 is stored first,
+ * so it gets the highest address.
+ *
+ * Registers 0-12 are general-purpose registers (r12 is normally used for
+ * the function return value).
+ * Register 13 is the stack pointer
+ * Register 14 is the link register
+ * Register 15 is the program counter (retrieved from the RAR sysreg)
+ */
+#define FRAME_SIZE_FULL 72
+#define REG_R12_ORIG    68
+#define REG_R0          64
+#define REG_R1          60
+#define REG_R2          56
+#define REG_R3          52
+#define REG_R4          48
+#define REG_R5          44
+#define REG_R6          40
+#define REG_R7          36
+#define REG_R8          32
+#define REG_R9          28
+#define REG_R10         24
+#define REG_R11         20
+#define REG_R12         16
+#define REG_SP          12
+#define REG_LR           8
+
+#define FRAME_SIZE_MIN   8
+#define REG_PC           4
+#define REG_SR           0
+
+#ifndef __ASSEMBLY__
+struct pt_regs {
+        /* These are always saved */
+        unsigned long sr;
+        unsigned long pc;
+
+        /* These are sometimes saved */
+        unsigned long lr;
+        unsigned long sp;
+        unsigned long r12;
+        unsigned long r11;
+        unsigned long r10;
+        unsigned long r9;
+        unsigned long r8;
+        unsigned long r7;
+        unsigned long r6;
+        unsigned long r5;
+        unsigned long r4;
+        unsigned long r3;
+        unsigned long r2;
+        unsigned long r1;
+        unsigned long r0;
+
+        /* Only saved on system call */
+        unsigned long r12_orig;
+};
+
+#ifdef __KERNEL__
+# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
+extern void show_regs (struct pt_regs *);
+
+static __inline__ int valid_user_regs(struct pt_regs *regs)
+{
+        /*
+         * Some of the Java bits might be acceptable if/when we
+         * implement some support for that stuff...
+         */
+        if ((regs->sr & 0xffff0000) == 0)
+                return 1;
+
+        /*
+         * Force status register flags to be sane and report this
+         * illegal behaviour...
+         */
+        regs->sr &= 0x0000ffff;
+        return 0;
+}
+
+#define instruction_pointer(regs) ((regs)->pc)
+
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif /* __KERNEL__ */
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_PTRACE_H */