[ARM] Orion: distinguish between physical and virtual addresses

Hack up the Orion port to distinguish between virtual and physical
addresses of register windows.  This will allow moving virtual
mappings higher up in the address space, to free up more kernel
virtual address space.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

5 files changed, 78 insertions, 54 deletions

diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S
index e2a80641f214..2746220f5d85 100644
--- a/include/asm-arm/arch-orion/debug-macro.S
+++ b/include/asm-arm/arch-orion/debug-macro.S
@@ -8,9 +8,14 @@
  * published by the Free Software Foundation.
 */
 
+#include <asm/arch/orion.h>
+
         .macro  addruart,rx
-        mov   \rx, #0xf1000000
-        orr   \rx, \rx, #0x00012000
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =ORION_REGS_PHYS_BASE
+        ldrne   \rx, =ORION_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
         .endm
 
 #define UART_SHIFT      2
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S
index b76075a7e44b..cda096b2acfd 100644
--- a/include/asm-arm/arch-orion/entry-macro.S
+++ b/include/asm-arm/arch-orion/entry-macro.S
@@ -3,8 +3,8 @@
  *
  * Low-level IRQ helper macros for Orion platforms
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h
index 8a12d213fbdc..65da374de735 100644
--- a/include/asm-arm/arch-orion/hardware.h
+++ b/include/asm-arm/arch-orion/hardware.h
@@ -4,7 +4,6 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
  */
 
 #ifndef __ASM_ARCH_HARDWARE_H__
@@ -12,13 +11,11 @@
 
 #include "orion.h"
 
-#define PCI_MEMORY_VADDR        ORION_PCI_SYS_MEM_BASE
-#define PCI_IO_VADDR            ORION_PCI_SYS_IO_BASE
+#define pcibios_assign_all_busses()     1
 
-#define pcibios_assign_all_busses()  1
+#define PCIBIOS_MIN_IO          0x00001000
+#define PCIBIOS_MIN_MEM         0x01000000
+#define PCIMEM_BASE             ORION_PCIE_MEM_PHYS_BASE
 
-#define PCIBIOS_MIN_IO  0x1000
-#define PCIBIOS_MIN_MEM 0x01000000
-#define PCIMEM_BASE     PCI_MEMORY_VADDR /* mem base for VGA */
 
-#endif  /* _ASM_ARCH_HARDWARE_H */
+#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
index f787f752e58c..4a8025466a33 100644
--- a/include/asm-arm/arch-orion/orion.h
+++ b/include/asm-arm/arch-orion/orion.h
@@ -14,32 +14,40 @@
 #ifndef __ASM_ARCH_ORION_H__
 #define __ASM_ARCH_ORION_H__
 
-/*******************************************************************************
+/*****************************************************************************
  * Orion Address Map
- * Use the same mapping (1:1 virtual:physical) of internal registers and
- * PCI system (PCI+PCIE) for all machines.
- * Each machine defines the rest of its mapping (e.g. device bus flashes)
- ******************************************************************************/
-#define ORION_REGS_BASE         0xf1000000
+ *
+ * virt         phys            size
+ * f0000000     f0000000        16M     PCIe WA space (Orion-NAS only)
+ * f1000000     f1000000        1M      on-chip peripheral registers
+ * f2000000     f2000000        1M      PCIe I/O space
+ * f2100000     f2100000        1M      PCI I/O space
+ ****************************************************************************/
+#define ORION_REGS_PHYS_BASE    0xf1000000
+#define ORION_REGS_VIRT_BASE    0xf1000000
 #define ORION_REGS_SIZE         SZ_1M
 
-#define ORION_PCI_SYS_MEM_BASE  0xe0000000
-#define ORION_PCIE_MEM_BASE     ORION_PCI_SYS_MEM_BASE
-#define ORION_PCIE_MEM_SIZE     SZ_128M
-#define ORION_PCI_MEM_BASE      (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
-#define ORION_PCI_MEM_SIZE      SZ_128M
-
-#define ORION_PCI_SYS_IO_BASE   0xf2000000
-#define ORION_PCIE_IO_BASE      ORION_PCI_SYS_IO_BASE
+#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
+#define ORION_PCIE_IO_VIRT_BASE 0xf2000000
+#define ORION_PCIE_IO_BUS_BASE  0x00000000
 #define ORION_PCIE_IO_SIZE      SZ_1M
-#define ORION_PCIE_IO_REMAP     (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
-#define ORION_PCI_IO_BASE       (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
+
+#define ORION_PCI_IO_PHYS_BASE  0xf2100000
+#define ORION_PCI_IO_VIRT_BASE  0xf2100000
+#define ORION_PCI_IO_BUS_BASE   0x00100000
 #define ORION_PCI_IO_SIZE       SZ_1M
-#define ORION_PCI_IO_REMAP      (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
+
 /* Relevant only for Orion-NAS */
-#define ORION_PCIE_WA_BASE      0xf0000000
+#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
+#define ORION_PCIE_WA_VIRT_BASE 0xf0000000
 #define ORION_PCIE_WA_SIZE      SZ_16M
 
+#define ORION_PCIE_MEM_PHYS_BASE        0xe0000000
+#define ORION_PCIE_MEM_SIZE             SZ_128M
+
+#define ORION_PCI_MEM_PHYS_BASE         0xe8000000
+#define ORION_PCI_MEM_SIZE              SZ_128M
+
 /*******************************************************************************
  * Supported Devices & Revisions
  ******************************************************************************/
@@ -57,25 +65,42 @@
 /*******************************************************************************
  * Orion Registers Map
  ******************************************************************************/
-#define ORION_DDR_REG_BASE      (ORION_REGS_BASE | 0x00000)
-#define ORION_DEV_BUS_REG_BASE  (ORION_REGS_BASE | 0x10000)
-#define ORION_BRIDGE_REG_BASE   (ORION_REGS_BASE | 0x20000)
-#define ORION_PCI_REG_BASE      (ORION_REGS_BASE | 0x30000)
-#define ORION_PCIE_REG_BASE     (ORION_REGS_BASE | 0x40000)
-#define ORION_USB0_REG_BASE     (ORION_REGS_BASE | 0x50000)
-#define ORION_ETH_REG_BASE      (ORION_REGS_BASE | 0x70000)
-#define ORION_SATA_REG_BASE     (ORION_REGS_BASE | 0x80000)
-#define ORION_USB1_REG_BASE     (ORION_REGS_BASE | 0xa0000)
-
-#define ORION_DDR_REG(x)        (ORION_DDR_REG_BASE | (x))
-#define ORION_DEV_BUS_REG(x)    (ORION_DEV_BUS_REG_BASE | (x))
-#define ORION_BRIDGE_REG(x)     (ORION_BRIDGE_REG_BASE | (x))
-#define ORION_PCI_REG(x)        (ORION_PCI_REG_BASE | (x))
-#define ORION_PCIE_REG(x)       (ORION_PCIE_REG_BASE | (x))
-#define ORION_USB0_REG(x)       (ORION_USB0_REG_BASE | (x))
-#define ORION_USB1_REG(x)       (ORION_USB1_REG_BASE | (x))
-#define ORION_ETH_REG(x)        (ORION_ETH_REG_BASE | (x))
-#define ORION_SATA_REG(x)       (ORION_SATA_REG_BASE | (x))
+#define ORION_DDR_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x00000)
+#define ORION_DDR_REG(x)                (ORION_DDR_VIRT_BASE | (x))
+
+#define ORION_DEV_BUS_PHYS_BASE         (ORION_REGS_PHYS_BASE | 0x10000)
+#define ORION_DEV_BUS_VIRT_BASE         (ORION_REGS_VIRT_BASE | 0x10000)
+#define ORION_DEV_BUS_REG(x)            (ORION_DEV_BUS_VIRT_BASE | (x))
+#define  I2C_PHYS_BASE                  (ORION_DEV_BUS_PHYS_BASE | 0x1000)
+#define  UART0_PHYS_BASE                (ORION_DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE                (ORION_DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE                (ORION_DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE                (ORION_DEV_BUS_VIRT_BASE | 0x2100)
+
+#define ORION_BRIDGE_VIRT_BASE          (ORION_REGS_VIRT_BASE | 0x20000)
+#define ORION_BRIDGE_REG(x)             (ORION_BRIDGE_VIRT_BASE | (x))
+
+#define ORION_PCI_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x30000)
+#define ORION_PCI_REG(x)                (ORION_PCI_VIRT_BASE | (x))
+
+#define ORION_PCIE_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x40000)
+#define ORION_PCIE_REG(x)               (ORION_PCIE_VIRT_BASE | (x))
+
+#define ORION_USB0_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0x50000)
+#define ORION_USB0_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x50000)
+#define ORION_USB0_REG(x)               (ORION_USB0_VIRT_BASE | (x))
+
+#define ORION_ETH_PHYS_BASE             (ORION_REGS_PHYS_BASE | 0x70000)
+#define ORION_ETH_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x70000)
+#define ORION_ETH_REG(x)                (ORION_ETH_VIRT_BASE | (x))
+
+#define ORION_SATA_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0x80000)
+#define ORION_SATA_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x80000)
+#define ORION_SATA_REG(x)               (ORION_SATA_VIRT_BASE | (x))
+
+#define ORION_USB1_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0xa0000)
+#define ORION_USB1_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0xa0000)
+#define ORION_USB1_REG(x)               (ORION_USB1_VIRT_BASE | (x))
 
 /*******************************************************************************
  * Device Bus Registers
@@ -100,9 +125,6 @@
 #define DEV_BUS_CTRL            ORION_DEV_BUS_REG(0x4c0)
 #define DEV_BUS_INT_CAUSE       ORION_DEV_BUS_REG(0x4d0)
 #define DEV_BUS_INT_MASK        ORION_DEV_BUS_REG(0x4d4)
-#define I2C_BASE                ORION_DEV_BUS_REG(0x1000)
-#define UART0_BASE              ORION_DEV_BUS_REG(0x2000)
-#define UART1_BASE              ORION_DEV_BUS_REG(0x2100)
 #define GPIO_MAX                32
 
 /***************************************************************************
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h
index 0cab78ad6332..59f44039909a 100644
--- a/include/asm-arm/arch-orion/uncompress.h
+++ b/include/asm-arm/arch-orion/uncompress.h
@@ -10,8 +10,8 @@
 
 #include <asm/arch/orion.h>
 
-#define MV_UART_LSR     ((volatile unsigned char *)(UART0_BASE + 0x14))
-#define MV_UART_THR     ((volatile unsigned char *)(UART0_BASE + 0x0))
+#define MV_UART_THR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
+#define MV_UART_LSR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
 
 #define LSR_THRE        0x20