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authorBen Dooks <ben-linux@fluff.org>2007-07-22 11:18:22 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-22 11:44:39 -0400
commitae39ae0b0030d7f96a6b7b06d9c77c8ad2a07673 (patch)
tree2bd9a8527ca4cd4acb5b7bef8eccd7d1cb2094b8 /include/asm-arm
parenta45f82616eaa7e7fcd365ced78d3f0974b991800 (diff)
[ARM] 4519/1: S3C: split S3C2400 values out of S3C24XX map.h
Move the S3C2400 values to their own include directory series in include/asm-arm/arch-s3c2400 as the support for the S3C2400 is best placed in its own arch directory. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-s3c2400/map.h66
-rw-r--r--include/asm-arm/arch-s3c2410/map.h51
2 files changed, 66 insertions, 51 deletions
diff --git a/include/asm-arm/arch-s3c2400/map.h b/include/asm-arm/arch-s3c2400/map.h
new file mode 100644
index 000000000000..1184d907b31e
--- /dev/null
+++ b/include/asm-arm/arch-s3c2400/map.h
@@ -0,0 +1,66 @@
1/* linux/include/asm-arm/arch-s3c2400/map.h
2 *
3 * Copyright 2003,2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Copyright 2003, Lucas Correia Villa Real
8 *
9 * S3C2400 - Memory map definitions
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#define S3C2400_PA_MEMCTRL (0x14000000)
17#define S3C2400_PA_USBHOST (0x14200000)
18#define S3C2400_PA_IRQ (0x14400000)
19#define S3C2400_PA_DMA (0x14600000)
20#define S3C2400_PA_CLKPWR (0x14800000)
21#define S3C2400_PA_LCD (0x14A00000)
22#define S3C2400_PA_UART (0x15000000)
23#define S3C2400_PA_TIMER (0x15100000)
24#define S3C2400_PA_USBDEV (0x15200140)
25#define S3C2400_PA_WATCHDOG (0x15300000)
26#define S3C2400_PA_IIC (0x15400000)
27#define S3C2400_PA_IIS (0x15508000)
28#define S3C2400_PA_GPIO (0x15600000)
29#define S3C2400_PA_RTC (0x15700040)
30#define S3C2400_PA_ADC (0x15800000)
31#define S3C2400_PA_SPI (0x15900000)
32
33#define S3C2400_PA_MMC (0x15A00000)
34#define S3C2400_SZ_MMC SZ_1M
35
36/* physical addresses of all the chip-select areas */
37
38#define S3C2400_CS0 (0x00000000)
39#define S3C2400_CS1 (0x02000000)
40#define S3C2400_CS2 (0x04000000)
41#define S3C2400_CS3 (0x06000000)
42#define S3C2400_CS4 (0x08000000)
43#define S3C2400_CS5 (0x0A000000)
44#define S3C2400_CS6 (0x0C000000)
45#define S3C2400_CS7 (0x0E000000)
46
47#define S3C2400_SDRAM_PA (S3C2400_CS6)
48
49/* Use a single interface for common resources between S3C24XX cpus */
50
51#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
52#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
53#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
54#define S3C24XX_PA_DMA S3C2400_PA_DMA
55#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
56#define S3C24XX_PA_LCD S3C2400_PA_LCD
57#define S3C24XX_PA_UART S3C2400_PA_UART
58#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
59#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
60#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
61#define S3C24XX_PA_IIC S3C2400_PA_IIC
62#define S3C24XX_PA_IIS S3C2400_PA_IIS
63#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
64#define S3C24XX_PA_RTC S3C2400_PA_RTC
65#define S3C24XX_PA_ADC S3C2400_PA_ADC
66#define S3C24XX_PA_SPI S3C2400_PA_SPI
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 19e77f038042..bec267b1d212 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -30,41 +30,33 @@
30#define S3C2410_ADDR(x) (0xF0000000 + (x)) 30#define S3C2410_ADDR(x) (0xF0000000 + (x))
31#endif 31#endif
32 32
33#define S3C2400_ADDR(x) S3C2410_ADDR(x)
34
35/* interrupt controller is the first thing we put in, to make 33/* interrupt controller is the first thing we put in, to make
36 * the assembly code for the irq detection easier 34 * the assembly code for the irq detection easier
37 */ 35 */
38#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000) 36#define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000)
39#define S3C2400_PA_IRQ (0x14400000)
40#define S3C2410_PA_IRQ (0x4A000000) 37#define S3C2410_PA_IRQ (0x4A000000)
41#define S3C24XX_SZ_IRQ SZ_1M 38#define S3C24XX_SZ_IRQ SZ_1M
42 39
43/* memory controller registers */ 40/* memory controller registers */
44#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000) 41#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
45#define S3C2400_PA_MEMCTRL (0x14000000)
46#define S3C2410_PA_MEMCTRL (0x48000000) 42#define S3C2410_PA_MEMCTRL (0x48000000)
47#define S3C24XX_SZ_MEMCTRL SZ_1M 43#define S3C24XX_SZ_MEMCTRL SZ_1M
48 44
49/* USB host controller */ 45/* USB host controller */
50#define S3C2400_PA_USBHOST (0x14200000)
51#define S3C2410_PA_USBHOST (0x49000000) 46#define S3C2410_PA_USBHOST (0x49000000)
52#define S3C24XX_SZ_USBHOST SZ_1M 47#define S3C24XX_SZ_USBHOST SZ_1M
53 48
54/* DMA controller */ 49/* DMA controller */
55#define S3C2400_PA_DMA (0x14600000)
56#define S3C2410_PA_DMA (0x4B000000) 50#define S3C2410_PA_DMA (0x4B000000)
57#define S3C24XX_SZ_DMA SZ_1M 51#define S3C24XX_SZ_DMA SZ_1M
58 52
59/* Clock and Power management */ 53/* Clock and Power management */
60#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000) 54#define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000)
61#define S3C2400_PA_CLKPWR (0x14800000)
62#define S3C2410_PA_CLKPWR (0x4C000000) 55#define S3C2410_PA_CLKPWR (0x4C000000)
63#define S3C24XX_SZ_CLKPWR SZ_1M 56#define S3C24XX_SZ_CLKPWR SZ_1M
64 57
65/* LCD controller */ 58/* LCD controller */
66#define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000) 59#define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000)
67#define S3C2400_PA_LCD (0x14A00000)
68#define S3C2410_PA_LCD (0x4D000000) 60#define S3C2410_PA_LCD (0x4D000000)
69#define S3C24XX_SZ_LCD SZ_1M 61#define S3C24XX_SZ_LCD SZ_1M
70 62
@@ -72,41 +64,31 @@
72#define S3C2410_PA_NAND (0x4E000000) 64#define S3C2410_PA_NAND (0x4E000000)
73#define S3C24XX_SZ_NAND SZ_1M 65#define S3C24XX_SZ_NAND SZ_1M
74 66
75/* MMC controller - available on the S3C2400 */
76#define S3C2400_PA_MMC (0x15A00000)
77#define S3C2400_SZ_MMC SZ_1M
78
79/* UARTs */ 67/* UARTs */
80#define S3C24XX_VA_UART S3C2410_ADDR(0x00400000) 68#define S3C24XX_VA_UART S3C2410_ADDR(0x00400000)
81#define S3C2400_PA_UART (0x15000000)
82#define S3C2410_PA_UART (0x50000000) 69#define S3C2410_PA_UART (0x50000000)
83#define S3C24XX_SZ_UART SZ_1M 70#define S3C24XX_SZ_UART SZ_1M
84 71
85/* Timers */ 72/* Timers */
86#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000) 73#define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000)
87#define S3C2400_PA_TIMER (0x15100000)
88#define S3C2410_PA_TIMER (0x51000000) 74#define S3C2410_PA_TIMER (0x51000000)
89#define S3C24XX_SZ_TIMER SZ_1M 75#define S3C24XX_SZ_TIMER SZ_1M
90 76
91/* USB Device port */ 77/* USB Device port */
92#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000) 78#define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000)
93#define S3C2400_PA_USBDEV (0x15200140)
94#define S3C2410_PA_USBDEV (0x52000000) 79#define S3C2410_PA_USBDEV (0x52000000)
95#define S3C24XX_SZ_USBDEV SZ_1M 80#define S3C24XX_SZ_USBDEV SZ_1M
96 81
97/* Watchdog */ 82/* Watchdog */
98#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000) 83#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
99#define S3C2400_PA_WATCHDOG (0x15300000)
100#define S3C2410_PA_WATCHDOG (0x53000000) 84#define S3C2410_PA_WATCHDOG (0x53000000)
101#define S3C24XX_SZ_WATCHDOG SZ_1M 85#define S3C24XX_SZ_WATCHDOG SZ_1M
102 86
103/* IIC hardware controller */ 87/* IIC hardware controller */
104#define S3C2400_PA_IIC (0x15400000)
105#define S3C2410_PA_IIC (0x54000000) 88#define S3C2410_PA_IIC (0x54000000)
106#define S3C24XX_SZ_IIC SZ_1M 89#define S3C24XX_SZ_IIC SZ_1M
107 90
108/* IIS controller */ 91/* IIS controller */
109#define S3C2400_PA_IIS (0x15508000)
110#define S3C2410_PA_IIS (0x55000000) 92#define S3C2410_PA_IIS (0x55000000)
111#define S3C24XX_SZ_IIS SZ_1M 93#define S3C24XX_SZ_IIS SZ_1M
112 94
@@ -120,23 +102,19 @@
120 * by the base system. 102 * by the base system.
121*/ 103*/
122 104
123#define S3C2400_PA_GPIO (0x15600000)
124#define S3C2410_PA_GPIO (0x56000000) 105#define S3C2410_PA_GPIO (0x56000000)
125#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) 106#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
126#define S3C24XX_SZ_GPIO SZ_1M 107#define S3C24XX_SZ_GPIO SZ_1M
127 108
128/* RTC */ 109/* RTC */
129#define S3C2400_PA_RTC (0x15700040)
130#define S3C2410_PA_RTC (0x57000000) 110#define S3C2410_PA_RTC (0x57000000)
131#define S3C24XX_SZ_RTC SZ_1M 111#define S3C24XX_SZ_RTC SZ_1M
132 112
133/* ADC */ 113/* ADC */
134#define S3C2400_PA_ADC (0x15800000)
135#define S3C2410_PA_ADC (0x58000000) 114#define S3C2410_PA_ADC (0x58000000)
136#define S3C24XX_SZ_ADC SZ_1M 115#define S3C24XX_SZ_ADC SZ_1M
137 116
138/* SPI */ 117/* SPI */
139#define S3C2400_PA_SPI (0x15900000)
140#define S3C2410_PA_SPI (0x59000000) 118#define S3C2410_PA_SPI (0x59000000)
141#define S3C24XX_SZ_SPI SZ_1M 119#define S3C24XX_SZ_SPI SZ_1M
142 120
@@ -177,37 +155,9 @@
177 155
178#define S3C2410_SDRAM_PA (S3C2410_CS6) 156#define S3C2410_SDRAM_PA (S3C2410_CS6)
179 157
180#define S3C2400_CS0 (0x00000000)
181#define S3C2400_CS1 (0x02000000)
182#define S3C2400_CS2 (0x04000000)
183#define S3C2400_CS3 (0x06000000)
184#define S3C2400_CS4 (0x08000000)
185#define S3C2400_CS5 (0x0A000000)
186#define S3C2400_CS6 (0x0C000000)
187#define S3C2400_CS7 (0x0E000000)
188
189#define S3C2400_SDRAM_PA (S3C2400_CS6)
190 158
191/* Use a single interface for common resources between S3C24XX cpus */ 159/* Use a single interface for common resources between S3C24XX cpus */
192 160
193#ifdef CONFIG_CPU_S3C2400
194#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
195#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
196#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
197#define S3C24XX_PA_DMA S3C2400_PA_DMA
198#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
199#define S3C24XX_PA_LCD S3C2400_PA_LCD
200#define S3C24XX_PA_UART S3C2400_PA_UART
201#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
202#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
203#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
204#define S3C24XX_PA_IIC S3C2400_PA_IIC
205#define S3C24XX_PA_IIS S3C2400_PA_IIS
206#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
207#define S3C24XX_PA_RTC S3C2400_PA_RTC
208#define S3C24XX_PA_ADC S3C2400_PA_ADC
209#define S3C24XX_PA_SPI S3C2400_PA_SPI
210#else
211#define S3C24XX_PA_IRQ S3C2410_PA_IRQ 161#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
212#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL 162#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
213#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST 163#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
@@ -224,7 +174,6 @@
224#define S3C24XX_PA_RTC S3C2410_PA_RTC 174#define S3C24XX_PA_RTC S3C2410_PA_RTC
225#define S3C24XX_PA_ADC S3C2410_PA_ADC 175#define S3C24XX_PA_ADC S3C2410_PA_ADC
226#define S3C24XX_PA_SPI S3C2410_PA_SPI 176#define S3C24XX_PA_SPI S3C2410_PA_SPI
227#endif
228 177
229/* deal with the registers that move under the 2412/2413 */ 178/* deal with the registers that move under the 2412/2413 */
230 179