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authorBen Dooks <ben-linux@fluff.org>2005-09-25 18:04:48 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-09-25 18:04:48 -0400
commit5b58745203f16ab83e50f4a015eea84c416d9279 (patch)
treedd71a7f359dfce9f58c2076ad6c54bf92b7b024d /include/asm-arm
parentef6bd6eb90ad72ee8ee7ba8b271f27102e9a90c1 (diff)
[ARM] 2934/1: Anubis - fix VA offsets for CPLD registers
Patch from Ben Dooks The VA addresses of the Anubis CPLD registers confoict with the addresses for the ISA space maps used by the rest of the s3c2410 architecture Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-s3c2410/anubis-map.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h
index 97741d6e506a..d529ffda8599 100644
--- a/include/asm-arm/arch-s3c2410/anubis-map.h
+++ b/include/asm-arm/arch-s3c2410/anubis-map.h
@@ -20,22 +20,22 @@
20 20
21/* start peripherals off after the S3C2410 */ 21/* start peripherals off after the S3C2410 */
22 22
23#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x02000000)) 23#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
24 24
25#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) 25#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
26 26
27/* we put the CPLD registers next, to get them out of the way */ 27/* we put the CPLD registers next, to get them out of the way */
28 28
29#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01300000 */ 29#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */
30#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) 30#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD)
31 31
32#define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01400000 */ 32#define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01900000 */
33#define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD) 33#define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD)
34 34
35#define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01500000 */ 35#define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01A00000 */
36#define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD) 36#define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD)
37 37
38#define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01600000 */ 38#define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */
39#define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD) 39#define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD)
40 40
41#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) 41#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)