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authorLennert Buytenhek <buytenh@wantstofly.org>2006-12-03 12:51:14 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-12-03 12:52:22 -0500
commitafe4b25e7d9260d85fccb2d13c9933a987bdfc8a (patch)
tree9b603e52ef91531089b45e5860e89d91d2e01565 /include/asm-arm
parentf5236225a3858b505221a59233af1f1158be9139 (diff)
[ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single 40 bit accumulator register), or an iWMMXt coprocessor (which contains eight 64 bit registers.) Because of the small amount of state in the DSP coprocessor, access to the DSP coprocessor (CP0) is always enabled, and DSP context switching is done unconditionally on every task switch. Access to the iWMMXt coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is first issued, and iWMMXt context switching is done lazily. CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will have iWMMXt support', but boards are supposed to select this config symbol by hand, and at least one pxa27x board doesn't get this right, so on that board, proc-xscale.S will incorrectly assume that we have a DSP coprocessor, enable CP0 on boot, and we will then only save the first iWMMXt register (wR0) on context switches, which is Bad. This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on might have iWMMXt support, and we will enable iWMMXt context switching if it does.' This means that with this patch, running a CONFIG_IWMMXT=n kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt state over context switches, and running a CONFIG_IWMMXT=y kernel on a non-iWMMXt capable CPU will still do DSP context save/restore. These changes should make iWMMXt work on PXA3xx, and as a side effect, enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined), as well as setting and using HWCAP_IWMMXT properly. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/elf.h48
1 files changed, 16 insertions, 32 deletions
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index f3929307a56b..642382d2c9f0 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -114,40 +114,24 @@ extern char elf_platform[];
114 have no such handler. */ 114 have no such handler. */
115#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0 115#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0
116 116
117#ifndef CONFIG_IWMMXT
118
119/* Old NetWinder binaries were compiled in such a way that the iBCS
120 heuristic always trips on them. Until these binaries become uncommon
121 enough not to care, don't trust the `ibcs' flag here. In any case
122 there is no other ELF system currently supported by iBCS.
123 @@ Could print a warning message to encourage users to upgrade. */
124#define SET_PERSONALITY(ex,ibcs2) \
125 set_personality(((ex).e_flags & EF_ARM_APCS26 ? PER_LINUX : PER_LINUX_32BIT))
126
127#else
128
129/* 117/*
130 * All iWMMXt capable CPUs don't support 26-bit mode. Yet they can run 118 * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0
131 * legacy binaries which used to contain FPA11 floating point instructions 119 * and CP1, we only enable access to the iWMMXt coprocessor if the
132 * that have always been emulated by the kernel. PFA11 and iWMMXt overlap 120 * binary is EABI or softfloat (and thus, guaranteed not to use
133 * on coprocessor 1 space though. We therefore must decide if given task 121 * FPA instructions.)
134 * is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked
135 * at all times for the prefetch exception handler to catch FPA11 opcodes
136 * and emulate them. The best indication to discriminate those two cases
137 * is the SOFT_FLOAT flag in the ELF header.
138 */ 122 */
139 123#define SET_PERSONALITY(ex, ibcs2) \
140#define SET_PERSONALITY(ex,ibcs2) \ 124 do { \
141do { \ 125 if ((ex).e_flags & EF_ARM_APCS26) { \
142 set_personality(PER_LINUX_32BIT); \ 126 set_personality(PER_LINUX); \
143 if (((ex).e_flags & EF_ARM_EABI_MASK) || \ 127 } else { \
144 ((ex).e_flags & EF_ARM_SOFT_FLOAT)) \ 128 set_personality(PER_LINUX_32BIT); \
145 set_thread_flag(TIF_USING_IWMMXT); \ 129 if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \
146 else \ 130 set_thread_flag(TIF_USING_IWMMXT); \
147 clear_thread_flag(TIF_USING_IWMMXT); \ 131 else \
148} while (0) 132 clear_thread_flag(TIF_USING_IWMMXT); \
149 133 } \
150#endif 134 } while (0)
151 135
152#endif 136#endif
153 137