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authorMatt Reimer <mreimer@vpop.net>2005-10-28 11:25:02 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-10-28 11:25:02 -0400
commitd9e29649875df82828167dd45c802d942db863ba (patch)
tree8ce0d5d46bde4a92e212aabe18a3a86f508c8fd4 /include/asm-arm
parent80a18573cea2e6d8e95abe4d42bfc5f97761999a (diff)
[ARM] 3029/1: Add HWUART support for PXA 255/26x
Patch from Matt Reimer Adds support for HWUART on PXA 255 / 26x. This patch originally came from http://svn.rungie.com/svn/gumstix-buildroot/trunk/sources/kernel-patches/000-gumstix-hwuart.patch and has been tweaked by me. Signed-off-by: Matt Reimer <mreimer@vpop.net> Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h33
-rw-r--r--include/asm-arm/arch-pxa/uncompress.h1
2 files changed, 34 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index a6a34edec813..75f085dc9894 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -326,6 +326,25 @@
326#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ 326#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
327#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ 327#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
328 328
329/* Hardware UART (HWUART) */
330#define HWUART HWRBR
331#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
332#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
333#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
334#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
335#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
336#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
337#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
338#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
339#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
340#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
341#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
342#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
343#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
344#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
345#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
346#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
347
329#define IER_DMAE (1 << 7) /* DMA Requests Enable */ 348#define IER_DMAE (1 << 7) /* DMA Requests Enable */
330#define IER_UUE (1 << 6) /* UART Unit Enable */ 349#define IER_UUE (1 << 6) /* UART Unit Enable */
331#define IER_NRZE (1 << 5) /* NRZ coding Enable */ 350#define IER_NRZE (1 << 5) /* NRZ coding Enable */
@@ -1250,9 +1269,13 @@
1250#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ 1269#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
1251#define GPIO41_FFRTS 41 /* FFUART request to send */ 1270#define GPIO41_FFRTS 41 /* FFUART request to send */
1252#define GPIO42_BTRXD 42 /* BTUART receive data */ 1271#define GPIO42_BTRXD 42 /* BTUART receive data */
1272#define GPIO42_HWRXD 42 /* HWUART receive data */
1253#define GPIO43_BTTXD 43 /* BTUART transmit data */ 1273#define GPIO43_BTTXD 43 /* BTUART transmit data */
1274#define GPIO43_HWTXD 43 /* HWUART transmit data */
1254#define GPIO44_BTCTS 44 /* BTUART clear to send */ 1275#define GPIO44_BTCTS 44 /* BTUART clear to send */
1276#define GPIO44_HWCTS 44 /* HWUART clear to send */
1255#define GPIO45_BTRTS 45 /* BTUART request to send */ 1277#define GPIO45_BTRTS 45 /* BTUART request to send */
1278#define GPIO45_HWRTS 45 /* HWUART request to send */
1256#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ 1279#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
1257#define GPIO46_ICPRXD 46 /* ICP receive data */ 1280#define GPIO46_ICPRXD 46 /* ICP receive data */
1258#define GPIO46_STRXD 46 /* STD_UART receive data */ 1281#define GPIO46_STRXD 46 /* STD_UART receive data */
@@ -1378,17 +1401,26 @@
1378#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) 1401#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
1379#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) 1402#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
1380#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) 1403#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
1404#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
1381#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) 1405#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
1406#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
1382#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) 1407#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
1408#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
1383#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) 1409#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
1410#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
1384#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) 1411#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
1385#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) 1412#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
1386#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) 1413#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
1387#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) 1414#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
1388#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) 1415#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
1389#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) 1416#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
1417#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
1418#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
1419#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
1390#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) 1420#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
1391#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) 1421#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
1422#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
1423#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
1392#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) 1424#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
1393#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) 1425#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
1394#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) 1426#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
@@ -1763,6 +1795,7 @@
1763#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ 1795#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
1764#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ 1796#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
1765#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ 1797#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
1798#define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */
1766#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ 1799#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
1767#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ 1800#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
1768#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */ 1801#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index 4428d3eb7432..fe38090444e0 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -12,6 +12,7 @@
12#define FFUART ((volatile unsigned long *)0x40100000) 12#define FFUART ((volatile unsigned long *)0x40100000)
13#define BTUART ((volatile unsigned long *)0x40200000) 13#define BTUART ((volatile unsigned long *)0x40200000)
14#define STUART ((volatile unsigned long *)0x40700000) 14#define STUART ((volatile unsigned long *)0x40700000)
15#define HWUART ((volatile unsigned long *)0x41600000)
15 16
16#define UART FFUART 17#define UART FFUART
17 18