diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-07-14 16:28:25 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-07-14 18:34:46 -0400 |
commit | 53ffe3b440aa85af6fc4eda09b2d44bcdd312d4d (patch) | |
tree | e3ee2f392c5f73c855367cee998fc2e5774fa267 /include/asm-arm | |
parent | f0006314d37639714da9658cf4ff3f1f9f420764 (diff) | |
parent | cabb352a6455c3550f157909196845f533b0f374 (diff) |
[ARM] Merge most of the PXA work for initial merge
This includes PXA work up to the SPI changes for the initial merge,
since e172274ccc55d20536fbdceb6131f38e288541e0 depends on the SPI
tree being merged.
Conflicts:
arch/arm/configs/em_x270_defconfig
arch/arm/configs/xm_x270_defconfig
Diffstat (limited to 'include/asm-arm')
-rw-r--r-- | include/asm-arm/arch-pxa/audio.h | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/hardware.h | 9 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/irda.h | 4 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 570 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa25x-udc.h | 163 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa27x-udc.h | 257 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa2xx-gpio.h | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa2xx-regs.h | 162 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/system.h | 1 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/zylonite.h | 1 |
10 files changed, 593 insertions, 578 deletions
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h index 52bbe3bc25e1..f82f96dd1053 100644 --- a/include/asm-arm/arch-pxa/audio.h +++ b/include/asm-arm/arch-pxa/audio.h | |||
@@ -12,4 +12,6 @@ typedef struct { | |||
12 | void *priv; | 12 | void *priv; |
13 | } pxa2xx_audio_ops_t; | 13 | } pxa2xx_audio_ops_t; |
14 | 14 | ||
15 | extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops); | ||
16 | |||
15 | #endif | 17 | #endif |
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index e25558faa5a4..d9af6dabc899 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h | |||
@@ -192,15 +192,6 @@ extern int pxa_gpio_get_value(unsigned gpio); | |||
192 | extern void pxa_gpio_set_value(unsigned gpio, int value); | 192 | extern void pxa_gpio_set_value(unsigned gpio, int value); |
193 | 193 | ||
194 | /* | 194 | /* |
195 | * Routine to enable or disable CKEN | ||
196 | */ | ||
197 | static inline void __deprecated pxa_set_cken(int clock, int enable) | ||
198 | { | ||
199 | extern void __pxa_set_cken(int clock, int enable); | ||
200 | __pxa_set_cken(clock, enable); | ||
201 | } | ||
202 | |||
203 | /* | ||
204 | * return current memory and LCD clock frequency in units of 10kHz | 195 | * return current memory and LCD clock frequency in units of 10kHz |
205 | */ | 196 | */ |
206 | extern unsigned int get_memclk_frequency_10khz(void); | 197 | extern unsigned int get_memclk_frequency_10khz(void); |
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h index 99f4f423a8e1..0a50c3c763df 100644 --- a/include/asm-arm/arch-pxa/irda.h +++ b/include/asm-arm/arch-pxa/irda.h | |||
@@ -16,4 +16,8 @@ struct pxaficp_platform_data { | |||
16 | 16 | ||
17 | extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); | 17 | extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); |
18 | 18 | ||
19 | #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) | ||
20 | void pxa2xx_transceiver_mode(struct device *dev, int mode); | ||
21 | #endif | ||
22 | |||
19 | #endif | 23 | #endif |
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 4b2ea1e95c57..dce9308626b7 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
@@ -600,418 +600,6 @@ | |||
600 | 600 | ||
601 | 601 | ||
602 | /* | 602 | /* |
603 | * USB Device Controller | ||
604 | * PXA25x and PXA27x USB device controller registers are different. | ||
605 | */ | ||
606 | #if defined(CONFIG_PXA25x) | ||
607 | |||
608 | #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ | ||
609 | #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ | ||
610 | #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ | ||
611 | |||
612 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ | ||
613 | #define UDCCR_UDE (1 << 0) /* UDC enable */ | ||
614 | #define UDCCR_UDA (1 << 1) /* UDC active */ | ||
615 | #define UDCCR_RSM (1 << 2) /* Device resume */ | ||
616 | #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ | ||
617 | #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ | ||
618 | #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ | ||
619 | #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ | ||
620 | #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ | ||
621 | |||
622 | #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ | ||
623 | #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ | ||
624 | #define UDCCS0_IPR (1 << 1) /* IN packet ready */ | ||
625 | #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ | ||
626 | #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ | ||
627 | #define UDCCS0_SST (1 << 4) /* Sent stall */ | ||
628 | #define UDCCS0_FST (1 << 5) /* Force stall */ | ||
629 | #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ | ||
630 | #define UDCCS0_SA (1 << 7) /* Setup active */ | ||
631 | |||
632 | /* Bulk IN - Endpoint 1,6,11 */ | ||
633 | #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ | ||
634 | #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ | ||
635 | #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ | ||
636 | |||
637 | #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ | ||
638 | #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ | ||
639 | #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ | ||
640 | #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
641 | #define UDCCS_BI_SST (1 << 4) /* Sent stall */ | ||
642 | #define UDCCS_BI_FST (1 << 5) /* Force stall */ | ||
643 | #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ | ||
644 | |||
645 | /* Bulk OUT - Endpoint 2,7,12 */ | ||
646 | #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ | ||
647 | #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ | ||
648 | #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ | ||
649 | |||
650 | #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ | ||
651 | #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ | ||
652 | #define UDCCS_BO_DME (1 << 3) /* DMA enable */ | ||
653 | #define UDCCS_BO_SST (1 << 4) /* Sent stall */ | ||
654 | #define UDCCS_BO_FST (1 << 5) /* Force stall */ | ||
655 | #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ | ||
656 | #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ | ||
657 | |||
658 | /* Isochronous IN - Endpoint 3,8,13 */ | ||
659 | #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ | ||
660 | #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ | ||
661 | #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ | ||
662 | |||
663 | #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ | ||
664 | #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ | ||
665 | #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ | ||
666 | #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
667 | #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ | ||
668 | |||
669 | /* Isochronous OUT - Endpoint 4,9,14 */ | ||
670 | #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ | ||
671 | #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ | ||
672 | #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ | ||
673 | |||
674 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ | ||
675 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ | ||
676 | #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ | ||
677 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ | ||
678 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ | ||
679 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ | ||
680 | |||
681 | /* Interrupt IN - Endpoint 5,10,15 */ | ||
682 | #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ | ||
683 | #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ | ||
684 | #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ | ||
685 | |||
686 | #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ | ||
687 | #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ | ||
688 | #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ | ||
689 | #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
690 | #define UDCCS_INT_SST (1 << 4) /* Sent stall */ | ||
691 | #define UDCCS_INT_FST (1 << 5) /* Force stall */ | ||
692 | #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ | ||
693 | |||
694 | #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ | ||
695 | #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ | ||
696 | #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ | ||
697 | #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ | ||
698 | #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ | ||
699 | #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ | ||
700 | #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ | ||
701 | #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ | ||
702 | #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ | ||
703 | #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ | ||
704 | #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ | ||
705 | #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ | ||
706 | #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ | ||
707 | #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ | ||
708 | #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ | ||
709 | #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ | ||
710 | #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ | ||
711 | #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ | ||
712 | #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ | ||
713 | #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ | ||
714 | #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ | ||
715 | #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ | ||
716 | #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ | ||
717 | #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ | ||
718 | |||
719 | #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ | ||
720 | |||
721 | #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ | ||
722 | #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ | ||
723 | #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ | ||
724 | #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ | ||
725 | #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ | ||
726 | #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ | ||
727 | #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ | ||
728 | #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ | ||
729 | |||
730 | #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ | ||
731 | |||
732 | #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ | ||
733 | #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ | ||
734 | #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ | ||
735 | #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ | ||
736 | #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ | ||
737 | #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ | ||
738 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ | ||
739 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ | ||
740 | |||
741 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ | ||
742 | |||
743 | #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ | ||
744 | #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ | ||
745 | #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ | ||
746 | #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ | ||
747 | #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ | ||
748 | #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ | ||
749 | #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ | ||
750 | #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ | ||
751 | |||
752 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ | ||
753 | |||
754 | #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ | ||
755 | #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ | ||
756 | #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ | ||
757 | #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ | ||
758 | #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ | ||
759 | #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ | ||
760 | #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ | ||
761 | #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ | ||
762 | |||
763 | #elif defined(CONFIG_PXA27x) | ||
764 | |||
765 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ | ||
766 | #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ | ||
767 | #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation | ||
768 | Protocol Port Support */ | ||
769 | #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol | ||
770 | Support */ | ||
771 | #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol | ||
772 | Enable */ | ||
773 | #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ | ||
774 | #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ | ||
775 | #define UDCCR_ACN_S 11 | ||
776 | #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ | ||
777 | #define UDCCR_AIN_S 8 | ||
778 | #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface | ||
779 | Setting Number */ | ||
780 | #define UDCCR_AAISN_S 5 | ||
781 | #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active | ||
782 | Configuration */ | ||
783 | #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration | ||
784 | Error */ | ||
785 | #define UDCCR_UDR (1 << 2) /* UDC Resume */ | ||
786 | #define UDCCR_UDA (1 << 1) /* UDC Active */ | ||
787 | #define UDCCR_UDE (1 << 0) /* UDC Enable */ | ||
788 | |||
789 | #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ | ||
790 | #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ | ||
791 | #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ | ||
792 | #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ | ||
793 | |||
794 | #define UDC_INT_FIFOERROR (0x2) | ||
795 | #define UDC_INT_PACKETCMP (0x1) | ||
796 | |||
797 | #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | ||
798 | #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ | ||
799 | #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ | ||
800 | #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ | ||
801 | #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ | ||
802 | #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ | ||
803 | |||
804 | #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ | ||
805 | #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ | ||
806 | #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | ||
807 | #define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ | ||
808 | #define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ | ||
809 | #define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ | ||
810 | #define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ | ||
811 | #define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ | ||
812 | |||
813 | #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ | ||
814 | #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ | ||
815 | #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ | ||
816 | #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt | ||
817 | Rising Edge Interrupt Enable */ | ||
818 | #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt | ||
819 | Falling Edge Interrupt Enable */ | ||
820 | #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge | ||
821 | Interrupt Enable */ | ||
822 | #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge | ||
823 | Interrupt Enable */ | ||
824 | #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge | ||
825 | Interrupt Enable */ | ||
826 | #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge | ||
827 | Interrupt Enable */ | ||
828 | #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge | ||
829 | Interrupt Enable */ | ||
830 | #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge | ||
831 | Interrupt Enable */ | ||
832 | #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising | ||
833 | Edge Interrupt Enable */ | ||
834 | #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling | ||
835 | Edge Interrupt Enable */ | ||
836 | #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge | ||
837 | Interrupt Enable */ | ||
838 | #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge | ||
839 | Interrupt Enable */ | ||
840 | |||
841 | #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ | ||
842 | |||
843 | #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ | ||
844 | #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ | ||
845 | #define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ | ||
846 | #define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ | ||
847 | #define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ | ||
848 | #define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ | ||
849 | #define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ | ||
850 | #define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ | ||
851 | #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ | ||
852 | #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ | ||
853 | #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ | ||
854 | #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ | ||
855 | #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ | ||
856 | #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ | ||
857 | |||
858 | #define UDCCSN(x) __REG2(0x40600100, (x) << 2) | ||
859 | #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ | ||
860 | #define UDCCSR0_SA (1 << 7) /* Setup Active */ | ||
861 | #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ | ||
862 | #define UDCCSR0_FST (1 << 5) /* Force Stall */ | ||
863 | #define UDCCSR0_SST (1 << 4) /* Sent Stall */ | ||
864 | #define UDCCSR0_DME (1 << 3) /* DMA Enable */ | ||
865 | #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ | ||
866 | #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ | ||
867 | #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ | ||
868 | |||
869 | #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ | ||
870 | #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ | ||
871 | #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ | ||
872 | #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ | ||
873 | #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ | ||
874 | #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ | ||
875 | #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ | ||
876 | #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ | ||
877 | #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ | ||
878 | #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ | ||
879 | #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ | ||
880 | #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ | ||
881 | #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ | ||
882 | #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ | ||
883 | #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ | ||
884 | #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ | ||
885 | #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ | ||
886 | #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ | ||
887 | #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ | ||
888 | #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ | ||
889 | #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ | ||
890 | #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ | ||
891 | #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ | ||
892 | |||
893 | #define UDCCSR_DPE (1 << 9) /* Data Packet Error */ | ||
894 | #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ | ||
895 | #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ | ||
896 | #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ | ||
897 | #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ | ||
898 | #define UDCCSR_FST (1 << 5) /* Force STALL */ | ||
899 | #define UDCCSR_SST (1 << 4) /* Sent STALL */ | ||
900 | #define UDCCSR_DME (1 << 3) /* DMA Enable */ | ||
901 | #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ | ||
902 | #define UDCCSR_PC (1 << 1) /* Packet Complete */ | ||
903 | #define UDCCSR_FS (1 << 0) /* FIFO needs service */ | ||
904 | |||
905 | #define UDCBCN(x) __REG2(0x40600200, (x)<<2) | ||
906 | #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ | ||
907 | #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ | ||
908 | #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ | ||
909 | #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ | ||
910 | #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ | ||
911 | #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ | ||
912 | #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ | ||
913 | #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ | ||
914 | #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ | ||
915 | #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ | ||
916 | #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ | ||
917 | #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ | ||
918 | #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ | ||
919 | #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ | ||
920 | #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ | ||
921 | #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ | ||
922 | #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ | ||
923 | #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ | ||
924 | #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ | ||
925 | #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ | ||
926 | #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ | ||
927 | #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ | ||
928 | #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ | ||
929 | #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ | ||
930 | |||
931 | #define UDCDN(x) __REG2(0x40600300, (x)<<2) | ||
932 | #define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) | ||
933 | #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) | ||
934 | #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ | ||
935 | #define UDCDRA __REG(0x40600304) /* Data Register - EPA */ | ||
936 | #define UDCDRB __REG(0x40600308) /* Data Register - EPB */ | ||
937 | #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ | ||
938 | #define UDCDRD __REG(0x40600310) /* Data Register - EPD */ | ||
939 | #define UDCDRE __REG(0x40600314) /* Data Register - EPE */ | ||
940 | #define UDCDRF __REG(0x40600318) /* Data Register - EPF */ | ||
941 | #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ | ||
942 | #define UDCDRH __REG(0x40600320) /* Data Register - EPH */ | ||
943 | #define UDCDRI __REG(0x40600324) /* Data Register - EPI */ | ||
944 | #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ | ||
945 | #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ | ||
946 | #define UDCDRL __REG(0x40600330) /* Data Register - EPL */ | ||
947 | #define UDCDRM __REG(0x40600334) /* Data Register - EPM */ | ||
948 | #define UDCDRN __REG(0x40600338) /* Data Register - EPN */ | ||
949 | #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ | ||
950 | #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ | ||
951 | #define UDCDRR __REG(0x40600344) /* Data Register - EPR */ | ||
952 | #define UDCDRS __REG(0x40600348) /* Data Register - EPS */ | ||
953 | #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ | ||
954 | #define UDCDRU __REG(0x40600350) /* Data Register - EPU */ | ||
955 | #define UDCDRV __REG(0x40600354) /* Data Register - EPV */ | ||
956 | #define UDCDRW __REG(0x40600358) /* Data Register - EPW */ | ||
957 | #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ | ||
958 | |||
959 | #define UDCCN(x) __REG2(0x40600400, (x)<<2) | ||
960 | #define UDCCRA __REG(0x40600404) /* Configuration register EPA */ | ||
961 | #define UDCCRB __REG(0x40600408) /* Configuration register EPB */ | ||
962 | #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ | ||
963 | #define UDCCRD __REG(0x40600410) /* Configuration register EPD */ | ||
964 | #define UDCCRE __REG(0x40600414) /* Configuration register EPE */ | ||
965 | #define UDCCRF __REG(0x40600418) /* Configuration register EPF */ | ||
966 | #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ | ||
967 | #define UDCCRH __REG(0x40600420) /* Configuration register EPH */ | ||
968 | #define UDCCRI __REG(0x40600424) /* Configuration register EPI */ | ||
969 | #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ | ||
970 | #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ | ||
971 | #define UDCCRL __REG(0x40600430) /* Configuration register EPL */ | ||
972 | #define UDCCRM __REG(0x40600434) /* Configuration register EPM */ | ||
973 | #define UDCCRN __REG(0x40600438) /* Configuration register EPN */ | ||
974 | #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ | ||
975 | #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ | ||
976 | #define UDCCRR __REG(0x40600444) /* Configuration register EPR */ | ||
977 | #define UDCCRS __REG(0x40600448) /* Configuration register EPS */ | ||
978 | #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ | ||
979 | #define UDCCRU __REG(0x40600450) /* Configuration register EPU */ | ||
980 | #define UDCCRV __REG(0x40600454) /* Configuration register EPV */ | ||
981 | #define UDCCRW __REG(0x40600458) /* Configuration register EPW */ | ||
982 | #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ | ||
983 | |||
984 | #define UDCCONR_CN (0x03 << 25) /* Configuration Number */ | ||
985 | #define UDCCONR_CN_S (25) | ||
986 | #define UDCCONR_IN (0x07 << 22) /* Interface Number */ | ||
987 | #define UDCCONR_IN_S (22) | ||
988 | #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ | ||
989 | #define UDCCONR_AISN_S (19) | ||
990 | #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ | ||
991 | #define UDCCONR_EN_S (15) | ||
992 | #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ | ||
993 | #define UDCCONR_ET_S (13) | ||
994 | #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ | ||
995 | #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ | ||
996 | #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ | ||
997 | #define UDCCONR_ET_NU (0x00 << 13) /* Not used */ | ||
998 | #define UDCCONR_ED (1 << 12) /* Endpoint Direction */ | ||
999 | #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ | ||
1000 | #define UDCCONR_MPS_S (2) | ||
1001 | #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ | ||
1002 | #define UDCCONR_EE (1 << 0) /* Endpoint Enable */ | ||
1003 | |||
1004 | |||
1005 | #define UDC_INT_FIFOERROR (0x2) | ||
1006 | #define UDC_INT_PACKETCMP (0x1) | ||
1007 | |||
1008 | #define UDC_FNR_MASK (0x7ff) | ||
1009 | |||
1010 | #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) | ||
1011 | #define UDC_BCR_MASK (0x3ff) | ||
1012 | #endif | ||
1013 | |||
1014 | /* | ||
1015 | * Fast Infrared Communication Port | 603 | * Fast Infrared Communication Port |
1016 | */ | 604 | */ |
1017 | 605 | ||
@@ -1237,120 +825,9 @@ | |||
1237 | #endif | 825 | #endif |
1238 | 826 | ||
1239 | /* | 827 | /* |
1240 | * Power Manager | 828 | * Power Manager - see pxa2xx-regs.h |
1241 | */ | 829 | */ |
1242 | 830 | ||
1243 | #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ | ||
1244 | #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ | ||
1245 | #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ | ||
1246 | #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ | ||
1247 | #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ | ||
1248 | #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ | ||
1249 | #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ | ||
1250 | #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ | ||
1251 | #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ | ||
1252 | #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ | ||
1253 | #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ | ||
1254 | #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ | ||
1255 | #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ | ||
1256 | |||
1257 | #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ | ||
1258 | #define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */ | ||
1259 | #define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */ | ||
1260 | #define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */ | ||
1261 | #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ | ||
1262 | #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ | ||
1263 | #define PCMD(x) __REG2(0x40F00080, (x)<<2) | ||
1264 | #define PCMD0 __REG(0x40F00080 + 0 * 4) | ||
1265 | #define PCMD1 __REG(0x40F00080 + 1 * 4) | ||
1266 | #define PCMD2 __REG(0x40F00080 + 2 * 4) | ||
1267 | #define PCMD3 __REG(0x40F00080 + 3 * 4) | ||
1268 | #define PCMD4 __REG(0x40F00080 + 4 * 4) | ||
1269 | #define PCMD5 __REG(0x40F00080 + 5 * 4) | ||
1270 | #define PCMD6 __REG(0x40F00080 + 6 * 4) | ||
1271 | #define PCMD7 __REG(0x40F00080 + 7 * 4) | ||
1272 | #define PCMD8 __REG(0x40F00080 + 8 * 4) | ||
1273 | #define PCMD9 __REG(0x40F00080 + 9 * 4) | ||
1274 | #define PCMD10 __REG(0x40F00080 + 10 * 4) | ||
1275 | #define PCMD11 __REG(0x40F00080 + 11 * 4) | ||
1276 | #define PCMD12 __REG(0x40F00080 + 12 * 4) | ||
1277 | #define PCMD13 __REG(0x40F00080 + 13 * 4) | ||
1278 | #define PCMD14 __REG(0x40F00080 + 14 * 4) | ||
1279 | #define PCMD15 __REG(0x40F00080 + 15 * 4) | ||
1280 | #define PCMD16 __REG(0x40F00080 + 16 * 4) | ||
1281 | #define PCMD17 __REG(0x40F00080 + 17 * 4) | ||
1282 | #define PCMD18 __REG(0x40F00080 + 18 * 4) | ||
1283 | #define PCMD19 __REG(0x40F00080 + 19 * 4) | ||
1284 | #define PCMD20 __REG(0x40F00080 + 20 * 4) | ||
1285 | #define PCMD21 __REG(0x40F00080 + 21 * 4) | ||
1286 | #define PCMD22 __REG(0x40F00080 + 22 * 4) | ||
1287 | #define PCMD23 __REG(0x40F00080 + 23 * 4) | ||
1288 | #define PCMD24 __REG(0x40F00080 + 24 * 4) | ||
1289 | #define PCMD25 __REG(0x40F00080 + 25 * 4) | ||
1290 | #define PCMD26 __REG(0x40F00080 + 26 * 4) | ||
1291 | #define PCMD27 __REG(0x40F00080 + 27 * 4) | ||
1292 | #define PCMD28 __REG(0x40F00080 + 28 * 4) | ||
1293 | #define PCMD29 __REG(0x40F00080 + 29 * 4) | ||
1294 | #define PCMD30 __REG(0x40F00080 + 30 * 4) | ||
1295 | #define PCMD31 __REG(0x40F00080 + 31 * 4) | ||
1296 | |||
1297 | #define PCMD_MBC (1<<12) | ||
1298 | #define PCMD_DCE (1<<11) | ||
1299 | #define PCMD_LC (1<<10) | ||
1300 | /* FIXME: PCMD_SQC need be checked. */ | ||
1301 | #define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, | ||
1302 | bit 9 should be 0 all day. */ | ||
1303 | #define PVCR_VCSA (0x1<<14) | ||
1304 | #define PVCR_CommandDelay (0xf80) | ||
1305 | #define PCFR_PI2C_EN (0x1 << 6) | ||
1306 | |||
1307 | #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ | ||
1308 | #define PSSR_RDH (1 << 5) /* Read Disable Hold */ | ||
1309 | #define PSSR_PH (1 << 4) /* Peripheral Control Hold */ | ||
1310 | #define PSSR_STS (1 << 3) /* Standby Mode Status */ | ||
1311 | #define PSSR_VFS (1 << 2) /* VDD Fault Status */ | ||
1312 | #define PSSR_BFS (1 << 1) /* Battery Fault Status */ | ||
1313 | #define PSSR_SSS (1 << 0) /* Software Sleep Status */ | ||
1314 | |||
1315 | #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ | ||
1316 | |||
1317 | #define PCFR_RO (1 << 15) /* RDH Override */ | ||
1318 | #define PCFR_PO (1 << 14) /* PH Override */ | ||
1319 | #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ | ||
1320 | #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ | ||
1321 | #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ | ||
1322 | #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ | ||
1323 | #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ | ||
1324 | #define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ | ||
1325 | #define PCFR_DS (1 << 3) /* Deep Sleep Mode */ | ||
1326 | #define PCFR_FS (1 << 2) /* Float Static Chip Selects */ | ||
1327 | #define PCFR_FP (1 << 1) /* Float PCMCIA controls */ | ||
1328 | #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ | ||
1329 | |||
1330 | #define RCSR_GPR (1 << 3) /* GPIO Reset */ | ||
1331 | #define RCSR_SMR (1 << 2) /* Sleep Mode */ | ||
1332 | #define RCSR_WDR (1 << 1) /* Watchdog Reset */ | ||
1333 | #define RCSR_HWR (1 << 0) /* Hardware Reset */ | ||
1334 | |||
1335 | #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ | ||
1336 | #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ | ||
1337 | #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ | ||
1338 | #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ | ||
1339 | #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ | ||
1340 | #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ | ||
1341 | #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ | ||
1342 | #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ | ||
1343 | #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ | ||
1344 | #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ | ||
1345 | #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ | ||
1346 | #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ | ||
1347 | #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ | ||
1348 | #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ | ||
1349 | #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ | ||
1350 | #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ | ||
1351 | #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ | ||
1352 | #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ | ||
1353 | |||
1354 | /* | 831 | /* |
1355 | * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h | 832 | * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h |
1356 | */ | 833 | */ |
@@ -1360,52 +837,9 @@ | |||
1360 | */ | 837 | */ |
1361 | 838 | ||
1362 | /* | 839 | /* |
1363 | * Core Clock | 840 | * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h |
1364 | */ | 841 | */ |
1365 | 842 | ||
1366 | #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ | ||
1367 | #define CKEN __REG(0x41300004) /* Clock Enable Register */ | ||
1368 | #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ | ||
1369 | #define CCSR __REG(0x4130000C) /* Core Clock Status Register */ | ||
1370 | |||
1371 | #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ | ||
1372 | #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ | ||
1373 | #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ | ||
1374 | |||
1375 | #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ | ||
1376 | #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ | ||
1377 | #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ | ||
1378 | #define CKEN_MEMC (22) /* Memory Controller Clock Enable */ | ||
1379 | #define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ | ||
1380 | #define CKEN_IM (20) /* Internal Memory Clock Enable */ | ||
1381 | #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ | ||
1382 | #define CKEN_USIM (18) /* USIM Unit Clock Enable */ | ||
1383 | #define CKEN_MSL (17) /* MSL Unit Clock Enable */ | ||
1384 | #define CKEN_LCD (16) /* LCD Unit Clock Enable */ | ||
1385 | #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ | ||
1386 | #define CKEN_I2C (14) /* I2C Unit Clock Enable */ | ||
1387 | #define CKEN_FICP (13) /* FICP Unit Clock Enable */ | ||
1388 | #define CKEN_MMC (12) /* MMC Unit Clock Enable */ | ||
1389 | #define CKEN_USB (11) /* USB Unit Clock Enable */ | ||
1390 | #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ | ||
1391 | #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ | ||
1392 | #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ | ||
1393 | #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ | ||
1394 | #define CKEN_I2S (8) /* I2S Unit Clock Enable */ | ||
1395 | #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ | ||
1396 | #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ | ||
1397 | #define CKEN_STUART (5) /* STUART Unit Clock Enable */ | ||
1398 | #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ | ||
1399 | #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ | ||
1400 | #define CKEN_SSP (3) /* SSP Unit Clock Enable */ | ||
1401 | #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ | ||
1402 | #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ | ||
1403 | #define CKEN_PWM1 (1) /* PWM1 Clock Enable */ | ||
1404 | #define CKEN_PWM0 (0) /* PWM0 Clock Enable */ | ||
1405 | |||
1406 | #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ | ||
1407 | #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ | ||
1408 | |||
1409 | #ifdef CONFIG_PXA27x | 843 | #ifdef CONFIG_PXA27x |
1410 | 844 | ||
1411 | /* Camera Interface */ | 845 | /* Camera Interface */ |
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h new file mode 100644 index 000000000000..840305916b6d --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa25x-udc.h | |||
@@ -0,0 +1,163 @@ | |||
1 | #ifndef _ASM_ARCH_PXA25X_UDC_H | ||
2 | #define _ASM_ARCH_PXA25X_UDC_H | ||
3 | |||
4 | #ifdef _ASM_ARCH_PXA27X_UDC_H | ||
5 | #error You can't include both PXA25x and PXA27x UDC support | ||
6 | #endif | ||
7 | |||
8 | #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ | ||
9 | #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ | ||
10 | #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ | ||
11 | |||
12 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ | ||
13 | #define UDCCR_UDE (1 << 0) /* UDC enable */ | ||
14 | #define UDCCR_UDA (1 << 1) /* UDC active */ | ||
15 | #define UDCCR_RSM (1 << 2) /* Device resume */ | ||
16 | #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ | ||
17 | #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ | ||
18 | #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ | ||
19 | #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ | ||
20 | #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ | ||
21 | |||
22 | #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ | ||
23 | #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ | ||
24 | #define UDCCS0_IPR (1 << 1) /* IN packet ready */ | ||
25 | #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ | ||
26 | #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ | ||
27 | #define UDCCS0_SST (1 << 4) /* Sent stall */ | ||
28 | #define UDCCS0_FST (1 << 5) /* Force stall */ | ||
29 | #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ | ||
30 | #define UDCCS0_SA (1 << 7) /* Setup active */ | ||
31 | |||
32 | /* Bulk IN - Endpoint 1,6,11 */ | ||
33 | #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ | ||
34 | #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ | ||
35 | #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ | ||
36 | |||
37 | #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ | ||
38 | #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ | ||
39 | #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ | ||
40 | #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
41 | #define UDCCS_BI_SST (1 << 4) /* Sent stall */ | ||
42 | #define UDCCS_BI_FST (1 << 5) /* Force stall */ | ||
43 | #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ | ||
44 | |||
45 | /* Bulk OUT - Endpoint 2,7,12 */ | ||
46 | #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ | ||
47 | #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ | ||
48 | #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ | ||
49 | |||
50 | #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ | ||
51 | #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ | ||
52 | #define UDCCS_BO_DME (1 << 3) /* DMA enable */ | ||
53 | #define UDCCS_BO_SST (1 << 4) /* Sent stall */ | ||
54 | #define UDCCS_BO_FST (1 << 5) /* Force stall */ | ||
55 | #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ | ||
56 | #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ | ||
57 | |||
58 | /* Isochronous IN - Endpoint 3,8,13 */ | ||
59 | #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ | ||
60 | #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ | ||
61 | #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ | ||
62 | |||
63 | #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ | ||
64 | #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ | ||
65 | #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ | ||
66 | #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
67 | #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ | ||
68 | |||
69 | /* Isochronous OUT - Endpoint 4,9,14 */ | ||
70 | #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ | ||
71 | #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ | ||
72 | #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ | ||
73 | |||
74 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ | ||
75 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ | ||
76 | #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ | ||
77 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ | ||
78 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ | ||
79 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ | ||
80 | |||
81 | /* Interrupt IN - Endpoint 5,10,15 */ | ||
82 | #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ | ||
83 | #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ | ||
84 | #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ | ||
85 | |||
86 | #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ | ||
87 | #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ | ||
88 | #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ | ||
89 | #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
90 | #define UDCCS_INT_SST (1 << 4) /* Sent stall */ | ||
91 | #define UDCCS_INT_FST (1 << 5) /* Force stall */ | ||
92 | #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ | ||
93 | |||
94 | #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ | ||
95 | #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ | ||
96 | #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ | ||
97 | #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ | ||
98 | #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ | ||
99 | #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ | ||
100 | #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ | ||
101 | #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ | ||
102 | #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ | ||
103 | #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ | ||
104 | #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ | ||
105 | #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ | ||
106 | #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ | ||
107 | #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ | ||
108 | #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ | ||
109 | #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ | ||
110 | #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ | ||
111 | #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ | ||
112 | #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ | ||
113 | #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ | ||
114 | #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ | ||
115 | #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ | ||
116 | #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ | ||
117 | #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ | ||
118 | |||
119 | #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ | ||
120 | |||
121 | #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ | ||
122 | #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ | ||
123 | #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ | ||
124 | #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ | ||
125 | #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ | ||
126 | #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ | ||
127 | #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ | ||
128 | #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ | ||
129 | |||
130 | #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ | ||
131 | |||
132 | #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ | ||
133 | #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ | ||
134 | #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ | ||
135 | #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ | ||
136 | #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ | ||
137 | #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ | ||
138 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ | ||
139 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ | ||
140 | |||
141 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ | ||
142 | |||
143 | #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ | ||
144 | #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ | ||
145 | #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ | ||
146 | #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ | ||
147 | #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ | ||
148 | #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ | ||
149 | #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ | ||
150 | #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ | ||
151 | |||
152 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ | ||
153 | |||
154 | #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ | ||
155 | #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ | ||
156 | #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ | ||
157 | #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ | ||
158 | #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ | ||
159 | #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ | ||
160 | #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ | ||
161 | #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ | ||
162 | |||
163 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h new file mode 100644 index 000000000000..bc1cf7d0773a --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa27x-udc.h | |||
@@ -0,0 +1,257 @@ | |||
1 | #ifndef _ASM_ARCH_PXA27X_UDC_H | ||
2 | #define _ASM_ARCH_PXA27X_UDC_H | ||
3 | |||
4 | #ifdef _ASM_ARCH_PXA25X_UDC_H | ||
5 | #error You cannot include both PXA25x and PXA27x UDC support | ||
6 | #endif | ||
7 | |||
8 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ | ||
9 | #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ | ||
10 | #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation | ||
11 | Protocol Port Support */ | ||
12 | #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol | ||
13 | Support */ | ||
14 | #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol | ||
15 | Enable */ | ||
16 | #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ | ||
17 | #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ | ||
18 | #define UDCCR_ACN_S 11 | ||
19 | #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ | ||
20 | #define UDCCR_AIN_S 8 | ||
21 | #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface | ||
22 | Setting Number */ | ||
23 | #define UDCCR_AAISN_S 5 | ||
24 | #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active | ||
25 | Configuration */ | ||
26 | #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration | ||
27 | Error */ | ||
28 | #define UDCCR_UDR (1 << 2) /* UDC Resume */ | ||
29 | #define UDCCR_UDA (1 << 1) /* UDC Active */ | ||
30 | #define UDCCR_UDE (1 << 0) /* UDC Enable */ | ||
31 | |||
32 | #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ | ||
33 | #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ | ||
34 | #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ | ||
35 | #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ | ||
36 | |||
37 | #define UDC_INT_FIFOERROR (0x2) | ||
38 | #define UDC_INT_PACKETCMP (0x1) | ||
39 | |||
40 | #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | ||
41 | #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ | ||
42 | #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ | ||
43 | #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ | ||
44 | #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ | ||
45 | #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ | ||
46 | |||
47 | #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ | ||
48 | #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ | ||
49 | #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | ||
50 | #define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ | ||
51 | #define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ | ||
52 | #define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ | ||
53 | #define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ | ||
54 | #define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ | ||
55 | |||
56 | #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ | ||
57 | #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ | ||
58 | #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ | ||
59 | #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt | ||
60 | Rising Edge Interrupt Enable */ | ||
61 | #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt | ||
62 | Falling Edge Interrupt Enable */ | ||
63 | #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge | ||
64 | Interrupt Enable */ | ||
65 | #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge | ||
66 | Interrupt Enable */ | ||
67 | #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge | ||
68 | Interrupt Enable */ | ||
69 | #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge | ||
70 | Interrupt Enable */ | ||
71 | #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge | ||
72 | Interrupt Enable */ | ||
73 | #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge | ||
74 | Interrupt Enable */ | ||
75 | #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising | ||
76 | Edge Interrupt Enable */ | ||
77 | #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling | ||
78 | Edge Interrupt Enable */ | ||
79 | #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge | ||
80 | Interrupt Enable */ | ||
81 | #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge | ||
82 | Interrupt Enable */ | ||
83 | |||
84 | #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ | ||
85 | #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */ | ||
86 | |||
87 | #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ | ||
88 | #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ | ||
89 | #define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ | ||
90 | #define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ | ||
91 | #define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ | ||
92 | #define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ | ||
93 | #define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ | ||
94 | #define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ | ||
95 | #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ | ||
96 | #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ | ||
97 | #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ | ||
98 | #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ | ||
99 | #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ | ||
100 | #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ | ||
101 | |||
102 | #define UDCCSN(x) __REG2(0x40600100, (x) << 2) | ||
103 | #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ | ||
104 | #define UDCCSR0_SA (1 << 7) /* Setup Active */ | ||
105 | #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ | ||
106 | #define UDCCSR0_FST (1 << 5) /* Force Stall */ | ||
107 | #define UDCCSR0_SST (1 << 4) /* Sent Stall */ | ||
108 | #define UDCCSR0_DME (1 << 3) /* DMA Enable */ | ||
109 | #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ | ||
110 | #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ | ||
111 | #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ | ||
112 | |||
113 | #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ | ||
114 | #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ | ||
115 | #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ | ||
116 | #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ | ||
117 | #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ | ||
118 | #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ | ||
119 | #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ | ||
120 | #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ | ||
121 | #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ | ||
122 | #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ | ||
123 | #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ | ||
124 | #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ | ||
125 | #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ | ||
126 | #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ | ||
127 | #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ | ||
128 | #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ | ||
129 | #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ | ||
130 | #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ | ||
131 | #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ | ||
132 | #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ | ||
133 | #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ | ||
134 | #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ | ||
135 | #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ | ||
136 | |||
137 | #define UDCCSR_DPE (1 << 9) /* Data Packet Error */ | ||
138 | #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ | ||
139 | #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ | ||
140 | #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ | ||
141 | #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ | ||
142 | #define UDCCSR_FST (1 << 5) /* Force STALL */ | ||
143 | #define UDCCSR_SST (1 << 4) /* Sent STALL */ | ||
144 | #define UDCCSR_DME (1 << 3) /* DMA Enable */ | ||
145 | #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ | ||
146 | #define UDCCSR_PC (1 << 1) /* Packet Complete */ | ||
147 | #define UDCCSR_FS (1 << 0) /* FIFO needs service */ | ||
148 | |||
149 | #define UDCBCN(x) __REG2(0x40600200, (x)<<2) | ||
150 | #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ | ||
151 | #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ | ||
152 | #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ | ||
153 | #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ | ||
154 | #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ | ||
155 | #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ | ||
156 | #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ | ||
157 | #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ | ||
158 | #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ | ||
159 | #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ | ||
160 | #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ | ||
161 | #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ | ||
162 | #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ | ||
163 | #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ | ||
164 | #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ | ||
165 | #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ | ||
166 | #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ | ||
167 | #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ | ||
168 | #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ | ||
169 | #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ | ||
170 | #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ | ||
171 | #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ | ||
172 | #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ | ||
173 | #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ | ||
174 | |||
175 | #define UDCDN(x) __REG2(0x40600300, (x)<<2) | ||
176 | #define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) | ||
177 | #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) | ||
178 | #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ | ||
179 | #define UDCDRA __REG(0x40600304) /* Data Register - EPA */ | ||
180 | #define UDCDRB __REG(0x40600308) /* Data Register - EPB */ | ||
181 | #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ | ||
182 | #define UDCDRD __REG(0x40600310) /* Data Register - EPD */ | ||
183 | #define UDCDRE __REG(0x40600314) /* Data Register - EPE */ | ||
184 | #define UDCDRF __REG(0x40600318) /* Data Register - EPF */ | ||
185 | #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ | ||
186 | #define UDCDRH __REG(0x40600320) /* Data Register - EPH */ | ||
187 | #define UDCDRI __REG(0x40600324) /* Data Register - EPI */ | ||
188 | #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ | ||
189 | #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ | ||
190 | #define UDCDRL __REG(0x40600330) /* Data Register - EPL */ | ||
191 | #define UDCDRM __REG(0x40600334) /* Data Register - EPM */ | ||
192 | #define UDCDRN __REG(0x40600338) /* Data Register - EPN */ | ||
193 | #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ | ||
194 | #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ | ||
195 | #define UDCDRR __REG(0x40600344) /* Data Register - EPR */ | ||
196 | #define UDCDRS __REG(0x40600348) /* Data Register - EPS */ | ||
197 | #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ | ||
198 | #define UDCDRU __REG(0x40600350) /* Data Register - EPU */ | ||
199 | #define UDCDRV __REG(0x40600354) /* Data Register - EPV */ | ||
200 | #define UDCDRW __REG(0x40600358) /* Data Register - EPW */ | ||
201 | #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ | ||
202 | |||
203 | #define UDCCN(x) __REG2(0x40600400, (x)<<2) | ||
204 | #define UDCCRA __REG(0x40600404) /* Configuration register EPA */ | ||
205 | #define UDCCRB __REG(0x40600408) /* Configuration register EPB */ | ||
206 | #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ | ||
207 | #define UDCCRD __REG(0x40600410) /* Configuration register EPD */ | ||
208 | #define UDCCRE __REG(0x40600414) /* Configuration register EPE */ | ||
209 | #define UDCCRF __REG(0x40600418) /* Configuration register EPF */ | ||
210 | #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ | ||
211 | #define UDCCRH __REG(0x40600420) /* Configuration register EPH */ | ||
212 | #define UDCCRI __REG(0x40600424) /* Configuration register EPI */ | ||
213 | #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ | ||
214 | #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ | ||
215 | #define UDCCRL __REG(0x40600430) /* Configuration register EPL */ | ||
216 | #define UDCCRM __REG(0x40600434) /* Configuration register EPM */ | ||
217 | #define UDCCRN __REG(0x40600438) /* Configuration register EPN */ | ||
218 | #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ | ||
219 | #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ | ||
220 | #define UDCCRR __REG(0x40600444) /* Configuration register EPR */ | ||
221 | #define UDCCRS __REG(0x40600448) /* Configuration register EPS */ | ||
222 | #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ | ||
223 | #define UDCCRU __REG(0x40600450) /* Configuration register EPU */ | ||
224 | #define UDCCRV __REG(0x40600454) /* Configuration register EPV */ | ||
225 | #define UDCCRW __REG(0x40600458) /* Configuration register EPW */ | ||
226 | #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ | ||
227 | |||
228 | #define UDCCONR_CN (0x03 << 25) /* Configuration Number */ | ||
229 | #define UDCCONR_CN_S (25) | ||
230 | #define UDCCONR_IN (0x07 << 22) /* Interface Number */ | ||
231 | #define UDCCONR_IN_S (22) | ||
232 | #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ | ||
233 | #define UDCCONR_AISN_S (19) | ||
234 | #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ | ||
235 | #define UDCCONR_EN_S (15) | ||
236 | #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ | ||
237 | #define UDCCONR_ET_S (13) | ||
238 | #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ | ||
239 | #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ | ||
240 | #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ | ||
241 | #define UDCCONR_ET_NU (0x00 << 13) /* Not used */ | ||
242 | #define UDCCONR_ED (1 << 12) /* Endpoint Direction */ | ||
243 | #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ | ||
244 | #define UDCCONR_MPS_S (2) | ||
245 | #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ | ||
246 | #define UDCCONR_EE (1 << 0) /* Endpoint Enable */ | ||
247 | |||
248 | |||
249 | #define UDC_INT_FIFOERROR (0x2) | ||
250 | #define UDC_INT_PACKETCMP (0x1) | ||
251 | |||
252 | #define UDC_FNR_MASK (0x7ff) | ||
253 | |||
254 | #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) | ||
255 | #define UDC_BCR_MASK (0x3ff) | ||
256 | |||
257 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h index b81cd63cb2eb..6ef1dd09970b 100644 --- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h +++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h | |||
@@ -1,6 +1,8 @@ | |||
1 | #ifndef __ASM_ARCH_PXA2XX_GPIO_H | 1 | #ifndef __ASM_ARCH_PXA2XX_GPIO_H |
2 | #define __ASM_ARCH_PXA2XX_GPIO_H | 2 | #define __ASM_ARCH_PXA2XX_GPIO_H |
3 | 3 | ||
4 | #warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h | ||
5 | |||
4 | /* GPIO alternate function assignments */ | 6 | /* GPIO alternate function assignments */ |
5 | 7 | ||
6 | #define GPIO1_RST 1 /* reset */ | 8 | #define GPIO1_RST 1 /* reset */ |
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h index 9553b54fa5bc..73e0a329cf7f 100644 --- a/include/asm-arm/arch-pxa/pxa2xx-regs.h +++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h | |||
@@ -81,4 +81,166 @@ | |||
81 | 81 | ||
82 | #endif | 82 | #endif |
83 | 83 | ||
84 | |||
85 | /* | ||
86 | * Power Manager | ||
87 | */ | ||
88 | |||
89 | #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ | ||
90 | #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ | ||
91 | #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ | ||
92 | #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ | ||
93 | #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ | ||
94 | #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ | ||
95 | #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ | ||
96 | #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ | ||
97 | #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ | ||
98 | #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ | ||
99 | #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ | ||
100 | #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ | ||
101 | #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ | ||
102 | |||
103 | #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ | ||
104 | #define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ | ||
105 | #define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ | ||
106 | #define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ | ||
107 | #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ | ||
108 | #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ | ||
109 | #define PCMD(x) __REG2(0x40F00080, (x)<<2) | ||
110 | #define PCMD0 __REG(0x40F00080 + 0 * 4) | ||
111 | #define PCMD1 __REG(0x40F00080 + 1 * 4) | ||
112 | #define PCMD2 __REG(0x40F00080 + 2 * 4) | ||
113 | #define PCMD3 __REG(0x40F00080 + 3 * 4) | ||
114 | #define PCMD4 __REG(0x40F00080 + 4 * 4) | ||
115 | #define PCMD5 __REG(0x40F00080 + 5 * 4) | ||
116 | #define PCMD6 __REG(0x40F00080 + 6 * 4) | ||
117 | #define PCMD7 __REG(0x40F00080 + 7 * 4) | ||
118 | #define PCMD8 __REG(0x40F00080 + 8 * 4) | ||
119 | #define PCMD9 __REG(0x40F00080 + 9 * 4) | ||
120 | #define PCMD10 __REG(0x40F00080 + 10 * 4) | ||
121 | #define PCMD11 __REG(0x40F00080 + 11 * 4) | ||
122 | #define PCMD12 __REG(0x40F00080 + 12 * 4) | ||
123 | #define PCMD13 __REG(0x40F00080 + 13 * 4) | ||
124 | #define PCMD14 __REG(0x40F00080 + 14 * 4) | ||
125 | #define PCMD15 __REG(0x40F00080 + 15 * 4) | ||
126 | #define PCMD16 __REG(0x40F00080 + 16 * 4) | ||
127 | #define PCMD17 __REG(0x40F00080 + 17 * 4) | ||
128 | #define PCMD18 __REG(0x40F00080 + 18 * 4) | ||
129 | #define PCMD19 __REG(0x40F00080 + 19 * 4) | ||
130 | #define PCMD20 __REG(0x40F00080 + 20 * 4) | ||
131 | #define PCMD21 __REG(0x40F00080 + 21 * 4) | ||
132 | #define PCMD22 __REG(0x40F00080 + 22 * 4) | ||
133 | #define PCMD23 __REG(0x40F00080 + 23 * 4) | ||
134 | #define PCMD24 __REG(0x40F00080 + 24 * 4) | ||
135 | #define PCMD25 __REG(0x40F00080 + 25 * 4) | ||
136 | #define PCMD26 __REG(0x40F00080 + 26 * 4) | ||
137 | #define PCMD27 __REG(0x40F00080 + 27 * 4) | ||
138 | #define PCMD28 __REG(0x40F00080 + 28 * 4) | ||
139 | #define PCMD29 __REG(0x40F00080 + 29 * 4) | ||
140 | #define PCMD30 __REG(0x40F00080 + 30 * 4) | ||
141 | #define PCMD31 __REG(0x40F00080 + 31 * 4) | ||
142 | |||
143 | #define PCMD_MBC (1<<12) | ||
144 | #define PCMD_DCE (1<<11) | ||
145 | #define PCMD_LC (1<<10) | ||
146 | /* FIXME: PCMD_SQC need be checked. */ | ||
147 | #define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, | ||
148 | bit 9 should be 0 all day. */ | ||
149 | #define PVCR_VCSA (0x1<<14) | ||
150 | #define PVCR_CommandDelay (0xf80) | ||
151 | #define PCFR_PI2C_EN (0x1 << 6) | ||
152 | |||
153 | #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ | ||
154 | #define PSSR_RDH (1 << 5) /* Read Disable Hold */ | ||
155 | #define PSSR_PH (1 << 4) /* Peripheral Control Hold */ | ||
156 | #define PSSR_STS (1 << 3) /* Standby Mode Status */ | ||
157 | #define PSSR_VFS (1 << 2) /* VDD Fault Status */ | ||
158 | #define PSSR_BFS (1 << 1) /* Battery Fault Status */ | ||
159 | #define PSSR_SSS (1 << 0) /* Software Sleep Status */ | ||
160 | |||
161 | #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ | ||
162 | |||
163 | #define PCFR_RO (1 << 15) /* RDH Override */ | ||
164 | #define PCFR_PO (1 << 14) /* PH Override */ | ||
165 | #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ | ||
166 | #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ | ||
167 | #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ | ||
168 | #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ | ||
169 | #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ | ||
170 | #define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ | ||
171 | #define PCFR_DS (1 << 3) /* Deep Sleep Mode */ | ||
172 | #define PCFR_FS (1 << 2) /* Float Static Chip Selects */ | ||
173 | #define PCFR_FP (1 << 1) /* Float PCMCIA controls */ | ||
174 | #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ | ||
175 | |||
176 | #define RCSR_GPR (1 << 3) /* GPIO Reset */ | ||
177 | #define RCSR_SMR (1 << 2) /* Sleep Mode */ | ||
178 | #define RCSR_WDR (1 << 1) /* Watchdog Reset */ | ||
179 | #define RCSR_HWR (1 << 0) /* Hardware Reset */ | ||
180 | |||
181 | #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ | ||
182 | #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ | ||
183 | #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ | ||
184 | #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ | ||
185 | #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ | ||
186 | #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ | ||
187 | #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ | ||
188 | #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ | ||
189 | #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ | ||
190 | #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ | ||
191 | #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ | ||
192 | #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ | ||
193 | #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ | ||
194 | #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ | ||
195 | #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ | ||
196 | #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ | ||
197 | #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ | ||
198 | #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ | ||
199 | |||
200 | /* | ||
201 | * PXA2xx specific Core clock definitions | ||
202 | */ | ||
203 | #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ | ||
204 | #define CCSR __REG(0x4130000C) /* Core Clock Status Register */ | ||
205 | #define CKEN __REG(0x41300004) /* Clock Enable Register */ | ||
206 | #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ | ||
207 | |||
208 | #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ | ||
209 | #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ | ||
210 | #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ | ||
211 | |||
212 | #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ | ||
213 | #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ | ||
214 | #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ | ||
215 | #define CKEN_MEMC (22) /* Memory Controller Clock Enable */ | ||
216 | #define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ | ||
217 | #define CKEN_IM (20) /* Internal Memory Clock Enable */ | ||
218 | #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ | ||
219 | #define CKEN_USIM (18) /* USIM Unit Clock Enable */ | ||
220 | #define CKEN_MSL (17) /* MSL Unit Clock Enable */ | ||
221 | #define CKEN_LCD (16) /* LCD Unit Clock Enable */ | ||
222 | #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ | ||
223 | #define CKEN_I2C (14) /* I2C Unit Clock Enable */ | ||
224 | #define CKEN_FICP (13) /* FICP Unit Clock Enable */ | ||
225 | #define CKEN_MMC (12) /* MMC Unit Clock Enable */ | ||
226 | #define CKEN_USB (11) /* USB Unit Clock Enable */ | ||
227 | #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ | ||
228 | #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ | ||
229 | #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ | ||
230 | #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ | ||
231 | #define CKEN_I2S (8) /* I2S Unit Clock Enable */ | ||
232 | #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ | ||
233 | #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ | ||
234 | #define CKEN_STUART (5) /* STUART Unit Clock Enable */ | ||
235 | #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ | ||
236 | #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ | ||
237 | #define CKEN_SSP (3) /* SSP Unit Clock Enable */ | ||
238 | #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ | ||
239 | #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ | ||
240 | #define CKEN_PWM1 (1) /* PWM1 Clock Enable */ | ||
241 | #define CKEN_PWM0 (0) /* PWM0 Clock Enable */ | ||
242 | |||
243 | #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ | ||
244 | #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ | ||
245 | |||
84 | #endif | 246 | #endif |
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h index 9aa6c2e939e8..ba7e132de1b3 100644 --- a/include/asm-arm/arch-pxa/system.h +++ b/include/asm-arm/arch-pxa/system.h | |||
@@ -12,6 +12,7 @@ | |||
12 | 12 | ||
13 | #include <asm/proc-fns.h> | 13 | #include <asm/proc-fns.h> |
14 | #include "hardware.h" | 14 | #include "hardware.h" |
15 | #include "pxa2xx-regs.h" | ||
15 | #include "pxa-regs.h" | 16 | #include "pxa-regs.h" |
16 | 17 | ||
17 | static inline void arch_idle(void) | 18 | static inline void arch_idle(void) |
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h index 4881b80f0f90..de577de8d18c 100644 --- a/include/asm-arm/arch-pxa/zylonite.h +++ b/include/asm-arm/arch-pxa/zylonite.h | |||
@@ -15,7 +15,6 @@ struct platform_mmc_slot { | |||
15 | 15 | ||
16 | extern struct platform_mmc_slot zylonite_mmc_slot[]; | 16 | extern struct platform_mmc_slot zylonite_mmc_slot[]; |
17 | 17 | ||
18 | extern int gpio_backlight; | ||
19 | extern int gpio_eth_irq; | 18 | extern int gpio_eth_irq; |
20 | 19 | ||
21 | extern int wm9713_irq; | 20 | extern int wm9713_irq; |