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authorMark Brown <broonie@sirena.org.uk>2008-06-18 22:11:49 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-07-10 12:07:46 -0400
commit54b238469bce3a1b5012b2f0ebf261cf1c53e664 (patch)
treed9fda05cd44d602edf3be6fe933d38d155429e11 /include/asm-arm
parentd6c47417a4ddf500a106fc8718c0f6107c7d5211 (diff)
[ARM] 5113/1: PXA SSP: Additional register definitions for PXA3xx SSP
Also add some white space for a little clarity. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h16
1 files changed, 15 insertions, 1 deletions
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
index 0255328c3c18..3c04cde2cf1f 100644
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -20,6 +20,10 @@
20#define SSTSS (0x38) /* SSP Timeslot Status */ 20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */ 21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22 22
23#if defined(CONFIG_PXA3xx)
24#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
25#endif
26
23/* Common PXA2xx bits first */ 27/* Common PXA2xx bits first */
24#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ 28#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
25#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ 29#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
@@ -29,10 +33,12 @@
29#define SSCR0_National (0x2 << 4) /* National Microwire */ 33#define SSCR0_National (0x2 << 4) /* National Microwire */
30#define SSCR0_ECS (1 << 6) /* External clock select */ 34#define SSCR0_ECS (1 << 6) /* External clock select */
31#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ 35#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
36
32#if defined(CONFIG_PXA25x) 37#if defined(CONFIG_PXA25x)
33#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ 38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
34#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ 39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
35#elif defined(CONFIG_PXA27x) 40
41#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
36#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ 42#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
37#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ 43#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
38#define SSCR0_EDSS (1 << 20) /* Extended data size select */ 44#define SSCR0_EDSS (1 << 20) /* Extended data size select */
@@ -45,6 +51,10 @@
45#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ 51#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
46#endif 52#endif
47 53
54#if defined(CONFIG_PXA3xx)
55#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
56#endif
57
48#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ 58#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
49#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ 59#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
50#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ 60#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
@@ -109,5 +119,9 @@
109#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ 119#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
110#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ 120#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
111#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ 121#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
122#if defined(CONFIG_PXA3xx)
123#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
124#endif
125
112 126
113#endif /* __ASM_ARCH_REGS_SSP_H */ 127#endif /* __ASM_ARCH_REGS_SSP_H */