Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into for-rmk

author: Ben Dooks <ben-linux@fluff.org> 2008-07-15 15:19:14 -0400
committer: Ben Dooks <ben-linux@fluff.org> 2008-07-15 15:19:14 -0400
commit: 0c17e4ceedd35c78b1c7413dbd16279a350be6bc (patch)
tree: 313b3b9ca04727f3704464e01d8dd97da1dd534b /include/asm-arm
parent: 19c1d6a34abf73d0baf8e325d018c920fa78dddc (diff)
parent: b9d2252c1e44fa83a4e65fdc9eb93db6297c55af (diff)
128 files changed, 4763 insertions, 1218 deletions
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index c2b13c280155..2001e81f2267 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -39,10 +39,14 @@
 #define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
 #define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL, CAP9] */
+#define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
+#define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
+#define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
+#define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI PLL Start-up Time */
 #define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
 #define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
-#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
+#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [SAM9x, CAP9] */
 #define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
 #define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
@@ -97,6 +101,7 @@
 #define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
 #define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
 #define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
+#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [AT91CAP9 only] */
 #define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
 #define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
index bac83adb5050..6f14d9053ac7 100644
--- a/include/asm-arm/arch-at91/at91cap9.h
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -118,7 +118,7 @@
 #define AT91CAP9_ROM_SIZE       (32 * SZ_1K)    /* Internal ROM size (32Kb) */
 #define AT91CAP9_LCDC_BASE      0x00500000      /* LCD Controller */
-#define AT91CAP9_UDPHS_BASE     0x00600000      /* USB High Speed Device Port */
+#define AT91CAP9_UDPHS_FIFO     0x00600000      /* USB High Speed Device Port */
 #define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
 #define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
index a641686b6c3d..ddbd4873c842 100644
--- a/include/asm-arm/arch-at91/at91cap9_matrix.h
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -106,6 +106,11 @@
 #define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
 #define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
+#define AT91_MATRIX_UDPHS       (AT91_MATRIX + 0x118)   /* USBHS Special Function Register [AT91CAP9 only] */
+#define         AT91_MATRIX_SELECT_UDPHS        (0 << 31)       /* select High Speed UDP */
+#define         AT91_MATRIX_SELECT_UDP          (1 << 31)       /* select standard UDP */
+#define         AT91_MATRIX_UDPHS_BYPASS_LOCK   (1 << 30)       /* bypass lock bit */
 #define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index c8934fe34dc5..889872a3f2a9 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -6,6 +6,8 @@
 * Common definitions.
 * Based on AT91SAM9260 datasheet revision A (Preliminary).
 *
+ * Includes also definitions for AT91SAM9XE and AT91SAM9G families
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
@@ -123,5 +125,14 @@
 #define AT91SAM9XE_FLASH_BASE   0x00200000      /* Internal FLASH base address */
 #define AT91SAM9XE_SRAM_BASE    0x00300000      /* Internal SRAM base address */
+#define AT91SAM9G20_ROM_BASE    0x00100000      /* Internal ROM base address */
+#define AT91SAM9G20_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+#define AT91SAM9G20_SRAM0_BASE  0x00200000      /* Internal SRAM 0 base address */
+#define AT91SAM9G20_SRAM0_SIZE  SZ_16K          /* Internal SRAM 0 size (16Kb) */
+#define AT91SAM9G20_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
+#define AT91SAM9G20_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
+#define AT91SAM9G20_UHP_BASE    0x00500000      /* USB Host controller */
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 16d2832f6c0a..622e56f81d42 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -110,6 +110,6 @@
 #define AT91SAM9RL_ROM_SIZE     (2 * SZ_16K)    /* Internal ROM size (32Kb) */
 #define AT91SAM9RL_LCDC_BASE    0x00500000      /* LCD Controller */
-#define AT91SAM9RL_UDPHS_BASE   0x00600000      /* USB Device HS controller */
+#define AT91SAM9RL_UDPHS_FIFO   0x00600000      /* USB Device HS controller */
 #endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index dc189f01c5b3..94de788da76e 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -36,6 +36,7 @@
 #include <linux/i2c.h>
 #include <linux/leds.h>
 #include <linux/spi/spi.h>
+#include <linux/usb/atmel_usba_udc.h>
 /* USB Device */
 struct at91_udc_data {
@@ -45,6 +46,9 @@ struct at91_udc_data {
 };
 extern void __init at91_add_device_udc(struct at91_udc_data *data);
+ /* USB High Speed Device */
+extern void __init at91_add_device_usba(struct usba_platform_data *data);
 /* Compact Flash */
 struct at91_cf_data {
        u8      irq_pin;                /* I/O IRQ */
@@ -73,7 +77,7 @@ struct at91_eth_data {
 };
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
 #define eth_platform_data       at91_eth_data
 #endif
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 7145166826a2..52df794205cb 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,6 +21,7 @@
 #define ARCH_ID_AT91SAM9260     0x019803a0
 #define ARCH_ID_AT91SAM9261     0x019703a0
 #define ARCH_ID_AT91SAM9263     0x019607a0
+#define ARCH_ID_AT91SAM9G20     0x019905a0
 #define ARCH_ID_AT91SAM9RL64    0x019b03a0
 #define ARCH_ID_AT91CAP9        0x039A03A0
@@ -63,6 +64,12 @@ static inline unsigned long at91_arch_identify(void)
 #define cpu_is_at91sam9260()    (0)
 #endif
+#ifdef CONFIG_ARCH_AT91SAM9G20
+#define cpu_is_at91sam9g20()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
+#else
+#define cpu_is_at91sam9g20()    (0)
+#endif
 #ifdef CONFIG_ARCH_AT91SAM9261
 #define cpu_is_at91sam9261()    (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
 #else
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 2c826d8247a3..016a3a3f6633 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -18,7 +18,7 @@
 #if defined(CONFIG_ARCH_AT91RM9200)
 #include <asm/arch/at91rm9200.h>
-#elif defined(CONFIG_ARCH_AT91SAM9260)
+#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
 #include <asm/arch/at91sam9260.h>
 #elif defined(CONFIG_ARCH_AT91SAM9261)
 #include <asm/arch/at91sam9261.h>
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index f1933b0fa43f..298d8313cdac 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -27,14 +27,29 @@
 #define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
-#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
+#elif defined(CONFIG_ARCH_AT91SAM9260)
+#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
+#define AT91SAM9_MASTER_CLOCK   90000000
+#else
+#define AT91SAM9_MASTER_CLOCK   99300000
+#endif
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+#elif defined(CONFIG_ARCH_AT91SAM9261)
 #define AT91SAM9_MASTER_CLOCK   99300000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 #elif defined(CONFIG_ARCH_AT91SAM9263)
+#if defined(CONFIG_MACH_USB_A9263)
+#define AT91SAM9_MASTER_CLOCK   90000000
+#else
 #define AT91SAM9_MASTER_CLOCK   99959500
+#endif
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 #elif defined(CONFIG_ARCH_AT91SAM9RL)
@@ -42,6 +57,11 @@
 #define AT91SAM9_MASTER_CLOCK   100000000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+#elif defined(CONFIG_ARCH_AT91SAM9G20)
+#define AT91SAM9_MASTER_CLOCK   132096000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 #elif defined(CONFIG_ARCH_AT91CAP9)
 #define AT91CAP9_MASTER_CLOCK   100000000
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h
index daad8ee2d194..74610c2c63d4 100644
--- a/include/asm-arm/arch-ebsa285/hardware.h
+++ b/include/asm-arm/arch-ebsa285/hardware.h
@@ -14,7 +14,6 @@
 #include <asm/arch/memory.h>
-#ifdef CONFIG_ARCH_FOOTBRIDGE
 /*   Virtual      Physical      Size
 * 0xff800000   0x40000000      1MB     X-Bus
 * 0xff000000   0x7c000000      1MB     PCI I/O space
@@ -50,31 +49,6 @@
 #define PCIMEM_SIZE             0x01000000
 #define PCIMEM_BASE             0xf0000000
-#elif defined(CONFIG_ARCH_CO285)
-/*
- * This is the COEBSA285 cut-down mapping
- */
-#define PCIMEM_SIZE             0x80000000
-#define PCIMEM_BASE             0x80000000
-#define WFLUSH_SIZE             0x01000000
-#define WFLUSH_BASE             0x7d000000
-#define ARMCSR_SIZE             0x00100000
-#define ARMCSR_BASE             0x7cf00000
-#define XBUS_SIZE               0x00020000
-#define XBUS_BASE               0x7cee0000
-#define PCIO_SIZE               0x00010000
-#define PCIO_BASE               0x7ced0000
-#else
-#error "Undefined footbridge architecture"
-#endif
 #define XBUS_LEDS               ((volatile unsigned char *)(XBUS_BASE + 0x12000))
 #define XBUS_LED_AMBER          (1 << 0)
 #define XBUS_LED_GREEN          (1 << 1)
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index cbd7ae64bcc9..9019a3bf5ab9 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -42,8 +42,6 @@ extern unsigned long __bus_to_virt(unsigned long);
 #endif
-#if defined(CONFIG_ARCH_FOOTBRIDGE)
 /* Task size and page offset at 3GB */
 #define TASK_SIZE               UL(0xbf000000)
 #define PAGE_OFFSET             UL(0xc0000000)
@@ -53,23 +51,6 @@ extern unsigned long __bus_to_virt(unsigned long);
 */
 #define FLUSH_BASE              0xf9000000
-#elif defined(CONFIG_ARCH_CO285)
-/* Task size and page offset at 1.5GB */
-#define TASK_SIZE               UL(0x5f000000)
-#define PAGE_OFFSET             UL(0x60000000)
-/*
- * Cache flushing area.
- */
-#define FLUSH_BASE              0x7e000000
-#else
-#error "Undefined footbridge architecture"
-#endif
 /*
 * Physical DRAM offset.
 */
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
index 02598200997d..e487d7e8c8a6 100644
--- a/include/asm-arm/arch-ebsa285/vmalloc.h
+++ b/include/asm-arm/arch-ebsa285/vmalloc.h
@@ -7,8 +7,4 @@
 */
-#ifdef CONFIG_ARCH_FOOTBRIDGE
 #define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
-#else
-#define VMALLOC_END       (PAGE_OFFSET + 0x20000000)
-#endif
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h
index adffb6acf42a..6542ca5e8c33 100644
--- a/include/asm-arm/arch-imx/hardware.h
+++ b/include/asm-arm/arch-imx/hardware.h
@@ -73,14 +73,6 @@
 */
 extern void imx_gpio_mode( int gpio_mode );
-/* get frequencies in Hz */
-extern unsigned int imx_get_system_clk(void);
-extern unsigned int imx_get_mcu_clk(void);
-extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
-extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12]         */
-extern unsigned int imx_get_perclk3(void); /* SSI                      */
-extern unsigned int imx_get_hclk(void);    /* SDRAM, CSI, Memory Stick,*/
-                                           /* I2C, DMA                 */
 #endif
 #define MAXIRQNUM                       62
diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h
index 5b1066da4e1f..44d89c35539a 100644
--- a/include/asm-arm/arch-imx/imx-dma.h
+++ b/include/asm-arm/arch-imx/imx-dma.h
@@ -88,7 +88,7 @@ int imx_dma_request(imx_dmach_t dma_ch, const char *name);
 void imx_dma_free(imx_dmach_t dma_ch);
-int imx_dma_request_by_prio(imx_dmach_t *pdma_ch, const char *name, imx_dma_prio prio);
+imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio);
 #endif  /* _ASM_ARCH_IMX_DMA_H */
diff --git a/include/asm-arm/arch-imx/imx-uart.h b/include/asm-arm/arch-imx/imx-uart.h
index 3a685e1780ea..d54eb1d48026 100644
--- a/include/asm-arm/arch-imx/imx-uart.h
+++ b/include/asm-arm/arch-imx/imx-uart.h
@@ -4,6 +4,8 @@
 #define IMXUART_HAVE_RTSCTS (1<<0)
 struct imxuart_platform_data {
+        int (*init)(struct platform_device *pdev);
+        void (*exit)(struct platform_device *pdev);
        unsigned int flags;
 };
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
index 2e15da53ff79..d79846fbb394 100644
--- a/include/asm-arm/arch-iop13xx/dma.h
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -1,3 +1,3 @@
 #ifndef _IOP13XX_DMA_H
-#define _IOP13XX_DMA_H_
+#define _IOP13XX_DMA_H
 #endif
diff --git a/include/asm-arm/arch-iop32x/gpio.h b/include/asm-arm/arch-iop32x/gpio.h
new file mode 100644
index 000000000000..708f4ec9db1d
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_IOP32X_GPIO_H
+#define __ASM_ARCH_IOP32X_GPIO_H
+#include <asm/hardware/iop3xx-gpio.h>
+#endif
diff --git a/include/asm-arm/arch-iop33x/gpio.h b/include/asm-arm/arch-iop33x/gpio.h
new file mode 100644
index 000000000000..ddd55bba9bb9
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_IOP33X_GPIO_H
+#define __ASM_ARCH_IOP33X_GPIO_H
+#include <asm/hardware/iop3xx-gpio.h>
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/fsg.h b/include/asm-arm/arch-ixp4xx/fsg.h
new file mode 100644
index 000000000000..c0100cc7981c
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/fsg.h
@@ -0,0 +1,50 @@
+/*
+ * include/asm-arm/arch-ixp4xx/fsg.h
+ *
+ * Freecom FSG-3 platform specific definitions
+ *
+ * Author: Rod Whitby <rod@whitby.id.au>
+ * Author: Tomasz Chmielewski <mangoo@wpkg.org>
+ * Maintainers: http://www.nslu2-linux.org
+ *
+ * Based on coyote.h by
+ * Copyright 2004 (c) MontaVista, Software, Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+#define FSG_SDA_PIN             12
+#define FSG_SCL_PIN             13
+/*
+ * FSG PCI IRQs
+ */
+#define FSG_PCI_MAX_DEV         3
+#define FSG_PCI_IRQ_LINES       3
+/* PCI controller GPIO to IRQ pin mappings */
+#define FSG_PCI_INTA_PIN        6
+#define FSG_PCI_INTB_PIN        7
+#define FSG_PCI_INTC_PIN        5
+/* Buttons */
+#define FSG_SB_GPIO             4       /* sync button */
+#define FSG_RB_GPIO             9       /* reset button */
+#define FSG_UB_GPIO             10      /* usb button */
+/* LEDs */
+#define FSG_LED_WLAN_BIT        0
+#define FSG_LED_WAN_BIT         1
+#define FSG_LED_SATA_BIT        2
+#define FSG_LED_USB_BIT         4
+#define FSG_LED_RING_BIT        5
+#define FSG_LED_SYNC_BIT        7
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 73e8dc36f6a4..fa723a627854 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -45,5 +45,6 @@
 #include "nslu2.h"
 #include "nas100d.h"
 #include "dsmg600.h"
+#include "fsg.h"
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
index 11801605047b..674af4a84147 100644
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -128,4 +128,11 @@
 #define        IRQ_DSMG600_PCI_INTE    IRQ_IXP4XX_GPIO7
 #define        IRQ_DSMG600_PCI_INTF    IRQ_IXP4XX_GPIO6
+/*
+ * Freecom FSG-3 Board IRQs
+ */
+#define        IRQ_FSG_PCI_INTA        IRQ_IXP4XX_GPIO6
+#define        IRQ_FSG_PCI_INTB        IRQ_IXP4XX_GPIO7
+#define        IRQ_FSG_PCI_INTC        IRQ_IXP4XX_GPIO5
 #endif
diff --git a/include/asm-arm/arch-kirkwood/debug-macro.S b/include/asm-arm/arch-kirkwood/debug-macro.S
new file mode 100644
index 000000000000..f55fb8ad9ee4
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-kirkwood/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <asm/arch/kirkwood.h>
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =KIRKWOOD_REGS_PHYS_BASE
+        ldrne   \rx, =KIRKWOOD_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-kirkwood/dma.h b/include/asm-arm/arch-kirkwood/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-kirkwood/entry-macro.S b/include/asm-arm/arch-kirkwood/entry-macro.S
new file mode 100644
index 000000000000..fc6a43d9355c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/entry-macro.S
@@ -0,0 +1,40 @@
+/*
+ * include/asm-arm/arch-kirkwood/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Kirkwood platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/arch/kirkwood.h>
+        .macro  disable_fiq
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+        bne     1001f
+        @ if no low interrupts set, check high interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        mov     \irqnr, #63
+        ands    \irqstat, \irqstat, \tmp
+        @ find first active interrupt source
+1001:   clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/include/asm-arm/arch-kirkwood/hardware.h b/include/asm-arm/arch-kirkwood/hardware.h
new file mode 100644
index 000000000000..e695719771a5
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-kirkwood/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include "kirkwood.h"
+#define pcibios_assign_all_busses()     1
+#define PCIBIOS_MIN_IO                  0x00001000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
+#endif
diff --git a/include/asm-arm/arch-kirkwood/io.h b/include/asm-arm/arch-kirkwood/io.h
new file mode 100644
index 000000000000..0ef6e95f5d5b
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/io.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-kirkwood/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+#include "kirkwood.h"
+#define IO_SPACE_LIMIT          0xffffffff
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
+                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
+}
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-kirkwood/irqs.h b/include/asm-arm/arch-kirkwood/irqs.h
new file mode 100644
index 000000000000..2e7b5da6335c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/irqs.h
@@ -0,0 +1,63 @@
+/*
+ * include/asm-arm/arch-kirkwood/irqs.h
+ *
+ * IRQ definitions for Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+#include "kirkwood.h"   /* need GPIO_MAX */
+/*
+ * Low Interrupt Controller
+ */
+#define IRQ_KIRKWOOD_HIGH_SUM   0
+#define IRQ_KIRKWOOD_BRIDGE     1
+#define IRQ_KIRKWOOD_HOST2CPU   2
+#define IRQ_KIRKWOOD_CPU2HOST   3
+#define IRQ_KIRKWOOD_XOR_00     5
+#define IRQ_KIRKWOOD_XOR_01     6
+#define IRQ_KIRKWOOD_XOR_10     7
+#define IRQ_KIRKWOOD_XOR_11     8
+#define IRQ_KIRKWOOD_PCIE       9
+#define IRQ_KIRKWOOD_GE00_SUM   11
+#define IRQ_KIRKWOOD_GE01_SUM   15
+#define IRQ_KIRKWOOD_USB        19
+#define IRQ_KIRKWOOD_SATA       21
+#define IRQ_KIRKWOOD_CRYPTO     22
+#define IRQ_KIRKWOOD_SPI        23
+#define IRQ_KIRKWOOD_I2S        24
+#define IRQ_KIRKWOOD_TS_0       26
+#define IRQ_KIRKWOOD_SDIO       28
+#define IRQ_KIRKWOOD_TWSI       29
+#define IRQ_KIRKWOOD_AVB        30
+#define IRQ_KIRKWOOD_TDMI       31
+/*
+ * High Interrupt Controller
+ */
+#define IRQ_KIRKWOOD_UART_0     33
+#define IRQ_KIRKWOOD_UART_1     34
+#define IRQ_KIRKWOOD_GPIO_LOW_0_7       35
+#define IRQ_KIRKWOOD_GPIO_LOW_8_15      36
+#define IRQ_KIRKWOOD_GPIO_LOW_16_23     37
+#define IRQ_KIRKWOOD_GPIO_LOW_24_31     38
+#define IRQ_KIRKWOOD_GPIO_HIGH_0_7      39
+#define IRQ_KIRKWOOD_GPIO_HIGH_8_15     40
+#define IRQ_KIRKWOOD_GPIO_HIGH_16_23    41
+/*
+ * KIRKWOOD General Purpose Pins
+ */
+#define IRQ_KIRKWOOD_GPIO_START 64
+#define NR_GPIO_IRQS            GPIO_MAX
+#define NR_IRQS                 (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
+#endif
diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h
new file mode 100644
index 000000000000..bb31b315c350
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/kirkwood.h
@@ -0,0 +1,100 @@
+/*
+ * include/asm-arm/arch-kirkwood/kirkwood.h
+ *
+ * Generic definitions for Marvell Kirkwood SoC flavors:
+ *  88F6180, 88F6192 and 88F6281.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_KIRKWOOD_H
+#define __ASM_ARCH_KIRKWOOD_H
+/*
+ * Marvell Kirkwood address maps.
+ *
+ * phys
+ * e0000000     PCIe Memory space
+ * f1000000     on-chip peripheral registers
+ * f2000000     PCIe I/O space
+ * f3000000     NAND controller address window
+ *
+ * virt         phys            size
+ * fee00000     f1000000        1M      on-chip peripheral registers
+ * fef00000     f2000000        1M      PCIe I/O space
+ */
+#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf3000000
+#define KIRKWOOD_NAND_MEM_SIZE          SZ_64K /* 1K is sufficient, but 64K
+                                                * is the minimal window size
+                                                */
+#define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfef00000
+#define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
+#define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
+#define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
+#define KIRKWOOD_REGS_VIRT_BASE         0xfee00000
+#define KIRKWOOD_REGS_SIZE              SZ_1M
+#define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
+#define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
+/*
+ * MBUS bridge registers.
+ */
+#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
+#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define   CPU_RESET             0x00000002
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_LOW_OFF     0x0000
+#define   IRQ_MASK_LOW_OFF      0x0004
+#define   IRQ_CAUSE_HIGH_OFF    0x0010
+#define   IRQ_MASK_HIGH_OFF     0x0014
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+#define  L2_CONFIG_REG          (BRIDGE_VIRT_BASE | 0x0128)
+#define   L2_WRITETHROUGH       0x00000010
+/*
+ * Register Map
+ */
+#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
+#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
+#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
+#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
+#define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
+#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
+#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
+#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
+#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
+#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
+#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
+#define GPIO_MAX                50
+#endif
diff --git a/include/asm-arm/arch-kirkwood/memory.h b/include/asm-arm/arch-kirkwood/memory.h
new file mode 100644
index 000000000000..e5108f408ce6
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/memory.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-kirkwood/memory.h
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#define PHYS_OFFSET             UL(0x00000000)
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+#endif
diff --git a/include/asm-arm/arch-kirkwood/system.h b/include/asm-arm/arch-kirkwood/system.h
new file mode 100644
index 000000000000..8dde7e379855
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/system.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-kirkwood/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/arch/hardware.h>
+#include <asm/arch/kirkwood.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+        while (1)
+                ;
+}
+#endif
diff --git a/include/asm-arm/arch-kirkwood/timex.h b/include/asm-arm/arch-kirkwood/timex.h
new file mode 100644
index 000000000000..82122e134e3c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/timex.h
@@ -0,0 +1,11 @@
+/*
+ * include/asm-arm/arch-kirkwood/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define CLOCK_TICK_RATE         (100 * HZ)
+#define KIRKWOOD_TCLK           166666667
diff --git a/include/asm-arm/arch-kirkwood/uncompress.h b/include/asm-arm/arch-kirkwood/uncompress.h
new file mode 100644
index 000000000000..a9062b6d7680
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * include/asm-arm/arch-kirkwood/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/serial_reg.h>
+#include <asm/arch/kirkwood.h>
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+        base[UART_TX << 2] = c;
+}
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-kirkwood/vmalloc.h b/include/asm-arm/arch-kirkwood/vmalloc.h
new file mode 100644
index 000000000000..41852c6e77f3
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-kirkwood/vmalloc.h
+ */
+#define VMALLOC_END     0xfe800000
diff --git a/include/asm-arm/arch-loki/debug-macro.S b/include/asm-arm/arch-loki/debug-macro.S
new file mode 100644
index 000000000000..585502e96513
--- /dev/null
+++ b/include/asm-arm/arch-loki/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-loki/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <asm/arch/loki.h>
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =LOKI_REGS_PHYS_BASE
+        ldrne   \rx, =LOKI_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-loki/dma.h b/include/asm-arm/arch-loki/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-loki/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-loki/entry-macro.S b/include/asm-arm/arch-loki/entry-macro.S
new file mode 100644
index 000000000000..693257cdbeb8
--- /dev/null
+++ b/include/asm-arm/arch-loki/entry-macro.S
@@ -0,0 +1,30 @@
+/*
+ * include/asm-arm/arch-loki/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/arch/loki.h>
+        .macro  disable_fiq
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #IRQ_CAUSE_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_OFF]
+        mov     \irqnr, #0
+        ands    \irqstat, \irqstat, \tmp
+        clzne   \irqnr, \irqstat
+        rsbne   \irqnr, \irqnr, #31
+        .endm
diff --git a/include/asm-arm/arch-loki/hardware.h b/include/asm-arm/arch-loki/hardware.h
new file mode 100644
index 000000000000..f65b01c733b6
--- /dev/null
+++ b/include/asm-arm/arch-loki/hardware.h
@@ -0,0 +1,15 @@
+/*
+ * include/asm-arm/arch-loki/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include "loki.h"
+#endif
diff --git a/include/asm-arm/arch-loki/io.h b/include/asm-arm/arch-loki/io.h
new file mode 100644
index 000000000000..e7418a915e75
--- /dev/null
+++ b/include/asm-arm/arch-loki/io.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-loki/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+#include "loki.h"
+#define IO_SPACE_LIMIT          0xffffffff
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
+                                        + LOKI_PCIE0_IO_VIRT_BASE);
+}
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-loki/irqs.h b/include/asm-arm/arch-loki/irqs.h
new file mode 100644
index 000000000000..7e4971438072
--- /dev/null
+++ b/include/asm-arm/arch-loki/irqs.h
@@ -0,0 +1,58 @@
+/*
+ * include/asm-arm/arch-loki/irqs.h
+ *
+ * IRQ definitions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+#include "loki.h"       /* need GPIO_MAX */
+/*
+ * Interrupt Controller
+ */
+#define IRQ_LOKI_PCIE_A_CPU_DRBL        0
+#define IRQ_LOKI_CPU_PCIE_A_DRBL        1
+#define IRQ_LOKI_PCIE_B_CPU_DRBL        2
+#define IRQ_LOKI_CPU_PCIE_B_DRBL        3
+#define IRQ_LOKI_COM_A_ERR              6
+#define IRQ_LOKI_COM_A_IN               7
+#define IRQ_LOKI_COM_A_OUT              8
+#define IRQ_LOKI_COM_B_ERR              9
+#define IRQ_LOKI_COM_B_IN               10
+#define IRQ_LOKI_COM_B_OUT              11
+#define IRQ_LOKI_DMA_A                  12
+#define IRQ_LOKI_DMA_B                  13
+#define IRQ_LOKI_SAS_A                  14
+#define IRQ_LOKI_SAS_B                  15
+#define IRQ_LOKI_DDR                    16
+#define IRQ_LOKI_XOR                    17
+#define IRQ_LOKI_BRIDGE                 18
+#define IRQ_LOKI_PCIE_A_ERR             20
+#define IRQ_LOKI_PCIE_A_INT             21
+#define IRQ_LOKI_PCIE_B_ERR             22
+#define IRQ_LOKI_PCIE_B_INT             23
+#define IRQ_LOKI_GBE_A_INT              24
+#define IRQ_LOKI_GBE_B_INT              25
+#define IRQ_LOKI_DEV_ERR                26
+#define IRQ_LOKI_UART0                  27
+#define IRQ_LOKI_UART1                  28
+#define IRQ_LOKI_TWSI                   29
+#define IRQ_LOKI_GPIO_23_0              30
+#define IRQ_LOKI_GPIO_25_24             31
+/*
+ * Loki General Purpose Pins
+ */
+#define IRQ_LOKI_GPIO_START     32
+#define NR_GPIO_IRQS            GPIO_MAX
+#define NR_IRQS                 (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
+#endif
diff --git a/include/asm-arm/arch-loki/loki.h b/include/asm-arm/arch-loki/loki.h
new file mode 100644
index 000000000000..5dd05ee0a4e6
--- /dev/null
+++ b/include/asm-arm/arch-loki/loki.h
@@ -0,0 +1,97 @@
+/*
+ * include/asm-arm/arch-loki/loki.h
+ *
+ * Generic definitions for Marvell Loki (88RC8480) SoC flavors
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_LOKI_H
+#define __ASM_ARCH_LOKI_H
+/*
+ * Marvell Loki (88RC8480) address maps.
+ *
+ * phys
+ * d0000000     on-chip peripheral registers
+ * e0000000     PCIe 0 Memory space
+ * e8000000     PCIe 1 Memory space
+ * f0000000     PCIe 0 I/O space
+ * f0100000     PCIe 1 I/O space
+ *
+ * virt         phys            size
+ * fed00000     d0000000        1M      on-chip peripheral registers
+ * fee00000     f0000000        64K     PCIe 0 I/O space
+ * fef00000     f0100000        64K     PCIe 1 I/O space
+ */
+#define LOKI_REGS_PHYS_BASE             0xd0000000
+#define LOKI_REGS_VIRT_BASE             0xfed00000
+#define LOKI_REGS_SIZE                  SZ_1M
+#define LOKI_PCIE0_IO_PHYS_BASE         0xf0000000
+#define LOKI_PCIE0_IO_VIRT_BASE         0xfee00000
+#define LOKI_PCIE0_IO_BUS_BASE          0x00000000
+#define LOKI_PCIE0_IO_SIZE              SZ_64K
+#define LOKI_PCIE1_IO_PHYS_BASE         0xf0100000
+#define LOKI_PCIE1_IO_VIRT_BASE         0xfef00000
+#define LOKI_PCIE1_IO_BUS_BASE          0x00000000
+#define LOKI_PCIE1_IO_SIZE              SZ_64K
+#define LOKI_PCIE0_MEM_PHYS_BASE        0xe0000000
+#define LOKI_PCIE0_MEM_SIZE             SZ_128M
+#define LOKI_PCIE1_MEM_PHYS_BASE        0xe8000000
+#define LOKI_PCIE1_MEM_SIZE             SZ_128M
+/*
+ * Register Map
+ */
+#define DEV_BUS_PHYS_BASE       (LOKI_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (LOKI_REGS_VIRT_BASE | 0x10000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+#define BRIDGE_VIRT_BASE        (LOKI_REGS_VIRT_BASE | 0x20000)
+#define  BRIDGE_REG(x)          (BRIDGE_VIRT_BASE | (x))
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR 0x0004
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_OFF         0x0000
+#define   IRQ_MASK_OFF          0x0004
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+#define PCIE0_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x30000)
+#define PCIE1_VIRT_BASE         (LOKI_REGS_VIRT_BASE | 0x40000)
+#define SAS0_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x80000)
+#define SAS1_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0x90000)
+#define GE0_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xa0000)
+#define GE0_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xa0000)
+#define GE1_PHYS_BASE           (LOKI_REGS_PHYS_BASE | 0xb0000)
+#define GE1_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xb0000)
+#define DDR_VIRT_BASE           (LOKI_REGS_VIRT_BASE | 0xf0000)
+#define DDR_REG(x)              (DDR_VIRT_BASE | (x))
+#define GPIO_MAX                8
+#endif
diff --git a/include/asm-arm/arch-loki/memory.h b/include/asm-arm/arch-loki/memory.h
new file mode 100644
index 000000000000..835101e49875
--- /dev/null
+++ b/include/asm-arm/arch-loki/memory.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-loki/memory.h
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#define PHYS_OFFSET             UL(0x00000000)
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+#endif
diff --git a/include/asm-arm/arch-loki/system.h b/include/asm-arm/arch-loki/system.h
new file mode 100644
index 000000000000..a3568ac8ec35
--- /dev/null
+++ b/include/asm-arm/arch-loki/system.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-loki/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/arch/hardware.h>
+#include <asm/arch/loki.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+        while (1)
+                ;
+}
+#endif
diff --git a/include/asm-arm/arch-loki/timex.h b/include/asm-arm/arch-loki/timex.h
new file mode 100644
index 000000000000..940014f97cae
--- /dev/null
+++ b/include/asm-arm/arch-loki/timex.h
@@ -0,0 +1,11 @@
+/*
+ * include/asm-arm/arch-loki/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define CLOCK_TICK_RATE         (100 * HZ)
+#define LOKI_TCLK               180000000
diff --git a/include/asm-arm/arch-loki/uncompress.h b/include/asm-arm/arch-loki/uncompress.h
new file mode 100644
index 000000000000..89a0cf88d3a5
--- /dev/null
+++ b/include/asm-arm/arch-loki/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * include/asm-arm/arch-loki/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/serial_reg.h>
+#include <asm/arch/loki.h>
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+        base[UART_TX << 2] = c;
+}
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-loki/vmalloc.h b/include/asm-arm/arch-loki/vmalloc.h
new file mode 100644
index 000000000000..f5be06220491
--- /dev/null
+++ b/include/asm-arm/arch-loki/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-loki/vmalloc.h
+ */
+#define VMALLOC_END     0xfe800000
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
index 565430cfaa7e..e62a108b1857 100644
--- a/include/asm-arm/arch-msm/irqs.h
+++ b/include/asm-arm/arch-msm/irqs.h
@@ -15,6 +15,7 @@
 */
 #ifndef __ASM_ARCH_MSM_IRQS_H
+#define __ASM_ARCH_MSM_IRQS_H
 /* MSM ARM11 Interrupt Numbers */
 /* See 80-VE113-1 A, pp219-221     */
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h
index 154b23fb3599..8724487ab4c9 100644
--- a/include/asm-arm/arch-msm/timex.h
+++ b/include/asm-arm/arch-msm/timex.h
@@ -14,6 +14,7 @@
 */
 #ifndef __ASM_ARCH_MSM_TIMEX_H
+#define __ASM_ARCH_MSM_TIMEX_H
 #define CLOCK_TICK_RATE         1000000
diff --git a/include/asm-arm/arch-mv78xx0/debug-macro.S b/include/asm-arm/arch-mv78xx0/debug-macro.S
new file mode 100644
index 000000000000..d0595bd645e5
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * include/asm-arm/arch-mv78xx0/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <asm/arch/mv78xx0.h>
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =MV78XX0_REGS_PHYS_BASE
+        ldrne   \rx, =MV78XX0_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-mv78xx0/dma.h b/include/asm-arm/arch-mv78xx0/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-mv78xx0/entry-macro.S b/include/asm-arm/arch-mv78xx0/entry-macro.S
new file mode 100644
index 000000000000..e9a606b12669
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * include/asm-arm/arch-mv78xx0/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell MV78xx0 platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/arch/mv78xx0.h>
+        .macro  disable_fiq
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+        @ if no low interrupts set, check high interrupts
+        ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        moveq   \irqnr, #63
+        andeqs  \irqstat, \irqstat, \tmp
+        @ find first active interrupt source
+        clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/include/asm-arm/arch-mv78xx0/hardware.h b/include/asm-arm/arch-mv78xx0/hardware.h
new file mode 100644
index 000000000000..8e17926086c6
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-mv78xx0/hardware.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include "mv78xx0.h"
+#define pcibios_assign_all_busses()     1
+#define PCIBIOS_MIN_IO                  0x00001000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/io.h b/include/asm-arm/arch-mv78xx0/io.h
new file mode 100644
index 000000000000..415d4c98e3d1
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/io.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-mv78xx0/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+#include "mv78xx0.h"
+#define IO_SPACE_LIMIT          0xffffffff
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
+                                        + MV78XX0_PCIE_IO_VIRT_BASE(0));
+}
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/irqs.h b/include/asm-arm/arch-mv78xx0/irqs.h
new file mode 100644
index 000000000000..75930450cd65
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/irqs.h
@@ -0,0 +1,91 @@
+/*
+ * include/asm-arm/arch-mv78xx0/irqs.h
+ *
+ * IRQ definitions for Marvell MV78xx0 SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+#include "mv78xx0.h"    /* need GPIO_MAX */
+/*
+ * MV78xx0 Low Interrupt Controller
+ */
+#define IRQ_MV78XX0_ERR         0
+#define IRQ_MV78XX0_SPI         1
+#define IRQ_MV78XX0_I2C_0       2
+#define IRQ_MV78XX0_I2C_1       3
+#define IRQ_MV78XX0_IDMA_0      4
+#define IRQ_MV78XX0_IDMA_1      5
+#define IRQ_MV78XX0_IDMA_2      6
+#define IRQ_MV78XX0_IDMA_3      7
+#define IRQ_MV78XX0_TIMER_0     8
+#define IRQ_MV78XX0_TIMER_1     9
+#define IRQ_MV78XX0_TIMER_2     10
+#define IRQ_MV78XX0_TIMER_3     11
+#define IRQ_MV78XX0_UART_0      12
+#define IRQ_MV78XX0_UART_1      13
+#define IRQ_MV78XX0_UART_2      14
+#define IRQ_MV78XX0_UART_3      15
+#define IRQ_MV78XX0_USB_0       16
+#define IRQ_MV78XX0_USB_1       17
+#define IRQ_MV78XX0_USB_2       18
+#define IRQ_MV78XX0_CRYPTO      19
+#define IRQ_MV78XX0_SDIO_0      20
+#define IRQ_MV78XX0_SDIO_1      21
+#define IRQ_MV78XX0_XOR_0       22
+#define IRQ_MV78XX0_XOR_1       23
+#define IRQ_MV78XX0_I2S_0       24
+#define IRQ_MV78XX0_I2S_1       25
+#define IRQ_MV78XX0_SATA        26
+#define IRQ_MV78XX0_TDMI        27
+/*
+ * MV78xx0 High Interrupt Controller
+ */
+#define IRQ_MV78XX0_PCIE_00     32
+#define IRQ_MV78XX0_PCIE_01     33
+#define IRQ_MV78XX0_PCIE_02     34
+#define IRQ_MV78XX0_PCIE_03     35
+#define IRQ_MV78XX0_PCIE_10     36
+#define IRQ_MV78XX0_PCIE_11     37
+#define IRQ_MV78XX0_PCIE_12     38
+#define IRQ_MV78XX0_PCIE_13     39
+#define IRQ_MV78XX0_GE00_SUM    40
+#define IRQ_MV78XX0_GE00_RX     41
+#define IRQ_MV78XX0_GE00_TX     42
+#define IRQ_MV78XX0_GE00_MISC   43
+#define IRQ_MV78XX0_GE01_SUM    44
+#define IRQ_MV78XX0_GE01_RX     45
+#define IRQ_MV78XX0_GE01_TX     46
+#define IRQ_MV78XX0_GE01_MISC   47
+#define IRQ_MV78XX0_GE10_SUM    48
+#define IRQ_MV78XX0_GE10_RX     49
+#define IRQ_MV78XX0_GE10_TX     50
+#define IRQ_MV78XX0_GE10_MISC   51
+#define IRQ_MV78XX0_GE11_SUM    52
+#define IRQ_MV78XX0_GE11_RX     53
+#define IRQ_MV78XX0_GE11_TX     54
+#define IRQ_MV78XX0_GE11_MISC   55
+#define IRQ_MV78XX0_GPIO_0_7    56
+#define IRQ_MV78XX0_GPIO_8_15   57
+#define IRQ_MV78XX0_GPIO_16_23  58
+#define IRQ_MV78XX0_GPIO_24_31  59
+#define IRQ_MV78XX0_DB_IN       60
+#define IRQ_MV78XX0_DB_OUT      61
+/*
+ * MV78XX0 General Purpose Pins
+ */
+#define IRQ_MV78XX0_GPIO_START  64
+#define NR_GPIO_IRQS            GPIO_MAX
+#define NR_IRQS                 (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/memory.h b/include/asm-arm/arch-mv78xx0/memory.h
new file mode 100644
index 000000000000..721a6b185b91
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/memory.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-mv78xx0/memory.h
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#define PHYS_OFFSET             UL(0x00000000)
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/mv78xx0.h b/include/asm-arm/arch-mv78xx0/mv78xx0.h
new file mode 100644
index 000000000000..9f5d83c73faa
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/mv78xx0.h
@@ -0,0 +1,126 @@
+/*
+ * include/asm-arm/arch-mv78xx0/mv78xx0.h
+ *
+ * Generic definitions for Marvell MV78xx0 SoC flavors:
+ *  MV781x0 and MV782x0.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_MV78XX0_H
+#define __ASM_ARCH_MV78XX0_H
+/*
+ * Marvell MV78xx0 address maps.
+ *
+ * phys
+ * c0000000     PCIe Memory space
+ * f0800000     PCIe #0 I/O space
+ * f0900000     PCIe #1 I/O space
+ * f0a00000     PCIe #2 I/O space
+ * f0b00000     PCIe #3 I/O space
+ * f0c00000     PCIe #4 I/O space
+ * f0d00000     PCIe #5 I/O space
+ * f0e00000     PCIe #6 I/O space
+ * f0f00000     PCIe #7 I/O space
+ * f1000000     on-chip peripheral registers
+ *
+ * virt         phys            size
+ * fe400000     f102x000        16K     core-specific peripheral registers
+ * fe700000     f0800000        1M      PCIe #0 I/O space
+ * fe800000     f0900000        1M      PCIe #1 I/O space
+ * fe900000     f0a00000        1M      PCIe #2 I/O space
+ * fea00000     f0b00000        1M      PCIe #3 I/O space
+ * feb00000     f0c00000        1M      PCIe #4 I/O space
+ * fec00000     f0d00000        1M      PCIe #5 I/O space
+ * fed00000     f0e00000        1M      PCIe #6 I/O space
+ * fee00000     f0f00000        1M      PCIe #7 I/O space
+ * fef00000     f1000000        1M      on-chip peripheral registers
+ */
+#define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
+#define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
+#define MV78XX0_CORE_REGS_VIRT_BASE     0xfe400000
+#define MV78XX0_CORE_REGS_SIZE          SZ_16K
+#define MV78XX0_PCIE_IO_PHYS_BASE(i)    (0xf0800000 + ((i) << 20))
+#define MV78XX0_PCIE_IO_VIRT_BASE(i)    (0xfe700000 + ((i) << 20))
+#define MV78XX0_PCIE_IO_SIZE            SZ_1M
+#define MV78XX0_REGS_PHYS_BASE          0xf1000000
+#define MV78XX0_REGS_VIRT_BASE          0xfef00000
+#define MV78XX0_REGS_SIZE               SZ_1M
+#define MV78XX0_PCIE_MEM_PHYS_BASE      0xc0000000
+#define MV78XX0_PCIE_MEM_SIZE           0x30000000
+/*
+ * Core-specific peripheral registers.
+ */
+#define BRIDGE_VIRT_BASE        (MV78XX0_CORE_REGS_VIRT_BASE)
+#define  CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define   L2_WRITETHROUGH       0x00020000
+#define  RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define   SOFT_RESET_OUT_EN     0x00000004
+#define  SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define   SOFT_RESET            0x00000001
+#define  BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define  BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define   BRIDGE_INT_TIMER0     0x0002
+#define   BRIDGE_INT_TIMER1     0x0004
+#define   BRIDGE_INT_TIMER1_CLR (~0x0004)
+#define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_LOW_OFF     0x0004
+#define   IRQ_CAUSE_HIGH_OFF    0x0008
+#define   IRQ_MASK_LOW_OFF      0x0010
+#define   IRQ_MASK_HIGH_OFF     0x0014
+#define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
+/*
+ * Register Map
+ */
+#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1700)
+#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
+#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
+#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
+#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
+#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
+#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
+#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
+#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
+#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
+#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
+#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
+#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
+#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
+#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
+#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
+#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
+#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
+#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
+#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
+#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
+#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
+#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+#define GPIO_MAX                32
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/system.h b/include/asm-arm/arch-mv78xx0/system.h
new file mode 100644
index 000000000000..7eb47d376db9
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/system.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-arm/arch-mv78xx0/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/arch/hardware.h>
+#include <asm/arch/mv78xx0.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+        while (1)
+                ;
+}
+#endif
diff --git a/include/asm-arm/arch-mv78xx0/timex.h b/include/asm-arm/arch-mv78xx0/timex.h
new file mode 100644
index 000000000000..a854b1ccbd01
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/timex.h
@@ -0,0 +1,9 @@
+/*
+ * include/asm-arm/arch-mv78xx0/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/include/asm-arm/arch-mv78xx0/uncompress.h b/include/asm-arm/arch-mv78xx0/uncompress.h
new file mode 100644
index 000000000000..3bfe0a293ef7
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/uncompress.h
@@ -0,0 +1,47 @@
+/*
+ * include/asm-arm/arch-mv78xx0/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/serial_reg.h>
+#include <asm/arch/mv78xx0.h>
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
+static void putc(const char c)
+{
+        unsigned char *base = SERIAL_BASE;
+        int i;
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
+                barrier();
+        }
+        base[UART_TX << 2] = c;
+}
+static void flush(void)
+{
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-mv78xx0/vmalloc.h b/include/asm-arm/arch-mv78xx0/vmalloc.h
new file mode 100644
index 000000000000..f2c512197579
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-mv78xx0/vmalloc.h
+ */
+#define VMALLOC_END     0xfe000000
diff --git a/include/asm-arm/arch-mxc/board-mx27ads.h b/include/asm-arm/arch-mxc/board-mx27ads.h
new file mode 100644
index 000000000000..61e66dac90ef
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx27ads.h
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+/* external interrupt multiplexer */
+#define MXC_EXP_IO_BASE         (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
+#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
+#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
+#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
+#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
+#define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
+                                MXC_MAX_VIRTUAL_INTS)
+/*
+ * MXC UART EVB board level configurations
+ */
+#define MXC_LL_EXTUART_PADDR    (CS4_BASE_ADDR + 0x20000)
+#define MXC_LL_EXTUART_VADDR    (CS4_BASE_ADDR_VIRT + 0x20000)
+#define MXC_LL_EXTUART_16BIT_BUS
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
+/*
+ * @name Memory Size parameters
+ */
+/*
+ * Size of SDRAM memory
+ */
+#define SDRAM_MEM_SIZE          SZ_128M
+/*
+ * PBC Controller parameters
+ */
+/*
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS        0xEB000000
+#define PBC_REG_ADDR(offset)    (PBC_BASE_ADDRESS + (offset))
+/*
+ * PBC Interupt name definitions
+ */
+#define PBC_GPIO1_0  0
+#define PBC_GPIO1_1  1
+#define PBC_GPIO1_2  2
+#define PBC_GPIO1_3  3
+#define PBC_GPIO1_4  4
+#define PBC_GPIO1_5  5
+#define PBC_INTR_MAX_NUM 6
+#define PBC_INTR_SHARED_MAX_NUM 8
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH             0
+/* Offsets for the PBC Controller register */
+/*
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
+/*PBC_ADDR_SH
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
+/*
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
+/*
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
+/*
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
+/*
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
+/*
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Status.
+ */
+#define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Control Set.
+ */
+#define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Control Clear.
+ */
+#define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
+/* PBC Board Version Register bit definition */
+#define PBC_VERSION_ADS         0x8000  /* Bit15=1 means version for ads */
+#define PBC_VERSION_EVB_REVB    0x4000  /* BIT14=1 means version for evb revb */
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_ERST         0x0001  /* Ethernet Reset */
+#define PBC_BCTRL1_URST         0x0002  /* Reset External UART controller */
+#define PBC_BCTRL1_FRST         0x0004  /* FEC Reset */
+#define PBC_BCTRL1_ESLEEP       0x0010  /* Enable ethernet Sleep */
+#define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
+/* PBC Board Control Register 2 bit definitions */
+#define PBC_BCTRL2_VCC_EN       0x0004  /*   Enable VCC */
+#define PBC_BCTRL2_VPP_EN       0x0008  /*   Enable Vpp */
+#define PBC_BCTRL2_ATAFEC_EN    0X0010
+#define PBC_BCTRL2_ATAFEC_SEL   0X0020
+#define PBC_BCTRL2_ATA_EN       0X0040
+#define PBC_BCTRL2_IRDA_SD      0X0080
+#define PBC_BCTRL2_IRDA_EN      0X0100
+#define PBC_BCTRL2_CCTL10       0X0200
+#define PBC_BCTRL2_CCTL11       0X0400
+/* PBC Board Control Register 3 bit definitions */
+#define PBC_BCTRL3_HSH_EN       0X0020
+#define PBC_BCTRL3_FSH_MOD      0X0040
+#define PBC_BCTRL3_OTG_HS_EN    0X0080
+#define PBC_BCTRL3_OTG_VBUS_EN  0X0100
+#define PBC_BCTRL3_FSH_VBUS_EN  0X0200
+#define PBC_BCTRL3_USB_OTG_ON   0X0800
+#define PBC_BCTRL3_USB_FSH_ON   0X1000
+/* PBC Board Control Register 4 bit definitions */
+#define PBC_BCTRL4_REGEN_SEL    0X0001
+#define PBC_BCTRL4_USER_OFF     0X0002
+#define PBC_BCTRL4_VIB_EN       0X0004
+#define PBC_BCTRL4_PWRGT1_EN    0X0008
+#define PBC_BCTRL4_PWRGT2_EN    0X0010
+#define PBC_BCTRL4_STDBY_PRI    0X0020
+#ifndef __ASSEMBLY__
+/*
+ * Enumerations for SD cards and memory stick card. This corresponds to
+ * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
+ */
+enum mxc_card_no {
+        MXC_CARD_SD2 = 0,
+        MXC_CARD_SD3,
+        MXC_CARD_MS,
+        MXC_CARD_SD1,
+        MXC_CARD_MIN = MXC_CARD_SD2,
+        MXC_CARD_MAX = MXC_CARD_SD1,
+};
+#endif
+#define MXC_CPLD_VER_1_50       0x01
+/*
+ * PBC BSTAT Register bit definitions
+ */
+#define PBC_BSTAT_PRI_INT       0X0001
+#define PBC_BSTAT_USB_BYP       0X0002
+#define PBC_BSTAT_ATA_IOCS16    0X0004
+#define PBC_BSTAT_ATA_CBLID     0X0008
+#define PBC_BSTAT_ATA_DASP      0X0010
+#define PBC_BSTAT_PWR_RDY       0X0020
+#define PBC_BSTAT_SD3_WP        0X0100
+#define PBC_BSTAT_SD2_WP        0X0200
+#define PBC_BSTAT_SD1_WP        0X0400
+#define PBC_BSTAT_SD3_DET       0X0800
+#define PBC_BSTAT_SD2_DET       0X1000
+#define PBC_BSTAT_SD1_DET       0X2000
+#define PBC_BSTAT_MS_DET        0X4000
+#define PBC_BSTAT_SD3_DET_BIT   11
+#define PBC_BSTAT_SD2_DET_BIT   12
+#define PBC_BSTAT_SD1_DET_BIT   13
+#define PBC_BSTAT_MS_DET_BIT    14
+#define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
+                                 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
+                                 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
+                                 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
+                                        0x0))))
+/*
+ * PBC UART Control Register bit definitions
+ */
+#define PBC_UCTRL_DCE_DCD       0X0001
+#define PBC_UCTRL_DCE_DSR       0X0002
+#define PBC_UCTRL_DCE_RI        0X0004
+#define PBC_UCTRL_DTE_DTR       0X0100
+/*
+ * PBC UART Status Register bit definitions
+ */
+#define PBC_USTAT_DTE_DCD       0X0001
+#define PBC_USTAT_DTE_DSR       0X0002
+#define PBC_USTAT_DTE_RI        0X0004
+#define PBC_USTAT_DCE_DTR       0X0100
+/*
+ * PBC Interupt mask register bit definitions
+ */
+#define PBC_INTR_SD3_R_EN_BIT   4
+#define PBC_INTR_SD2_R_EN_BIT   0
+#define PBC_INTR_SD1_R_EN_BIT   6
+#define PBC_INTR_MS_R_EN_BIT    5
+#define PBC_INTR_SD3_EN_BIT     13
+#define PBC_INTR_SD2_EN_BIT     12
+#define PBC_INTR_MS_EN_BIT      14
+#define PBC_INTR_SD1_EN_BIT     15
+#define PBC_INTR_SD2_R_EN       0x0001
+#define PBC_INTR_LOW_BAT        0X0002
+#define PBC_INTR_OTG_FSOVER     0X0004
+#define PBC_INTR_FSH_OVER       0X0008
+#define PBC_INTR_SD3_R_EN       0x0010
+#define PBC_INTR_MS_R_EN        0x0020
+#define PBC_INTR_SD1_R_EN       0x0040
+#define PBC_INTR_FEC_INT        0X0080
+#define PBC_INTR_ENET_INT       0X0100
+#define PBC_INTR_OTGFS_INT      0X0200
+#define PBC_INTR_XUART_INT      0X0400
+#define PBC_INTR_CCTL12         0X0800
+#define PBC_INTR_SD2_EN         0x1000
+#define PBC_INTR_SD3_EN         0x2000
+#define PBC_INTR_MS_EN          0x4000
+#define PBC_INTR_SD1_EN         0x8000
+/* For interrupts like xuart, enet etc */
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
+#define MXC_MAX_EXP_IO_LINES    16
+/*
+ * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
+ *
+ */
+#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)
+/*
+ * This is System IRQ used by CS8900A for interrupt generation
+ * taken from platform.h
+ */
+#define CS8900AIRQ              EXPIO_INT_ENET_INT
+/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
+#define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)
+#define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)
+/*
+* This is used to detect if the CPLD version is for mx27 evb board rev-a
+*/
+#define PBC_CPLD_VERSION_IS_REVA() \
+        ((__raw_readw(PBC_VERSION_REG) & \
+        (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
+        == 0)
+/* This is used to active or inactive ata signal in CPLD .
+ *  It is dependent with hardware
+ */
+#define PBC_ATA_SIGNAL_ACTIVE() \
+        __raw_writew(           \
+                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
+                PBC_BCTRL2_CLEAR_REG)
+#define PBC_ATA_SIGNAL_INACTIVE() \
+        __raw_writew(  \
+                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
+                PBC_BCTRL2_SET_REG)
+#define MXC_BD_LED1             (1 << 5)
+#define MXC_BD_LED2             (1 << 6)
+#define MXC_BD_LED_ON(led) \
+        __raw_writew(led, PBC_BCTRL1_SET_REG)
+#define MXC_BD_LED_OFF(led) \
+        __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
+/* to determine the correct external crystal reference */
+#define CKIH_27MHZ_BIT_SET      (1 << 3)
+#endif                          /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
index 8590127760a8..1bc6fb0f9a83 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -109,4 +109,9 @@
 #define MXC_MAX_EXP_IO_LINES    16
+/* mandatory for CONFIG_LL_DEBUG */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31lite.h b/include/asm-arm/arch-mxc/board-mx31lite.h
new file mode 100644
index 000000000000..e4e5cf5ad7db
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31lite.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+#define MXC_MAX_EXP_IO_LINES    16
+/*
+ * Memory Size parameters
+ */
+/*
+ * Size of SDRAM memory
+ */
+#define SDRAM_MEM_SIZE          SZ_128M
+/*
+ * Size of MBX buffer memory
+ */
+#define MXC_MBX_MEM_SIZE        SZ_16M
+/*
+ * Size of memory available to kernel
+ */
+#define MEM_SIZE                (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE)
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-pcm037.h b/include/asm-arm/arch-mxc/board-pcm037.h
new file mode 100644
index 000000000000..82232ba3c8fc
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm037.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
+#define __ASM_ARCH_MXC_BOARD_PCM037_H__
+/* mandatory for CONFIG_LL_DEBUG */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/include/asm-arm/arch-mxc/board-pcm038.h b/include/asm-arm/arch-mxc/board-pcm038.h
new file mode 100644
index 000000000000..750c62afd90f
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm038.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
+#define __ASM_ARCH_MXC_BOARD_PCM038_H__
+/* mandatory for CONFIG_LL_DEBUG */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
+#ifndef __ASSEMBLY__
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own baseboard init function and call it from
+ * inside pcm038_init().
+ *
+ * This example here is for the development board. Refer pcm970-baseboard.c
+ */
+extern void pcm970_baseboard_init(void);
+#endif
+#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/include/asm-arm/arch-mxc/clock.h b/include/asm-arm/arch-mxc/clock.h
new file mode 100644
index 000000000000..24caa2b7c91d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/clock.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#ifndef __ASM_ARCH_MXC_CLOCK_H__
+#define __ASM_ARCH_MXC_CLOCK_H__
+#ifndef __ASSEMBLY__
+#include <linux/list.h>
+struct module;
+struct clk {
+        struct list_head node;
+        struct module *owner;
+        const char *name;
+        int id;
+        /* Source clock this clk depends on */
+        struct clk *parent;
+        /* Secondary clock to enable/disable with this clock */
+        struct clk *secondary;
+        /* Reference count of clock enable/disable */
+        __s8 usecount;
+        /* Register bit position for clock's enable/disable control. */
+        u8 enable_shift;
+        /* Register address for clock's enable/disable control. */
+        u32 enable_reg;
+        u32 flags;
+        /* get the current clock rate (always a fresh value) */
+        unsigned long (*get_rate) (struct clk *);
+        /* Function ptr to set the clock to a new rate. The rate must match a
+           supported rate returned from round_rate. Leave blank if clock is not
+           programmable */
+        int (*set_rate) (struct clk *, unsigned long);
+        /* Function ptr to round the requested clock rate to the nearest
+           supported rate that is less than or equal to the requested rate. */
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        /* Function ptr to enable the clock. Leave blank if clock can not
+           be gated. */
+        int (*enable) (struct clk *);
+        /* Function ptr to disable the clock. Leave blank if clock can not
+           be gated. */
+        void (*disable) (struct clk *);
+        /* Function ptr to set the parent clock of the clock. */
+        int (*set_parent) (struct clk *, struct clk *);
+};
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
index 23b4350edbd6..a6d2e24aab15 100644
--- a/include/asm-arm/arch-mxc/common.h
+++ b/include/asm-arm/arch-mxc/common.h
@@ -11,10 +11,10 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
-struct sys_timer;
 extern void mxc_map_io(void);
 extern void mxc_init_irq(void);
-extern struct sys_timer mxc_timer;
+extern void mxc_timer_init(const char *clk_timer);
+extern int mxc_clocks_init(unsigned long fref);
+extern int mxc_register_gpios(void);
 #endif
diff --git a/include/asm-arm/arch-mxc/debug-macro.S b/include/asm-arm/arch-mxc/debug-macro.S
new file mode 100644
index 000000000000..575087f8561a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/debug-macro.S
@@ -0,0 +1,49 @@
+/* linux/include/asm-arm/arch-imx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <asm/arch/hardware.h>
+#ifdef CONFIG_MACH_MX31ADS
+#include <asm/arch/board-mx31ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM037
+#include <asm/arch/board-pcm037.h>
+#endif
+#ifdef CONFIG_MACH_MX31LITE
+#include <asm/arch/board-mx31lite.h>
+#endif
+#ifdef CONFIG_MACH_MX27ADS
+#include <asm/arch/board-mx27ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM038
+#include <asm/arch/board-pcm038.h>
+#endif
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                ldreq   \rx, =MXC_LL_UART_PADDR @ physical
+                ldrne   \rx, =MXC_LL_UART_VADDR @ virtual
+                .endm
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x40]       @ TXDATA
+                .endm
+                .macro  waituart,rd,rx
+                .endm
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x98]       @ SR2
+                tst     \rd, #1 << 3            @ TXDC
+                beq     1002b                   @ wait until transmit done
+                .endm
diff --git a/include/asm-arm/arch-mxc/gpio.h b/include/asm-arm/arch-mxc/gpio.h
new file mode 100644
index 000000000000..d393e15f5a6b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __ASM_ARCH_MXC_GPIO_H__
+#define __ASM_ARCH_MXC_GPIO_H__
+#include <asm/hardware.h>
+#include <asm-generic/gpio.h>
+/* use gpiolib dispatchers */
+#define gpio_get_value          __gpio_get_value
+#define gpio_set_value          __gpio_set_value
+#define gpio_cansleep           __gpio_cansleep
+#define gpio_to_irq(gpio)       (MXC_MAX_INT_LINES + (gpio))
+#define irq_to_gpio(irq)        ((irq) - MXC_MAX_INT_LINES)
+struct mxc_gpio_port {
+        void __iomem *base;
+        int irq;
+        int virtual_irq_start;
+        struct gpio_chip chip;
+};
+int mxc_gpio_init(struct mxc_gpio_port*, int);
+#endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
index e87ff0679d5e..37cddbaaade7 100644
--- a/include/asm-arm/arch-mxc/hardware.h
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -1,11 +1,20 @@
 /*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
-/*
+ * This program is free software; you can redistribute it and/or
- * This program is free software; you can redistribute it and/or modify
+ * modify it under the terms of the GNU General Public License
- * it under the terms of the GNU General Public License version 2 as
+ * as published by the Free Software Foundation; either version 2
- * published by the Free Software Foundation.
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
 */
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
@@ -17,15 +26,12 @@
 # include <asm/arch/mx31.h>
 #endif
-#include <asm/arch/mxc.h>
+#ifdef CONFIG_ARCH_MX2
+# ifdef CONFIG_MACH_MX27
-/*
+#  include <asm/arch/mx27.h>
- * ---------------------------------------------------------------------------
+# endif
- * Board specific defines
- * ---------------------------------------------------------------------------
- */
-#ifdef CONFIG_MACH_MX31ADS
-# include <asm/arch/board-mx31ads.h>
 #endif
+#include <asm/arch/mxc.h>
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/iim.h b/include/asm-arm/arch-mxc/iim.h
new file mode 100644
index 000000000000..315bffadafda
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iim.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#ifndef __ASM_ARCH_MXC_IIM_H__
+#define __ASM_ARCH_MXC_IIM_H__
+/* Register offsets */
+#define MXC_IIMSTAT             0x0000
+#define MXC_IIMSTATM            0x0004
+#define MXC_IIMERR              0x0008
+#define MXC_IIMEMASK            0x000C
+#define MXC_IIMFCTL             0x0010
+#define MXC_IIMUA               0x0014
+#define MXC_IIMLA               0x0018
+#define MXC_IIMSDAT             0x001C
+#define MXC_IIMPREV             0x0020
+#define MXC_IIMSREV             0x0024
+#define MXC_IIMPRG_P            0x0028
+#define MXC_IIMSCS0             0x002C
+#define MXC_IIMSCS1             0x0030
+#define MXC_IIMSCS2             0x0034
+#define MXC_IIMSCS3             0x0038
+#define MXC_IIMFBAC0            0x0800
+#define MXC_IIMJAC              0x0804
+#define MXC_IIMHWV1             0x0808
+#define MXC_IIMHWV2             0x080C
+#define MXC_IIMHAB0             0x0810
+#define MXC_IIMHAB1             0x0814
+/* Definitions for i.MX27 TO2 */
+#define MXC_IIMMAC              0x0814
+#define MXC_IIMPREV_FUSE        0x0818
+#define MXC_IIMSREV_FUSE        0x081C
+#define MXC_IIMSJC_CHALL_0      0x0820
+#define MXC_IIMSJC_CHALL_7      0x083C
+#define MXC_IIMFB0UC17          0x0840
+#define MXC_IIMFB0UC255         0x0BFC
+#define MXC_IIMFBAC1            0x0C00
+/* Definitions for i.MX27 TO2 */
+#define MXC_IIMSUID             0x0C04
+#define MXC_IIMKEY0             0x0C04
+#define MXC_IIMKEY20            0x0C54
+#define MXC_IIMSJC_RESP_0       0x0C58
+#define MXC_IIMSJC_RESP_7       0x0C74
+#define MXC_IIMFB1UC30          0x0C78
+#define MXC_IIMFB1UC255         0x0FFC
+/* Bit definitions */
+#define MXC_IIMHWV1_WLOCK               (0x1 << 7)
+#define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
+#define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
+#define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
+#define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
+#define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
+#define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)
+#define MXC_IIMHWV2_WLOCK               (0x1 << 7)
+#define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
+#define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)
+#endif /* __ASM_ARCH_MXC_IIM_H__ */
diff --git a/include/asm-arm/arch-mxc/imx-uart.h b/include/asm-arm/arch-mxc/imx-uart.h
new file mode 100644
index 000000000000..83fb72c4048a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/imx-uart.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef ASMARM_ARCH_UART_H
+#define ASMARM_ARCH_UART_H
+#define IMXUART_HAVE_RTSCTS (1<<0)
+struct imxuart_platform_data {
+        int (*init)(struct platform_device *pdev);
+        int (*exit)(struct platform_device *pdev);
+        unsigned int flags;
+};
+int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata);
+#endif
diff --git a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
new file mode 100644
index 000000000000..076d37b38eb2
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
@@ -0,0 +1,372 @@
+/*
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef _MXC_GPIO_MX1_MX2_H
+#define _MXC_GPIO_MX1_MX2_H
+#include <linux/io.h>
+#define MXC_GPIO_ALLOC_MODE_NORMAL      0
+#define MXC_GPIO_ALLOC_MODE_NO_ALLOC    1
+#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC   2
+#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY  4
+#define MXC_GPIO_ALLOC_MODE_RELEASE     8
+/*
+ *  GPIO Module and I/O Multiplexer
+ *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
+ */
+#define VA_GPIO_BASE    IO_ADDRESS(GPIO_BASE_ADDR)
+#define MXC_DDIR(x)    (0x00 + ((x) << 8))
+#define MXC_OCR1(x)    (0x04 + ((x) << 8))
+#define MXC_OCR2(x)    (0x08 + ((x) << 8))
+#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
+#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
+#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
+#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
+#define MXC_DR(x)      (0x1c + ((x) << 8))
+#define MXC_GIUS(x)    (0x20 + ((x) << 8))
+#define MXC_SSR(x)     (0x24 + ((x) << 8))
+#define MXC_ICR1(x)    (0x28 + ((x) << 8))
+#define MXC_ICR2(x)    (0x2c + ((x) << 8))
+#define MXC_IMR(x)     (0x30 + ((x) << 8))
+#define MXC_ISR(x)     (0x34 + ((x) << 8))
+#define MXC_GPR(x)     (0x38 + ((x) << 8))
+#define MXC_SWR(x)     (0x3c + ((x) << 8))
+#define MXC_PUEN(x)    (0x40 + ((x) << 8))
+#ifdef CONFIG_ARCH_MX1
+# define GPIO_PORT_MAX  3
+#endif
+#ifdef CONFIG_ARCH_MX2
+# define GPIO_PORT_MAX  5
+#endif
+#ifndef GPIO_PORT_MAX
+# error "GPIO config port count unknown!"
+#endif
+#define GPIO_PIN_MASK 0x1f
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+#define GPIO_OUT   (1 << 8)
+#define GPIO_IN    (0 << 8)
+#define GPIO_PUEN  (1 << 9)
+#define GPIO_PF    (1 << 10)
+#define GPIO_AF    (1 << 11)
+#define GPIO_OCR_SHIFT 12
+#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN   (0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN   (1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN   (2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO  (3 << GPIO_OCR_SHIFT)
+#define GPIO_AOUT_SHIFT 14
+#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT     (0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0   (2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1   (3 << GPIO_AOUT_SHIFT)
+#define GPIO_BOUT_SHIFT 16
+#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT      (0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR  (1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0    (2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1    (3 << GPIO_BOUT_SHIFT)
+extern void mxc_gpio_mode(int gpio_mode);
+extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
+                                        int alloc_mode, const char *label);
+/*-------------------------------------------------------------------------*/
+/* assignements for GPIO alternate/primary functions */
+/* FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#ifdef CONFIG_ARCH_MX1
+#define PA0_AIN_SPI2_CLK     (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0)
+#define PA0_AF_ETMTRACESYNC  (GPIO_PORTA | GPIO_AF | 0)
+#define PA1_AOUT_SPI2_RXD    (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1)
+#define PA1_PF_TIN           (GPIO_PORTA | GPIO_PF | 1)
+#define PA2_PF_PWM0          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
+#define PA3_PF_CSI_MCLK      (GPIO_PORTA | GPIO_PF | 3)
+#define PA4_PF_CSI_D0        (GPIO_PORTA | GPIO_PF | 4)
+#define PA5_PF_CSI_D1        (GPIO_PORTA | GPIO_PF | 5)
+#define PA6_PF_CSI_D2        (GPIO_PORTA | GPIO_PF | 6)
+#define PA7_PF_CSI_D3        (GPIO_PORTA | GPIO_PF | 7)
+#define PA8_PF_CSI_D4        (GPIO_PORTA | GPIO_PF | 8)
+#define PA9_PF_CSI_D5        (GPIO_PORTA | GPIO_PF | 9)
+#define PA10_PF_CSI_D6       (GPIO_PORTA | GPIO_PF | 10)
+#define PA11_PF_CSI_D7       (GPIO_PORTA | GPIO_PF | 11)
+#define PA12_PF_CSI_VSYNC    (GPIO_PORTA | GPIO_PF | 12)
+#define PA13_PF_CSI_HSYNC    (GPIO_PORTA | GPIO_PF | 13)
+#define PA14_PF_CSI_PIXCLK   (GPIO_PORTA | GPIO_PF | 14)
+#define PA15_PF_I2C_SDA      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
+#define PA16_PF_I2C_SCL      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
+#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
+#define PA17_AIN_SPI2_SS     (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17)
+#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
+#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
+#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
+#define PA21_PF_A0           (GPIO_PORTA | GPIO_PF | 21)
+#define PA22_PF_CS4          (GPIO_PORTA | GPIO_PF | 22)
+#define PA23_PF_CS5          (GPIO_PORTA | GPIO_PF | 23)
+#define PA24_PF_A16          (GPIO_PORTA | GPIO_PF | 24)
+#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
+#define PA25_PF_A17          (GPIO_PORTA | GPIO_PF | 25)
+#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
+#define PA26_PF_A18          (GPIO_PORTA | GPIO_PF | 26)
+#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
+#define PA27_PF_A19          (GPIO_PORTA | GPIO_PF | 27)
+#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
+#define PA28_PF_A20          (GPIO_PORTA | GPIO_PF | 28)
+#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
+#define PA29_PF_A21          (GPIO_PORTA | GPIO_PF | 29)
+#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
+#define PA30_PF_A22          (GPIO_PORTA | GPIO_PF | 30)
+#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
+#define PA31_PF_A23          (GPIO_PORTA | GPIO_PF | 31)
+#define PA31_AF_ETMTRACECLK  (GPIO_PORTA | GPIO_AF | 31)
+#define PB8_PF_SD_DAT0       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
+#define PB8_AF_MS_PIO        (GPIO_PORTB | GPIO_AF | 8)
+#define PB9_PF_SD_DAT1       (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9)
+#define PB9_AF_MS_PI1        (GPIO_PORTB | GPIO_AF | 9)
+#define PB10_PF_SD_DAT2      (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10)
+#define PB10_AF_MS_SCLKI     (GPIO_PORTB | GPIO_AF | 10)
+#define PB11_PF_SD_DAT3      (GPIO_PORTB | GPIO_PF | 11)
+#define PB11_AF_MS_SDIO      (GPIO_PORTB | GPIO_AF | 11)
+#define PB12_PF_SD_CLK       (GPIO_PORTB | GPIO_PF | 12)
+#define PB12_AF_MS_SCLK0     (GPIO_PORTB | GPIO_AF | 12)
+#define PB13_PF_SD_CMD       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
+#define PB13_AF_MS_BS        (GPIO_PORTB | GPIO_AF | 13)
+#define PB14_AF_SSI_RXFS     (GPIO_PORTB | GPIO_AF | 14)
+#define PB15_AF_SSI_RXCLK    (GPIO_PORTB | GPIO_AF | 15)
+#define PB16_AF_SSI_RXDAT    (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
+#define PB17_AF_SSI_TXDAT    (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
+#define PB18_AF_SSI_TXFS     (GPIO_PORTB | GPIO_AF | 18)
+#define PB19_AF_SSI_TXCLK    (GPIO_PORTB | GPIO_AF | 19)
+#define PB20_PF_USBD_AFE     (GPIO_PORTB | GPIO_PF | 20)
+#define PB21_PF_USBD_OE      (GPIO_PORTB | GPIO_PF | 21)
+#define PB22_PFUSBD_RCV      (GPIO_PORTB | GPIO_PF | 22)
+#define PB23_PF_USBD_SUSPND  (GPIO_PORTB | GPIO_PF | 23)
+#define PB24_PF_USBD_VP      (GPIO_PORTB | GPIO_PF | 24)
+#define PB25_PF_USBD_VM      (GPIO_PORTB | GPIO_PF | 25)
+#define PB26_PF_USBD_VPO     (GPIO_PORTB | GPIO_PF | 26)
+#define PB27_PF_USBD_VMO     (GPIO_PORTB | GPIO_PF | 27)
+#define PB28_PF_UART2_CTS    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
+#define PB29_PF_UART2_RTS    (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
+#define PB30_PF_UART2_TXD    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
+#define PB31_PF_UART2_RXD    (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
+#define PC3_PF_SSI_RXFS      (GPIO_PORTC | GPIO_PF | 3)
+#define PC4_PF_SSI_RXCLK     (GPIO_PORTC | GPIO_PF | 4)
+#define PC5_PF_SSI_RXDAT     (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
+#define PC6_PF_SSI_TXDAT     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
+#define PC7_PF_SSI_TXFS      (GPIO_PORTC | GPIO_PF | 7)
+#define PC8_PF_SSI_TXCLK     (GPIO_PORTC | GPIO_PF | 8)
+#define PC9_PF_UART1_CTS     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
+#define PC10_PF_UART1_RTS    (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
+#define PC11_PF_UART1_TXD    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
+#define PC12_PF_UART1_RXD    (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
+#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
+#define PC14_PF_SPI1_SCLK    (GPIO_PORTC | GPIO_PF | 14)
+#define PC15_PF_SPI1_SS      (GPIO_PORTC | GPIO_PF | 15)
+#define PC16_PF_SPI1_MISO    (GPIO_PORTC | GPIO_PF | 16)
+#define PC17_PF_SPI1_MOSI    (GPIO_PORTC | GPIO_PF | 17)
+#define PC24_BIN_UART3_RI    (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
+#define PC25_BIN_UART3_DSR   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
+#define PC26_AOUT_UART3_DTR  (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26)
+#define PC27_BIN_UART3_DCD   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
+#define PC28_BIN_UART3_CTS   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
+#define PC29_AOUT_UART3_RTS  (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29)
+#define PC30_BIN_UART3_TX    (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30)
+#define PC31_AOUT_UART3_RX   (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
+#define PD6_PF_LSCLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
+#define PD7_PF_REV           (GPIO_PORTD | GPIO_PF | 7)
+#define PD7_AF_UART2_DTR     (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
+#define PD7_AIN_SPI2_SCLK    (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7)
+#define PD8_PF_CLS           (GPIO_PORTD | GPIO_PF | 8)
+#define PD8_AF_UART2_DCD     (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
+#define PD8_AIN_SPI2_SS      (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8)
+#define PD9_PF_PS            (GPIO_PORTD | GPIO_PF | 9)
+#define PD9_AF_UART2_RI      (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
+#define PD9_AOUT_SPI2_RXD    (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9)
+#define PD10_PF_SPL_SPR      (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
+#define PD10_AF_UART2_DSR    (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
+#define PD10_AIN_SPI2_TXD    (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10)
+#define PD11_PF_CONTRAST     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
+#define PD12_PF_ACD_OE       (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
+#define PD13_PF_LP_HSYNC     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
+#define PD14_PF_FLM_VSYNC    (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
+#define PD15_PF_LD0          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
+#define PD16_PF_LD1          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
+#define PD17_PF_LD2          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_LD3          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD19_PF_LD4          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
+#define PD20_PF_LD5          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
+#define PD21_PF_LD6          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
+#define PD22_PF_LD7          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
+#define PD23_PF_LD8          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
+#define PD24_PF_LD9          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
+#define PD25_PF_LD10         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
+#define PD26_PF_LD11         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
+#define PD27_PF_LD12         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
+#define PD28_PF_LD13         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
+#define PD29_PF_LD14         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
+#define PD30_PF_LD15         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
+#define PD31_PF_TMR2OUT      (GPIO_PORTD | GPIO_PF | 31)
+#define PD31_BIN_SPI2_TXD    (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31)
+#endif
+#ifdef CONFIG_ARCH_MX2
+#define PA5_PF_LSCLK            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
+#define PA6_PF_LD0              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
+#define PA7_PF_LD1              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
+#define PA8_PF_LD2              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
+#define PA9_PF_LD3              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
+#define PA10_PF_LD4             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
+#define PA11_PF_LD5             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
+#define PA12_PF_LD6             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
+#define PA13_PF_LD7             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
+#define PA14_PF_LD8             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
+#define PA15_PF_LD9             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
+#define PA16_PF_LD10            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
+#define PA17_PF_LD11            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
+#define PA18_PF_LD12            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
+#define PA19_PF_LD13            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
+#define PA20_PF_LD14            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
+#define PA21_PF_LD15            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
+#define PA22_PF_LD16            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
+#define PA23_PF_LD17            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
+#define PA24_PF_REV             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
+#define PA25_PF_CLS             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
+#define PA26_PF_PS              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
+#define PA27_PF_SPL_SPR         (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
+#define PA28_PF_HSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
+#define PA29_PF_VSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
+#define PA30_PF_CONTRAST        (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
+#define PA31_PF_OE_ACD          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
+#define PB10_PF_CSI_D0          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
+#define PB10_AF_UART6_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
+#define PB11_PF_CSI_D1          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
+#define PB11_AF_UART6_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 11)
+#define PB12_PF_CSI_D2          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
+#define PB12_AF_UART6_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
+#define PB13_PF_CSI_D3          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
+#define PB13_AF_UART6_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 13)
+#define PB14_PF_CSI_D4          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
+#define PB15_PF_CSI_MCLK        (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
+#define PB16_PF_CSI_PIXCLK      (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
+#define PB17_PF_CSI_D5          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
+#define PB18_PF_CSI_D6          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
+#define PB18_AF_UART5_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
+#define PB19_PF_CSI_D7          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
+#define PB19_AF_UART5_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 19)
+#define PB20_PF_CSI_VSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
+#define PB20_AF_UART5_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
+#define PB21_PF_CSI_HSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
+#define PB21_AF_UART5_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 21)
+#define PB26_AF_UART4_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_PF | 26)
+#define PB28_AF_UART4_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
+#define PB29_AF_UART4_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
+#define PB31_AF_UART4_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 31)
+#define PC5_PF_I2C2_SDA         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 5)
+#define PC6_PF_I2C2_SCL         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 6)
+#define PC16_PF_SSI4_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 16)
+#define PC17_PF_SSI4_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 17)
+#define PC18_PF_SSI4_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 18)
+#define PC19_PF_SSI4_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 19)
+#define PC20_PF_SSI1_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 20)
+#define PC21_PF_SSI1_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 21)
+#define PC22_PF_SSI1_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 22)
+#define PC23_PF_SSI1_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 23)
+#define PC24_PF_SSI2_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 24)
+#define PC25_PF_SSI2_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 25)
+#define PC26_PF_SSI2_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 26)
+#define PC27_PF_SSI2_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 27)
+#define PC28_PF_SSI3_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 28)
+#define PC29_PF_SSI3_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 29)
+#define PC30_PF_SSI3_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 30)
+#define PC31_PF_SSI3_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 31)
+#define PD0_AIN_FEC_TXD0        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
+#define PD1_AIN_FEC_TXD1        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
+#define PD2_AIN_FEC_TXD2        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
+#define PD3_AIN_FEC_TXD3        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
+#define PD4_AOUT_FEC_RX_ER      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
+#define PD5_AOUT_FEC_RXD1       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
+#define PD6_AOUT_FEC_RXD2       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
+#define PD7_AOUT_FEC_RXD3       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
+#define PD8_AF_FEC_MDIO         (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
+#define PD9_AIN_FEC_MDC         (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
+#define PD10_AOUT_FEC_CRS       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
+#define PD11_AOUT_FEC_TX_CLK    (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
+#define PD12_AOUT_FEC_RXD0      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
+#define PD13_AOUT_FEC_RX_DV     (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
+#define PD14_AOUT_FEC_CLR       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
+#define PD15_AOUT_FEC_COL       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
+#define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
+#define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 25)
+#define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 26)
+#define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 27)
+#define PD28_PF_CSPI1_SS0       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 28)
+#define PD29_PF_CSPI1_SCLK      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 29)
+#define PD30_PF_CSPI1_MISO      (GPIO_PORTD | GPIO_IN | GPIO_PF  | 30)
+#define PD31_PF_CSPI1_MOSI      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 31)
+#define PF23_AIN_FEC_TX_EN      (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
+#define PE3_PF_UART2_CTS        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
+#define PE4_PF_UART2_RTS        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
+#define PE6_PF_UART2_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
+#define PE7_PF_UART2_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
+#define PE8_PF_UART3_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
+#define PE9_PF_UART3_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
+#define PE10_PF_UART3_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
+#define PE11_PF_UART3_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
+#define PE12_PF_UART1_TXD       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
+#define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
+#define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
+#define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
+#define PE18_AF_CSPI3_MISO      (GPIO_PORTE | GPIO_IN  | GPIO_AF | 18)
+#define PE21_AF_CSPI3_SS        (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
+#define PE22_AF_CSPI3_MOSI      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
+#define PE23_AF_CSPI3_SCLK      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
+#endif
+/* decode irq number to use with IMR(x), ISR(x) and friends */
+#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5)
+#define IRQ_GPIOA(x)  (MXC_MAX_INT_LINES + x)
+#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
+#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
+#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
+#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/include/asm-arm/arch-mxc/iomux-mx3.h b/include/asm-arm/arch-mxc/iomux-mx3.h
new file mode 100644
index 000000000000..7509e7692f08
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx3.h
@@ -0,0 +1,501 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __MACH_MX31_IOMUX_H__
+#define __MACH_MX31_IOMUX_H__
+#include <linux/types.h>
+/*
+ * various IOMUX output functions
+ */
+#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
+#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
+#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
+#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
+#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
+#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
+#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
+#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
+#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
+#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
+#define IOMUX_ICONFIG_FUNC  2           /* used as function */
+#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
+#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
+#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
+#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
+#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
+#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
+/*
+ * various IOMUX pad functions
+ */
+enum iomux_pad_config {
+        PAD_CTL_NOLOOPBACK      = 0x0 << 9,
+        PAD_CTL_LOOPBACK        = 0x1 << 9,
+        PAD_CTL_PKE_NONE        = 0x0 << 8,
+        PAD_CTL_PKE_ENABLE      = 0x1 << 8,
+        PAD_CTL_PUE_KEEPER      = 0x0 << 7,
+        PAD_CTL_PUE_PUD         = 0x1 << 7,
+        PAD_CTL_100K_PD         = 0x0 << 5,
+        PAD_CTL_100K_PU         = 0x1 << 5,
+        PAD_CTL_47K_PU          = 0x2 << 5,
+        PAD_CTL_22K_PU          = 0x3 << 5,
+        PAD_CTL_HYS_CMOS        = 0x0 << 4,
+        PAD_CTL_HYS_SCHMITZ     = 0x1 << 4,
+        PAD_CTL_ODE_CMOS        = 0x0 << 3,
+        PAD_CTL_ODE_OpenDrain   = 0x1 << 3,
+        PAD_CTL_DRV_NORMAL      = 0x0 << 1,
+        PAD_CTL_DRV_HIGH        = 0x1 << 1,
+        PAD_CTL_DRV_MAX         = 0x2 << 1,
+        PAD_CTL_SRE_SLOW        = 0x0 << 0,
+        PAD_CTL_SRE_FAST        = 0x1 << 0
+};
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+        MUX_PGP_FIRI                    = 1 << 0,
+        MUX_DDR_MODE                    = 1 << 1,
+        MUX_PGP_CSPI_BB                 = 1 << 2,
+        MUX_PGP_ATA_1                   = 1 << 3,
+        MUX_PGP_ATA_2                   = 1 << 4,
+        MUX_PGP_ATA_3                   = 1 << 5,
+        MUX_PGP_ATA_4                   = 1 << 6,
+        MUX_PGP_ATA_5                   = 1 << 7,
+        MUX_PGP_ATA_6                   = 1 << 8,
+        MUX_PGP_ATA_7                   = 1 << 9,
+        MUX_PGP_ATA_8                   = 1 << 10,
+        MUX_PGP_UH2                     = 1 << 11,
+        MUX_SDCTL_CSD0_SEL              = 1 << 12,
+        MUX_SDCTL_CSD1_SEL              = 1 << 13,
+        MUX_CSPI1_UART3                 = 1 << 14,
+        MUX_EXTDMAREQ2_MBX_SEL          = 1 << 15,
+        MUX_TAMPER_DETECT_EN            = 1 << 16,
+        MUX_PGP_USB_4WIRE               = 1 << 17,
+        MUX_PGB_USB_COMMON              = 1 << 18,
+        MUX_SDHC_MEMSTICK1              = 1 << 19,
+        MUX_SDHC_MEMSTICK2              = 1 << 20,
+        MUX_PGP_SPLL_BYP                = 1 << 21,
+        MUX_PGP_UPLL_BYP                = 1 << 22,
+        MUX_PGP_MSHC1_CLK_SEL           = 1 << 23,
+        MUX_PGP_MSHC2_CLK_SEL           = 1 << 24,
+        MUX_CSPI3_UART5_SEL             = 1 << 25,
+        MUX_PGP_ATA_9                   = 1 << 26,
+        MUX_PGP_USB_SUSPEND             = 1 << 27,
+        MUX_PGP_USB_OTG_LOOPBACK        = 1 << 28,
+        MUX_PGP_USB_HS1_LOOPBACK        = 1 << 29,
+        MUX_PGP_USB_HS2_LOOPBACK        = 1 << 30,
+        MUX_CLKO_DDR_MODE               = 1 << 31,
+};
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void iomux_config_gpr(enum iomux_gp_func , bool);
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(unsigned int);
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
+#define IOMUX_PADNUM_MASK       0x1ff
+#define IOMUX_GPIONUM_SHIFT     9
+#define IOMUX_GPIONUM_MASK      (0xff << IOMUX_GPIONUM_SHIFT)
+#define IOMUX_MODE_SHIFT        17
+#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
+#define IOMUX_PIN(gpionum, padnum) \
+        (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
+         (padnum & IOMUX_PADNUM_MASK))
+#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
+#define IOMUX_TO_GPIO(iomux_pin) \
+        ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
+#define IOMUX_TO_IRQ(iomux_pin) \
+        (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
+        MXC_GPIO_INT_BASE)
+/*
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+enum iomux_pins {
+        MX31_PIN_TTM_PAD        = IOMUX_PIN(0xff,   0),
+        MX31_PIN_CSPI3_SPI_RDY  = IOMUX_PIN(0xff,   1),
+        MX31_PIN_CSPI3_SCLK     = IOMUX_PIN(0xff,   2),
+        MX31_PIN_CSPI3_MISO     = IOMUX_PIN(0xff,   3),
+        MX31_PIN_CSPI3_MOSI     = IOMUX_PIN(0xff,   4),
+        MX31_PIN_CLKSS          = IOMUX_PIN(0xff,   5),
+        MX31_PIN_CE_CONTROL     = IOMUX_PIN(0xff,   6),
+        MX31_PIN_ATA_RESET_B    = IOMUX_PIN(95,     7),
+        MX31_PIN_ATA_DMACK      = IOMUX_PIN(94,     8),
+        MX31_PIN_ATA_DIOW       = IOMUX_PIN(93,     9),
+        MX31_PIN_ATA_DIOR       = IOMUX_PIN(92,    10),
+        MX31_PIN_ATA_CS1        = IOMUX_PIN(91,    11),
+        MX31_PIN_ATA_CS0        = IOMUX_PIN(90,    12),
+        MX31_PIN_SD1_DATA3      = IOMUX_PIN(63,    13),
+        MX31_PIN_SD1_DATA2      = IOMUX_PIN(62,    14),
+        MX31_PIN_SD1_DATA1      = IOMUX_PIN(61,    15),
+        MX31_PIN_SD1_DATA0      = IOMUX_PIN(60,    16),
+        MX31_PIN_SD1_CLK        = IOMUX_PIN(59,    17),
+        MX31_PIN_SD1_CMD        = IOMUX_PIN(58,    18),
+        MX31_PIN_D3_SPL         = IOMUX_PIN(0xff,  19),
+        MX31_PIN_D3_CLS         = IOMUX_PIN(0xff,  20),
+        MX31_PIN_D3_REV         = IOMUX_PIN(0xff,  21),
+        MX31_PIN_CONTRAST       = IOMUX_PIN(0xff,  22),
+        MX31_PIN_VSYNC3         = IOMUX_PIN(0xff,  23),
+        MX31_PIN_READ           = IOMUX_PIN(0xff,  24),
+        MX31_PIN_WRITE          = IOMUX_PIN(0xff,  25),
+        MX31_PIN_PAR_RS         = IOMUX_PIN(0xff,  26),
+        MX31_PIN_SER_RS         = IOMUX_PIN(89,    27),
+        MX31_PIN_LCS1           = IOMUX_PIN(88,    28),
+        MX31_PIN_LCS0           = IOMUX_PIN(87,    29),
+        MX31_PIN_SD_D_CLK       = IOMUX_PIN(86,    30),
+        MX31_PIN_SD_D_IO        = IOMUX_PIN(85,    31),
+        MX31_PIN_SD_D_I         = IOMUX_PIN(84,    32),
+        MX31_PIN_DRDY0          = IOMUX_PIN(0xff,  33),
+        MX31_PIN_FPSHIFT        = IOMUX_PIN(0xff,  34),
+        MX31_PIN_HSYNC          = IOMUX_PIN(0xff,  35),
+        MX31_PIN_VSYNC0         = IOMUX_PIN(0xff,  36),
+        MX31_PIN_LD17           = IOMUX_PIN(0xff,  37),
+        MX31_PIN_LD16           = IOMUX_PIN(0xff,  38),
+        MX31_PIN_LD15           = IOMUX_PIN(0xff,  39),
+        MX31_PIN_LD14           = IOMUX_PIN(0xff,  40),
+        MX31_PIN_LD13           = IOMUX_PIN(0xff,  41),
+        MX31_PIN_LD12           = IOMUX_PIN(0xff,  42),
+        MX31_PIN_LD11           = IOMUX_PIN(0xff,  43),
+        MX31_PIN_LD10           = IOMUX_PIN(0xff,  44),
+        MX31_PIN_LD9            = IOMUX_PIN(0xff,  45),
+        MX31_PIN_LD8            = IOMUX_PIN(0xff,  46),
+        MX31_PIN_LD7            = IOMUX_PIN(0xff,  47),
+        MX31_PIN_LD6            = IOMUX_PIN(0xff,  48),
+        MX31_PIN_LD5            = IOMUX_PIN(0xff,  49),
+        MX31_PIN_LD4            = IOMUX_PIN(0xff,  50),
+        MX31_PIN_LD3            = IOMUX_PIN(0xff,  51),
+        MX31_PIN_LD2            = IOMUX_PIN(0xff,  52),
+        MX31_PIN_LD1            = IOMUX_PIN(0xff,  53),
+        MX31_PIN_LD0            = IOMUX_PIN(0xff,  54),
+        MX31_PIN_USBH2_DATA1    = IOMUX_PIN(0xff,  55),
+        MX31_PIN_USBH2_DATA0    = IOMUX_PIN(0xff,  56),
+        MX31_PIN_USBH2_NXT      = IOMUX_PIN(0xff,  57),
+        MX31_PIN_USBH2_STP      = IOMUX_PIN(0xff,  58),
+        MX31_PIN_USBH2_DIR      = IOMUX_PIN(0xff,  59),
+        MX31_PIN_USBH2_CLK      = IOMUX_PIN(0xff,  60),
+        MX31_PIN_USBOTG_DATA7   = IOMUX_PIN(0xff,  61),
+        MX31_PIN_USBOTG_DATA6   = IOMUX_PIN(0xff,  62),
+        MX31_PIN_USBOTG_DATA5   = IOMUX_PIN(0xff,  63),
+        MX31_PIN_USBOTG_DATA4   = IOMUX_PIN(0xff,  64),
+        MX31_PIN_USBOTG_DATA3   = IOMUX_PIN(0xff,  65),
+        MX31_PIN_USBOTG_DATA2   = IOMUX_PIN(0xff,  66),
+        MX31_PIN_USBOTG_DATA1   = IOMUX_PIN(0xff,  67),
+        MX31_PIN_USBOTG_DATA0   = IOMUX_PIN(0xff,  68),
+        MX31_PIN_USBOTG_NXT     = IOMUX_PIN(0xff,  69),
+        MX31_PIN_USBOTG_STP     = IOMUX_PIN(0xff,  70),
+        MX31_PIN_USBOTG_DIR     = IOMUX_PIN(0xff,  71),
+        MX31_PIN_USBOTG_CLK     = IOMUX_PIN(0xff,  72),
+        MX31_PIN_USB_BYP        = IOMUX_PIN(31,    73),
+        MX31_PIN_USB_OC         = IOMUX_PIN(30,    74),
+        MX31_PIN_USB_PWR        = IOMUX_PIN(29,    75),
+        MX31_PIN_SJC_MOD        = IOMUX_PIN(0xff,  76),
+        MX31_PIN_DE_B           = IOMUX_PIN(0xff,  77),
+        MX31_PIN_TRSTB          = IOMUX_PIN(0xff,  78),
+        MX31_PIN_TDO            = IOMUX_PIN(0xff,  79),
+        MX31_PIN_TDI            = IOMUX_PIN(0xff,  80),
+        MX31_PIN_TMS            = IOMUX_PIN(0xff,  81),
+        MX31_PIN_TCK            = IOMUX_PIN(0xff,  82),
+        MX31_PIN_RTCK           = IOMUX_PIN(0xff,  83),
+        MX31_PIN_KEY_COL7       = IOMUX_PIN(57,    84),
+        MX31_PIN_KEY_COL6       = IOMUX_PIN(56,    85),
+        MX31_PIN_KEY_COL5       = IOMUX_PIN(55,    86),
+        MX31_PIN_KEY_COL4       = IOMUX_PIN(54,    87),
+        MX31_PIN_KEY_COL3       = IOMUX_PIN(0xff,  88),
+        MX31_PIN_KEY_COL2       = IOMUX_PIN(0xff,  89),
+        MX31_PIN_KEY_COL1       = IOMUX_PIN(0xff,  90),
+        MX31_PIN_KEY_COL0       = IOMUX_PIN(0xff,  91),
+        MX31_PIN_KEY_ROW7       = IOMUX_PIN(53,    92),
+        MX31_PIN_KEY_ROW6       = IOMUX_PIN(52,    93),
+        MX31_PIN_KEY_ROW5       = IOMUX_PIN(51,    94),
+        MX31_PIN_KEY_ROW4       = IOMUX_PIN(50,    95),
+        MX31_PIN_KEY_ROW3       = IOMUX_PIN(0xff,  96),
+        MX31_PIN_KEY_ROW2       = IOMUX_PIN(0xff,  97),
+        MX31_PIN_KEY_ROW1       = IOMUX_PIN(0xff,  98),
+        MX31_PIN_KEY_ROW0       = IOMUX_PIN(0xff,  99),
+        MX31_PIN_BATT_LINE      = IOMUX_PIN(49,   100),
+        MX31_PIN_CTS2           = IOMUX_PIN(0xff, 101),
+        MX31_PIN_RTS2           = IOMUX_PIN(0xff, 102),
+        MX31_PIN_TXD2           = IOMUX_PIN(28,   103),
+        MX31_PIN_RXD2           = IOMUX_PIN(27,   104),
+        MX31_PIN_DTR_DCE2       = IOMUX_PIN(48,   105),
+        MX31_PIN_DCD_DTE1       = IOMUX_PIN(47,   106),
+        MX31_PIN_RI_DTE1        = IOMUX_PIN(46,   107),
+        MX31_PIN_DSR_DTE1       = IOMUX_PIN(45,   108),
+        MX31_PIN_DTR_DTE1       = IOMUX_PIN(44,   109),
+        MX31_PIN_DCD_DCE1       = IOMUX_PIN(43,   110),
+        MX31_PIN_RI_DCE1        = IOMUX_PIN(42,   111),
+        MX31_PIN_DSR_DCE1       = IOMUX_PIN(41,   112),
+        MX31_PIN_DTR_DCE1       = IOMUX_PIN(40,   113),
+        MX31_PIN_CTS1           = IOMUX_PIN(39,   114),
+        MX31_PIN_RTS1           = IOMUX_PIN(38,   115),
+        MX31_PIN_TXD1           = IOMUX_PIN(37,   116),
+        MX31_PIN_RXD1           = IOMUX_PIN(36,   117),
+        MX31_PIN_CSPI2_SPI_RDY  = IOMUX_PIN(0xff, 118),
+        MX31_PIN_CSPI2_SCLK     = IOMUX_PIN(0xff, 119),
+        MX31_PIN_CSPI2_SS2      = IOMUX_PIN(0xff, 120),
+        MX31_PIN_CSPI2_SS1      = IOMUX_PIN(0xff, 121),
+        MX31_PIN_CSPI2_SS0      = IOMUX_PIN(0xff, 122),
+        MX31_PIN_CSPI2_MISO     = IOMUX_PIN(0xff, 123),
+        MX31_PIN_CSPI2_MOSI     = IOMUX_PIN(0xff, 124),
+        MX31_PIN_CSPI1_SPI_RDY  = IOMUX_PIN(0xff, 125),
+        MX31_PIN_CSPI1_SCLK     = IOMUX_PIN(0xff, 126),
+        MX31_PIN_CSPI1_SS2      = IOMUX_PIN(0xff, 127),
+        MX31_PIN_CSPI1_SS1      = IOMUX_PIN(0xff, 128),
+        MX31_PIN_CSPI1_SS0      = IOMUX_PIN(0xff, 129),
+        MX31_PIN_CSPI1_MISO     = IOMUX_PIN(0xff, 130),
+        MX31_PIN_CSPI1_MOSI     = IOMUX_PIN(0xff, 131),
+        MX31_PIN_SFS6           = IOMUX_PIN(26,   132),
+        MX31_PIN_SCK6           = IOMUX_PIN(25,   133),
+        MX31_PIN_SRXD6          = IOMUX_PIN(24,   134),
+        MX31_PIN_STXD6          = IOMUX_PIN(23,   135),
+        MX31_PIN_SFS5           = IOMUX_PIN(0xff, 136),
+        MX31_PIN_SCK5           = IOMUX_PIN(0xff, 137),
+        MX31_PIN_SRXD5          = IOMUX_PIN(22,   138),
+        MX31_PIN_STXD5          = IOMUX_PIN(21,   139),
+        MX31_PIN_SFS4           = IOMUX_PIN(0xff, 140),
+        MX31_PIN_SCK4           = IOMUX_PIN(0xff, 141),
+        MX31_PIN_SRXD4          = IOMUX_PIN(20,   142),
+        MX31_PIN_STXD4          = IOMUX_PIN(19,   143),
+        MX31_PIN_SFS3           = IOMUX_PIN(0xff, 144),
+        MX31_PIN_SCK3           = IOMUX_PIN(0xff, 145),
+        MX31_PIN_SRXD3          = IOMUX_PIN(18,   146),
+        MX31_PIN_STXD3          = IOMUX_PIN(17,   147),
+        MX31_PIN_I2C_DAT        = IOMUX_PIN(0xff, 148),
+        MX31_PIN_I2C_CLK        = IOMUX_PIN(0xff, 149),
+        MX31_PIN_CSI_PIXCLK     = IOMUX_PIN(83,   150),
+        MX31_PIN_CSI_HSYNC      = IOMUX_PIN(82,   151),
+        MX31_PIN_CSI_VSYNC      = IOMUX_PIN(81,   152),
+        MX31_PIN_CSI_MCLK       = IOMUX_PIN(80,   153),
+        MX31_PIN_CSI_D15        = IOMUX_PIN(79,   154),
+        MX31_PIN_CSI_D14        = IOMUX_PIN(78,   155),
+        MX31_PIN_CSI_D13        = IOMUX_PIN(77,   156),
+        MX31_PIN_CSI_D12        = IOMUX_PIN(76,   157),
+        MX31_PIN_CSI_D11        = IOMUX_PIN(75,   158),
+        MX31_PIN_CSI_D10        = IOMUX_PIN(74,   159),
+        MX31_PIN_CSI_D9         = IOMUX_PIN(73,   160),
+        MX31_PIN_CSI_D8         = IOMUX_PIN(72,   161),
+        MX31_PIN_CSI_D7         = IOMUX_PIN(71,   162),
+        MX31_PIN_CSI_D6         = IOMUX_PIN(70,   163),
+        MX31_PIN_CSI_D5         = IOMUX_PIN(69,   164),
+        MX31_PIN_CSI_D4         = IOMUX_PIN(68,   165),
+        MX31_PIN_M_GRANT        = IOMUX_PIN(0xff, 166),
+        MX31_PIN_M_REQUEST      = IOMUX_PIN(0xff, 167),
+        MX31_PIN_PC_POE         = IOMUX_PIN(0xff, 168),
+        MX31_PIN_PC_RW_B        = IOMUX_PIN(0xff, 169),
+        MX31_PIN_IOIS16         = IOMUX_PIN(0xff, 170),
+        MX31_PIN_PC_RST         = IOMUX_PIN(0xff, 171),
+        MX31_PIN_PC_BVD2        = IOMUX_PIN(0xff, 172),
+        MX31_PIN_PC_BVD1        = IOMUX_PIN(0xff, 173),
+        MX31_PIN_PC_VS2         = IOMUX_PIN(0xff, 174),
+        MX31_PIN_PC_VS1         = IOMUX_PIN(0xff, 175),
+        MX31_PIN_PC_PWRON       = IOMUX_PIN(0xff, 176),
+        MX31_PIN_PC_READY       = IOMUX_PIN(0xff, 177),
+        MX31_PIN_PC_WAIT_B      = IOMUX_PIN(0xff, 178),
+        MX31_PIN_PC_CD2_B       = IOMUX_PIN(0xff, 179),
+        MX31_PIN_PC_CD1_B       = IOMUX_PIN(0xff, 180),
+        MX31_PIN_D0             = IOMUX_PIN(0xff, 181),
+        MX31_PIN_D1             = IOMUX_PIN(0xff, 182),
+        MX31_PIN_D2             = IOMUX_PIN(0xff, 183),
+        MX31_PIN_D3             = IOMUX_PIN(0xff, 184),
+        MX31_PIN_D4             = IOMUX_PIN(0xff, 185),
+        MX31_PIN_D5             = IOMUX_PIN(0xff, 186),
+        MX31_PIN_D6             = IOMUX_PIN(0xff, 187),
+        MX31_PIN_D7             = IOMUX_PIN(0xff, 188),
+        MX31_PIN_D8             = IOMUX_PIN(0xff, 189),
+        MX31_PIN_D9             = IOMUX_PIN(0xff, 190),
+        MX31_PIN_D10            = IOMUX_PIN(0xff, 191),
+        MX31_PIN_D11            = IOMUX_PIN(0xff, 192),
+        MX31_PIN_D12            = IOMUX_PIN(0xff, 193),
+        MX31_PIN_D13            = IOMUX_PIN(0xff, 194),
+        MX31_PIN_D14            = IOMUX_PIN(0xff, 195),
+        MX31_PIN_D15            = IOMUX_PIN(0xff, 196),
+        MX31_PIN_NFRB           = IOMUX_PIN(16,   197),
+        MX31_PIN_NFCE_B         = IOMUX_PIN(15,   198),
+        MX31_PIN_NFWP_B         = IOMUX_PIN(14,   199),
+        MX31_PIN_NFCLE          = IOMUX_PIN(13,   200),
+        MX31_PIN_NFALE          = IOMUX_PIN(12,   201),
+        MX31_PIN_NFRE_B         = IOMUX_PIN(11,   202),
+        MX31_PIN_NFWE_B         = IOMUX_PIN(10,   203),
+        MX31_PIN_SDQS3          = IOMUX_PIN(0xff, 204),
+        MX31_PIN_SDQS2          = IOMUX_PIN(0xff, 205),
+        MX31_PIN_SDQS1          = IOMUX_PIN(0xff, 206),
+        MX31_PIN_SDQS0          = IOMUX_PIN(0xff, 207),
+        MX31_PIN_SDCLK_B        = IOMUX_PIN(0xff, 208),
+        MX31_PIN_SDCLK          = IOMUX_PIN(0xff, 209),
+        MX31_PIN_SDCKE1         = IOMUX_PIN(0xff, 210),
+        MX31_PIN_SDCKE0         = IOMUX_PIN(0xff, 211),
+        MX31_PIN_SDWE           = IOMUX_PIN(0xff, 212),
+        MX31_PIN_CAS            = IOMUX_PIN(0xff, 213),
+        MX31_PIN_RAS            = IOMUX_PIN(0xff, 214),
+        MX31_PIN_RW             = IOMUX_PIN(0xff, 215),
+        MX31_PIN_BCLK           = IOMUX_PIN(0xff, 216),
+        MX31_PIN_LBA            = IOMUX_PIN(0xff, 217),
+        MX31_PIN_ECB            = IOMUX_PIN(0xff, 218),
+        MX31_PIN_CS5            = IOMUX_PIN(0xff, 219),
+        MX31_PIN_CS4            = IOMUX_PIN(0xff, 220),
+        MX31_PIN_CS3            = IOMUX_PIN(0xff, 221),
+        MX31_PIN_CS2            = IOMUX_PIN(0xff, 222),
+        MX31_PIN_CS1            = IOMUX_PIN(0xff, 223),
+        MX31_PIN_CS0            = IOMUX_PIN(0xff, 224),
+        MX31_PIN_OE             = IOMUX_PIN(0xff, 225),
+        MX31_PIN_EB1            = IOMUX_PIN(0xff, 226),
+        MX31_PIN_EB0            = IOMUX_PIN(0xff, 227),
+        MX31_PIN_DQM3           = IOMUX_PIN(0xff, 228),
+        MX31_PIN_DQM2           = IOMUX_PIN(0xff, 229),
+        MX31_PIN_DQM1           = IOMUX_PIN(0xff, 230),
+        MX31_PIN_DQM0           = IOMUX_PIN(0xff, 231),
+        MX31_PIN_SD31           = IOMUX_PIN(0xff, 232),
+        MX31_PIN_SD30           = IOMUX_PIN(0xff, 233),
+        MX31_PIN_SD29           = IOMUX_PIN(0xff, 234),
+        MX31_PIN_SD28           = IOMUX_PIN(0xff, 235),
+        MX31_PIN_SD27           = IOMUX_PIN(0xff, 236),
+        MX31_PIN_SD26           = IOMUX_PIN(0xff, 237),
+        MX31_PIN_SD25           = IOMUX_PIN(0xff, 238),
+        MX31_PIN_SD24           = IOMUX_PIN(0xff, 239),
+        MX31_PIN_SD23           = IOMUX_PIN(0xff, 240),
+        MX31_PIN_SD22           = IOMUX_PIN(0xff, 241),
+        MX31_PIN_SD21           = IOMUX_PIN(0xff, 242),
+        MX31_PIN_SD20           = IOMUX_PIN(0xff, 243),
+        MX31_PIN_SD19           = IOMUX_PIN(0xff, 244),
+        MX31_PIN_SD18           = IOMUX_PIN(0xff, 245),
+        MX31_PIN_SD17           = IOMUX_PIN(0xff, 246),
+        MX31_PIN_SD16           = IOMUX_PIN(0xff, 247),
+        MX31_PIN_SD15           = IOMUX_PIN(0xff, 248),
+        MX31_PIN_SD14           = IOMUX_PIN(0xff, 249),
+        MX31_PIN_SD13           = IOMUX_PIN(0xff, 250),
+        MX31_PIN_SD12           = IOMUX_PIN(0xff, 251),
+        MX31_PIN_SD11           = IOMUX_PIN(0xff, 252),
+        MX31_PIN_SD10           = IOMUX_PIN(0xff, 253),
+        MX31_PIN_SD9            = IOMUX_PIN(0xff, 254),
+        MX31_PIN_SD8            = IOMUX_PIN(0xff, 255),
+        MX31_PIN_SD7            = IOMUX_PIN(0xff, 256),
+        MX31_PIN_SD6            = IOMUX_PIN(0xff, 257),
+        MX31_PIN_SD5            = IOMUX_PIN(0xff, 258),
+        MX31_PIN_SD4            = IOMUX_PIN(0xff, 259),
+        MX31_PIN_SD3            = IOMUX_PIN(0xff, 260),
+        MX31_PIN_SD2            = IOMUX_PIN(0xff, 261),
+        MX31_PIN_SD1            = IOMUX_PIN(0xff, 262),
+        MX31_PIN_SD0            = IOMUX_PIN(0xff, 263),
+        MX31_PIN_SDBA0          = IOMUX_PIN(0xff, 264),
+        MX31_PIN_SDBA1          = IOMUX_PIN(0xff, 265),
+        MX31_PIN_A25            = IOMUX_PIN(0xff, 266),
+        MX31_PIN_A24            = IOMUX_PIN(0xff, 267),
+        MX31_PIN_A23            = IOMUX_PIN(0xff, 268),
+        MX31_PIN_A22            = IOMUX_PIN(0xff, 269),
+        MX31_PIN_A21            = IOMUX_PIN(0xff, 270),
+        MX31_PIN_A20            = IOMUX_PIN(0xff, 271),
+        MX31_PIN_A19            = IOMUX_PIN(0xff, 272),
+        MX31_PIN_A18            = IOMUX_PIN(0xff, 273),
+        MX31_PIN_A17            = IOMUX_PIN(0xff, 274),
+        MX31_PIN_A16            = IOMUX_PIN(0xff, 275),
+        MX31_PIN_A14            = IOMUX_PIN(0xff, 276),
+        MX31_PIN_A15            = IOMUX_PIN(0xff, 277),
+        MX31_PIN_A13            = IOMUX_PIN(0xff, 278),
+        MX31_PIN_A12            = IOMUX_PIN(0xff, 279),
+        MX31_PIN_A11            = IOMUX_PIN(0xff, 280),
+        MX31_PIN_MA10           = IOMUX_PIN(0xff, 281),
+        MX31_PIN_A10            = IOMUX_PIN(0xff, 282),
+        MX31_PIN_A9             = IOMUX_PIN(0xff, 283),
+        MX31_PIN_A8             = IOMUX_PIN(0xff, 284),
+        MX31_PIN_A7             = IOMUX_PIN(0xff, 285),
+        MX31_PIN_A6             = IOMUX_PIN(0xff, 286),
+        MX31_PIN_A5             = IOMUX_PIN(0xff, 287),
+        MX31_PIN_A4             = IOMUX_PIN(0xff, 288),
+        MX31_PIN_A3             = IOMUX_PIN(0xff, 289),
+        MX31_PIN_A2             = IOMUX_PIN(0xff, 290),
+        MX31_PIN_A1             = IOMUX_PIN(0xff, 291),
+        MX31_PIN_A0             = IOMUX_PIN(0xff, 292),
+        MX31_PIN_VPG1           = IOMUX_PIN(0xff, 293),
+        MX31_PIN_VPG0           = IOMUX_PIN(0xff, 294),
+        MX31_PIN_DVFS1          = IOMUX_PIN(0xff, 295),
+        MX31_PIN_DVFS0          = IOMUX_PIN(0xff, 296),
+        MX31_PIN_VSTBY          = IOMUX_PIN(0xff, 297),
+        MX31_PIN_POWER_FAIL     = IOMUX_PIN(0xff, 298),
+        MX31_PIN_CKIL           = IOMUX_PIN(0xff, 299),
+        MX31_PIN_BOOT_MODE4     = IOMUX_PIN(0xff, 300),
+        MX31_PIN_BOOT_MODE3     = IOMUX_PIN(0xff, 301),
+        MX31_PIN_BOOT_MODE2     = IOMUX_PIN(0xff, 302),
+        MX31_PIN_BOOT_MODE1     = IOMUX_PIN(0xff, 303),
+        MX31_PIN_BOOT_MODE0     = IOMUX_PIN(0xff, 304),
+        MX31_PIN_CLKO           = IOMUX_PIN(0xff, 305),
+        MX31_PIN_POR_B          = IOMUX_PIN(0xff, 306),
+        MX31_PIN_RESET_IN_B     = IOMUX_PIN(0xff, 307),
+        MX31_PIN_CKIH           = IOMUX_PIN(0xff, 308),
+        MX31_PIN_SIMPD0         = IOMUX_PIN(35,   309),
+        MX31_PIN_SRX0           = IOMUX_PIN(34,   310),
+        MX31_PIN_STX0           = IOMUX_PIN(33,   311),
+        MX31_PIN_SVEN0          = IOMUX_PIN(32,   312),
+        MX31_PIN_SRST0          = IOMUX_PIN(67,   313),
+        MX31_PIN_SCLK0          = IOMUX_PIN(66,   314),
+        MX31_PIN_GPIO3_1        = IOMUX_PIN(65,   315),
+        MX31_PIN_GPIO3_0        = IOMUX_PIN(64,   316),
+        MX31_PIN_GPIO1_6        = IOMUX_PIN( 6,   317),
+        MX31_PIN_GPIO1_5        = IOMUX_PIN( 5,   318),
+        MX31_PIN_GPIO1_4        = IOMUX_PIN( 4,   319),
+        MX31_PIN_GPIO1_3        = IOMUX_PIN( 3,   320),
+        MX31_PIN_GPIO1_2        = IOMUX_PIN( 2,   321),
+        MX31_PIN_GPIO1_1        = IOMUX_PIN( 1,   322),
+        MX31_PIN_GPIO1_0        = IOMUX_PIN( 0,   323),
+        MX31_PIN_PWMO           = IOMUX_PIN( 9,   324),
+        MX31_PIN_WATCHDOG_RST   = IOMUX_PIN(0xff, 325),
+        MX31_PIN_COMPARE        = IOMUX_PIN( 8,   326),
+        MX31_PIN_CAPTURE        = IOMUX_PIN( 7,   327),
+};
+/*
+ * Convenience values for use with mxc_iomux_mode()
+ *
+ * Format here is MX31_PIN_(pin name)__(function)
+ */
+#define MX31_PIN_CSPI3_MOSI__RXD3       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI3_MISO__TXD3       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CTS1__CTS1             IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins, u32);
+#endif
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index b2c5205e1962..f416130718cf 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,17 +13,4 @@
 #include <asm/hardware.h>
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
-#define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_GPIO_INT_BASE)
-#define MXC_GPIO_TO_IRQ(x)      (MXC_GPIO_INT_BASE + x)
-/* Number of normal interrupts */
-#define NR_IRQS         (MXC_MAX_INT_LINES + \
-                        MXC_MAX_GPIO_LINES + \
-                        MXC_MAX_VIRTUAL_INTS)
-/* Number of fast interrupts */
-#define NR_FIQS         MXC_MAX_INTS
 #endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/mx27.h b/include/asm-arm/arch-mxc/mx27.h
new file mode 100644
index 000000000000..212ecc246626
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx27.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#ifndef __ASM_ARCH_MXC_MX27_H__
+#define __ASM_ARCH_MXC_MX27_H__
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+/* IRAM */
+#define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
+/* Register offests */
+#define AIPI_BASE_ADDR          0x10000000
+#define AIPI_BASE_ADDR_VIRT     0xF4000000
+#define AIPI_SIZE               SZ_1M
+#define DMA_BASE_ADDR           (AIPI_BASE_ADDR + 0x01000)
+#define WDOG_BASE_ADDR          (AIPI_BASE_ADDR + 0x02000)
+#define GPT1_BASE_ADDR          (AIPI_BASE_ADDR + 0x03000)
+#define GPT2_BASE_ADDR          (AIPI_BASE_ADDR + 0x04000)
+#define GPT3_BASE_ADDR          (AIPI_BASE_ADDR + 0x05000)
+#define PWM_BASE_ADDR           (AIPI_BASE_ADDR + 0x06000)
+#define RTC_BASE_ADDR           (AIPI_BASE_ADDR + 0x07000)
+#define KPP_BASE_ADDR           (AIPI_BASE_ADDR + 0x08000)
+#define OWIRE_BASE_ADDR         (AIPI_BASE_ADDR + 0x09000)
+#define UART1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0A000)
+#define UART2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0B000)
+#define UART3_BASE_ADDR         (AIPI_BASE_ADDR + 0x0C000)
+#define UART4_BASE_ADDR         (AIPI_BASE_ADDR + 0x0D000)
+#define CSPI1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0E000)
+#define CSPI2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0F000)
+#define SSI1_BASE_ADDR          (AIPI_BASE_ADDR + 0x10000)
+#define SSI2_BASE_ADDR          (AIPI_BASE_ADDR + 0x11000)
+#define I2C_BASE_ADDR           (AIPI_BASE_ADDR + 0x12000)
+#define SDHC1_BASE_ADDR         (AIPI_BASE_ADDR + 0x13000)
+#define SDHC2_BASE_ADDR         (AIPI_BASE_ADDR + 0x14000)
+#define GPIO_BASE_ADDR          (AIPI_BASE_ADDR + 0x15000)
+#define AUDMUX_BASE_ADDR        (AIPI_BASE_ADDR + 0x16000)
+#define CSPI3_BASE_ADDR         (AIPI_BASE_ADDR + 0x17000)
+#define MSHC_BASE_ADDR          (AIPI_BASE_ADDR + 0x18000)
+#define GPT5_BASE_ADDR          (AIPI_BASE_ADDR + 0x19000)
+#define GPT4_BASE_ADDR          (AIPI_BASE_ADDR + 0x1A000)
+#define UART5_BASE_ADDR         (AIPI_BASE_ADDR + 0x1B000)
+#define UART6_BASE_ADDR         (AIPI_BASE_ADDR + 0x1C000)
+#define I2C2_BASE_ADDR          (AIPI_BASE_ADDR + 0x1D000)
+#define SDHC3_BASE_ADDR         (AIPI_BASE_ADDR + 0x1E000)
+#define GPT6_BASE_ADDR          (AIPI_BASE_ADDR + 0x1F000)
+#define LCDC_BASE_ADDR          (AIPI_BASE_ADDR + 0x21000)
+#define SLCDC_BASE_ADDR         (AIPI_BASE_ADDR + 0x22000)
+#define VPU_BASE_ADDR           (AIPI_BASE_ADDR + 0x23000)
+#define USBOTG_BASE_ADDR        (AIPI_BASE_ADDR + 0x24000)
+/* for mx27*/
+#define OTG_BASE_ADDR           USBOTG_BASE_ADDR
+#define SAHARA_BASE_ADDR        (AIPI_BASE_ADDR + 0x25000)
+#define EMMA_BASE_ADDR          (AIPI_BASE_ADDR + 0x26400)
+#define CCM_BASE_ADDR           (AIPI_BASE_ADDR + 0x27000)
+#define SYSCTRL_BASE_ADDR       (AIPI_BASE_ADDR + 0x27800)
+#define IIM_BASE_ADDR           (AIPI_BASE_ADDR + 0x28000)
+#define RTIC_BASE_ADDR          (AIPI_BASE_ADDR + 0x2A000)
+#define FEC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2B000)
+#define SCC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2C000)
+#define ETB_BASE_ADDR           (AIPI_BASE_ADDR + 0x3B000)
+#define ETB_RAM_BASE_ADDR       (AIPI_BASE_ADDR + 0x3C000)
+#define JAM_BASE_ADDR           (AIPI_BASE_ADDR + 0x3E000)
+#define MAX_BASE_ADDR           (AIPI_BASE_ADDR + 0x3F000)
+/* ROMP and AVIC */
+#define ROMP_BASE_ADDR          0x10041000
+#define AVIC_BASE_ADDR          0x10040000
+#define SAHB1_BASE_ADDR         0x80000000
+#define SAHB1_BASE_ADDR_VIRT    0xF4100000
+#define SAHB1_SIZE              SZ_1M
+#define CSI_BASE_ADDR           (SAHB1_BASE_ADDR + 0x0000)
+#define ATA_BASE_ADDR           (SAHB1_BASE_ADDR + 0x1000)
+/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
+#define X_MEMC_BASE_ADDR        0xD8000000
+#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define X_MEMC_SIZE             SZ_1M
+#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
+#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x4000)
+/* Memory regions and CS */
+#define SDRAM_BASE_ADDR         0xA0000000
+#define CSD1_BASE_ADDR          0xB0000000
+#define CS0_BASE_ADDR           0xC0000000
+#define CS1_BASE_ADDR           0xC8000000
+#define CS2_BASE_ADDR           0xD0000000
+#define CS3_BASE_ADDR           0xD2000000
+#define CS4_BASE_ADDR           0xD4000000
+#define CS5_BASE_ADDR           0xD6000000
+#define PCMCIA_MEM_BASE_ADDR    0xDC000000
+/*
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+        (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
+                AIPI_IO_ADDRESS(x) : \
+        ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
+                SAHB1_IO_ADDRESS(x) : \
+        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
+                X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
+/* define the address mapping macros: in physical address order */
+#define AIPI_IO_ADDRESS(x)  \
+        (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
+#define AVIC_IO_ADDRESS(x)      AIPI_IO_ADDRESS(x)
+#define SAHB1_IO_ADDRESS(x)  \
+        (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
+#define CS4_IO_ADDRESS(x)  \
+        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+#define X_MEMC_IO_ADDRESS(x)  \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+#define PCMCIA_IO_ADDRESS(x) \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+/* fixed interrput numbers */
+#define MXC_INT_CCM             63
+#define MXC_INT_IIM             62
+#define MXC_INT_LCDC            61
+#define MXC_INT_SLCDC           60
+#define MXC_INT_SAHARA          59
+#define MXC_INT_SCC_SCM         58
+#define MXC_INT_SCC_SMN         57
+#define MXC_INT_USB3            56
+#define MXC_INT_USB2            55
+#define MXC_INT_USB1            54
+#define MXC_INT_VPU             53
+#define MXC_INT_EMMAPP          52
+#define MXC_INT_EMMAPRP         51
+#define MXC_INT_FEC             50
+#define MXC_INT_UART5           49
+#define MXC_INT_UART6           48
+#define MXC_INT_DMACH15         47
+#define MXC_INT_DMACH14         46
+#define MXC_INT_DMACH13         45
+#define MXC_INT_DMACH12         44
+#define MXC_INT_DMACH11         43
+#define MXC_INT_DMACH10         42
+#define MXC_INT_DMACH9          41
+#define MXC_INT_DMACH8          40
+#define MXC_INT_DMACH7          39
+#define MXC_INT_DMACH6          38
+#define MXC_INT_DMACH5          37
+#define MXC_INT_DMACH4          36
+#define MXC_INT_DMACH3          35
+#define MXC_INT_DMACH2          34
+#define MXC_INT_DMACH1          33
+#define MXC_INT_DMACH0          32
+#define MXC_INT_CSI             31
+#define MXC_INT_ATA             30
+#define MXC_INT_NANDFC          29
+#define MXC_INT_PCMCIA          28
+#define MXC_INT_WDOG            27
+#define MXC_INT_GPT1            26
+#define MXC_INT_GPT2            25
+#define MXC_INT_GPT3            24
+#define MXC_INT_GPT             INT_GPT1
+#define MXC_INT_PWM             23
+#define MXC_INT_RTC             22
+#define MXC_INT_KPP             21
+#define MXC_INT_UART1           20
+#define MXC_INT_UART2           19
+#define MXC_INT_UART3           18
+#define MXC_INT_UART4           17
+#define MXC_INT_CSPI1           16
+#define MXC_INT_CSPI2           15
+#define MXC_INT_SSI1            14
+#define MXC_INT_SSI2            13
+#define MXC_INT_I2C             12
+#define MXC_INT_SDHC1           11
+#define MXC_INT_SDHC2           10
+#define MXC_INT_SDHC3           9
+#define MXC_INT_GPIO            8
+#define MXC_INT_SDHC            7
+#define MXC_INT_CSPI3           6
+#define MXC_INT_RTIC            5
+#define MXC_INT_GPT4            4
+#define MXC_INT_GPT5            3
+#define MXC_INT_GPT6            2
+#define MXC_INT_I2C2            1
+/* fixed DMA request numbers */
+#define DMA_REQ_NFC             37
+#define DMA_REQ_SDHC3           36
+#define DMA_REQ_UART6_RX        35
+#define DMA_REQ_UART6_TX        34
+#define DMA_REQ_UART5_RX        33
+#define DMA_REQ_UART5_TX        32
+#define DMA_REQ_CSI_RX          31
+#define DMA_REQ_CSI_STAT        30
+#define DMA_REQ_ATA_RCV         29
+#define DMA_REQ_ATA_TX          28
+#define DMA_REQ_UART1_TX        27
+#define DMA_REQ_UART1_RX        26
+#define DMA_REQ_UART2_TX        25
+#define DMA_REQ_UART2_RX        24
+#define DMA_REQ_UART3_TX        23
+#define DMA_REQ_UART3_RX        22
+#define DMA_REQ_UART4_TX        21
+#define DMA_REQ_UART4_RX        20
+#define DMA_REQ_CSPI1_TX        19
+#define DMA_REQ_CSPI1_RX        18
+#define DMA_REQ_CSPI2_TX        17
+#define DMA_REQ_CSPI2_RX        16
+#define DMA_REQ_SSI1_TX1        15
+#define DMA_REQ_SSI1_RX1        14
+#define DMA_REQ_SSI1_TX0        13
+#define DMA_REQ_SSI1_RX0        12
+#define DMA_REQ_SSI2_TX1        11
+#define DMA_REQ_SSI2_RX1        10
+#define DMA_REQ_SSI2_TX0        9
+#define DMA_REQ_SSI2_RX0        8
+#define DMA_REQ_SDHC1           7
+#define DMA_REQ_SDHC2           6
+#define DMA_REQ_MSHC            4
+#define DMA_REQ_EXT             3
+#define DMA_REQ_CSPI3_TX        2
+#define DMA_REQ_CSPI3_RX        1
+/* silicon revisions specific to i.MX27 */
+#define CHIP_REV_1_0            0x00
+#define CHIP_REV_2_0            0x01
+#ifndef __ASSEMBLY__
+extern int mx27_revision(void);
+#endif
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x1C
+#define GPIO_GDIR               0x00
+#define GPIO_PSR                0x24
+#define GPIO_ICR1               0x28
+#define GPIO_ICR2               0x2C
+#define GPIO_IMR                0x30
+#define GPIO_ISR                0x34
+#define GPIO_INT_LOW_LEV        0x3
+#define GPIO_INT_HIGH_LEV       0x2
+#define GPIO_INT_RISE_EDGE      0x0
+#define GPIO_INT_FALL_EDGE      0x1
+#define GPIO_INT_NONE           0x4
+/* Mandatory defines used globally */
+/* this is an i.MX27 CPU */
+#define cpu_is_mx27()           (1)
+/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
+#define ARCH_NR_GPIOS           (192 + 16)
+/* OS clock tick rate */
+#define CLOCK_TICK_RATE         13300000
+/* Start of RAM */
+#define PHYS_OFFSET             SDRAM_BASE_ADDR
+/* max interrupt lines count */
+#define NR_IRQS                 256
+/* count of internal interrupt sources */
+#define MXC_MAX_INT_LINES       64
+#endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 36a1af495bb3..a7373e4a56cb 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -320,6 +320,8 @@
 #define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
 #define MXC_MAX_VIRTUAL_INTS    16
+#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
 /*!
 * Number of GPIO port as defined in the IC Spec
 */
@@ -347,6 +349,25 @@
 #define SYSTEM_REV_MIN          CHIP_REV_1_0
 #define SYSTEM_REV_NUM          3
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x00
+#define GPIO_GDIR               0x04
+#define GPIO_PSR                0x08
+#define GPIO_ICR1               0x0C
+#define GPIO_ICR2               0x10
+#define GPIO_IMR                0x14
+#define GPIO_ISR                0x18
+#define GPIO_INT_LOW_LEV        0x0
+#define GPIO_INT_HIGH_LEV       0x1
+#define GPIO_INT_RISE_EDGE      0x2
+#define GPIO_INT_FALL_EDGE      0x3
+#define GPIO_INT_NONE           0x4
+/* Mandatory defines used globally */
+/* this CPU supports up to 96 GPIOs */
+#define ARCH_NR_GPIOS           96
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 /* this is a i.MX31 CPU */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 146d3f60951a..332eda4dbd3b 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -1,11 +1,20 @@
 /*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
-/*
+ * This program is free software; you can redistribute it and/or
- * This program is free software; you can redistribute it and/or modify
+ * modify it under the terms of the GNU General Public License
- * it under the terms of the GNU General Public License version 2 as
+ * as published by the Free Software Foundation; either version 2
- * published by the Free Software Foundation.
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
 */
 #ifndef __ASM_ARCH_MXC_H__
@@ -20,133 +29,8 @@
 # define cpu_is_mx31() (0)
 #endif
-/*
+#ifndef CONFIG_MACH_MX27
- *****************************************
+# define cpu_is_mx27() (0)
- * GPT  Register definitions             *
+#endif
- *****************************************
- */
-#define MXC_GPT_GPTCR           IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
-#define MXC_GPT_GPTPR           IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
-#define MXC_GPT_GPTSR           IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
-#define MXC_GPT_GPTIR           IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
-#define MXC_GPT_GPTOCR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
-#define MXC_GPT_GPTOCR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
-#define MXC_GPT_GPTOCR3         IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
-#define MXC_GPT_GPTICR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
-#define MXC_GPT_GPTICR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
-#define MXC_GPT_GPTCNT          IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
-/* GPT Control register bit definitions */
-#define GPTCR_FO3                       (1 << 31)
-#define GPTCR_FO2                       (1 << 30)
-#define GPTCR_FO1                       (1 << 29)
-#define GPTCR_OM3_SHIFT                 26
-#define GPTCR_OM3_MASK                  (7 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_DISCONNECTED          (0 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_TOGGLE                (1 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_CLEAR                 (2 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_SET                   (3 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM3_GENERATE_LOW          (7 << GPTCR_OM3_SHIFT)
-#define GPTCR_OM2_SHIFT                 23
-#define GPTCR_OM2_MASK                  (7 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_DISCONNECTED          (0 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_TOGGLE                (1 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_CLEAR                 (2 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_SET                   (3 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM2_GENERATE_LOW          (7 << GPTCR_OM2_SHIFT)
-#define GPTCR_OM1_SHIFT                 20
-#define GPTCR_OM1_MASK                  (7 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_DISCONNECTED          (0 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_TOGGLE                (1 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_CLEAR                 (2 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_SET                   (3 << GPTCR_OM1_SHIFT)
-#define GPTCR_OM1_GENERATE_LOW          (7 << GPTCR_OM1_SHIFT)
-#define GPTCR_IM2_SHIFT                 18
-#define GPTCR_IM2_MASK                  (3 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_DISABLE       (0 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_RISING        (1 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_FALLING       (2 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM2_CAPTURE_BOTH          (3 << GPTCR_IM2_SHIFT)
-#define GPTCR_IM1_SHIFT                 16
-#define GPTCR_IM1_MASK                  (3 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_DISABLE       (0 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_RISING        (1 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_FALLING       (2 << GPTCR_IM1_SHIFT)
-#define GPTCR_IM1_CAPTURE_BOTH          (3 << GPTCR_IM1_SHIFT)
-#define GPTCR_SWR                       (1 << 15)
-#define GPTCR_FRR                       (1 << 9)
-#define GPTCR_CLKSRC_SHIFT              6
-#define GPTCR_CLKSRC_MASK               (7 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_NOCLOCK            (0 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_HIGHFREQ           (2 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_CLKIN              (3 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_CLKSRC_CLK32K             (7 << GPTCR_CLKSRC_SHIFT)
-#define GPTCR_STOPEN                    (1 << 5)
-#define GPTCR_DOZEN                     (1 << 4)
-#define GPTCR_WAITEN                    (1 << 3)
-#define GPTCR_DBGEN                     (1 << 2)
-#define GPTCR_ENMOD                     (1 << 1)
-#define GPTCR_ENABLE                    (1 << 0)
-#define GPTSR_OF1                       (1 << 0)
-#define GPTSR_OF2                       (1 << 1)
-#define GPTSR_OF3                       (1 << 2)
-#define GPTSR_IF1                       (1 << 3)
-#define GPTSR_IF2                       (1 << 4)
-#define GPTSR_ROV                       (1 << 5)
-#define GPTIR_OF1IE                     GPTSR_OF1
-#define GPTIR_OF2IE                     GPTSR_OF2
-#define GPTIR_OF3IE                     GPTSR_OF3
-#define GPTIR_IF1IE                     GPTSR_IF1
-#define GPTIR_IF2IE                     GPTSR_IF2
-#define GPTIR_ROVIE                     GPTSR_ROV
-/*
- *****************************************
- * AVIC Registers                        *
- *****************************************
- */
-#define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
-#define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
-#define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
-#define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
-#define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
-#define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
-#define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
-#define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
-#define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
-#define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
-#define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
-#define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
-#define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
-#define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
-#define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
-#define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
-#define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
-#define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
-#define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
-#define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
-#define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
-#define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
-#define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
-#define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
-#define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
-#define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
-#define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
-#define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
-#define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
-#define IIM_PROD_REV_SH         3
-#define IIM_PROD_REV_LEN        5
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h
new file mode 100644
index 000000000000..6cb11f4f1a06
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc_timer.h
@@ -0,0 +1,158 @@
+/*
+ * mxc_timer.h
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+#ifndef __PLAT_MXC_TIMER_H
+#define __PLAT_MXC_TIMER_H
+#include <linux/clk.h>
+#include <asm/hardware.h>
+#ifdef CONFIG_ARCH_IMX
+#define TIMER_BASE              IO_ADDRESS(TIM1_BASE_ADDR)
+#define TIMER_INTERRUPT         TIM1_INT
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_CLK_TIN            (3<<1)
+#define TCTL_CLK_32             (4<<1)
+#define MXC_TCTL   0x00
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_IMX */
+#ifdef CONFIG_ARCH_MX2
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT1
+#define MXC_TCTL   0x00
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX2 */
+#ifdef CONFIG_ARCH_MX3
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT
+#define MXC_TCTL   0x00
+#define TCTL_VAL                (TCTL_CLK_IPG | TCTL_WAITEN)
+#define TCTL_CLK_IPG            (1<<6)
+#define TCTL_FRR                (1<<9)
+#define TCTL_WAITEN             (1<<3)
+#define MXC_TPRER  0x04
+#define MXC_TSTAT  0x08
+#define TSTAT_OF1               (1<<0)
+#define TSTAT_OF2               (1<<1)
+#define TSTAT_OF3               (1<<2)
+#define TSTAT_IF1               (1<<3)
+#define TSTAT_IF2               (1<<4)
+#define TSTAT_ROV               (1<<5)
+#define MXC_IR     0x0c
+#define MXC_TCMP   0x10
+#define MXC_TCMP2  0x14
+#define MXC_TCMP3  0x18
+#define MXC_TCR    0x1c
+#define MXC_TCN    0x24
+static inline void gpt_irq_disable(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_IR);
+}
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(1<<0, TIMER_BASE + MXC_IR);
+}
+static inline void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX3 */
+#define TCTL_SWR                (1<<15)
+#define TCTL_CC                 (1<<10)
+#define TCTL_OM                 (1<<9)
+#define TCTL_CAP_RIS            (1<<6)
+#define TCTL_CAP_FAL            (2<<6)
+#define TCTL_CAP_RIS_FAL        (3<<6)
+#define TCTL_CAP_ENA            (1<<5)
+#define TCTL_TEN                (1<<0)
+#endif
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h
index 0b7b34603f1c..0dca11ce21fc 100644
--- a/include/asm-arm/arch-ns9xxx/hardware.h
+++ b/include/asm-arm/arch-ns9xxx/hardware.h
@@ -66,13 +66,13 @@
         __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
 #  define REGGETIM_IDX(var, reg, field, idx)                            \
-         __REGGET(var, reg ## _ ## field((idx))) /                      \
+         __REGGET(var, reg ## _ ## field((idx))) /                      \
         __REGSHIFT(reg ## _ ## field((idx)))
 #else
 #  define __REG(x)      io_p2v(x)
-#  define __REG2(x, y)  io_p2v((x) + (y))
+#  define __REG2(x, y)  io_p2v((x) + 4 * (y))
 #endif
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h
index e9c65ce3cb12..c7db9004ec31 100644
--- a/include/asm-arm/arch-omap/board-2430sdp.h
+++ b/include/asm-arm/arch-omap/board-2430sdp.h
@@ -36,9 +36,4 @@
 #define TWL4030_IRQNUM                  INT_24XX_SYS_NIRQ
-/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
-#define IH_TWL4030_BASE                 IH_BOARD_BASE
-#define IH_TWL4030_END                  (IH_TWL4030_BASE+8)
-#define NR_IRQS                         (IH_TWL4030_END)
 #endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index 0f6404435ea8..c5d0f32a40ac 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,12 +30,6 @@
 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
 #define OMAP1710_ETHR_START             0x04000300
-#define MAXIRQNUM                       (IH_BOARD_BASE)
-#define MAXFIQNUM                       MAXIRQNUM
-#define MAXSWINUM                       MAXIRQNUM
-#define NR_IRQS                         (MAXIRQNUM + 1)
 extern void h3_mmc_init(void);
 extern void h3_mmc_slot_cover_handler(void *arg, int state);
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 56d2c98e143c..9ca03dec9d36 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -36,9 +36,6 @@
 #define OMAP1510P1_EMIFS_PRI_VALUE              0x00
 #define OMAP1510P1_EMIFF_PRI_VALUE              0x00
-#define NR_FPGA_IRQS            24
-#define NR_IRQS                 (IH_BOARD_BASE + NR_FPGA_IRQS)
 #ifndef __ASSEMBLY__
 void fpga_write(unsigned char val, int reg);
 unsigned char fpga_read(int reg);
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
index eb74420cb439..d7429cb0f726 100644
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -36,10 +36,4 @@
 #define OMAP_SDRAM_DEVICE               D256M_1X16_4B
 #endif
-#define MAXIRQNUM               IH_BOARD_BASE
-#define MAXFIQNUM               MAXIRQNUM
-#define MAXSWINUM               MAXIRQNUM
-#define NR_IRQS                 (MAXIRQNUM + 1)
 #endif
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index 12a5e4de9518..4c7b3514f71a 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -33,12 +33,24 @@ struct dpll_data {
        void __iomem            *mult_div1_reg;
        u32                     mult_mask;
        u32                     div1_mask;
+        u16                     last_rounded_m;
+        u8                      last_rounded_n;
+        unsigned long           last_rounded_rate;
+        unsigned int            rate_tolerance;
+        u16                     max_multiplier;
+        u8                      max_divider;
+        u32                     max_tolerance;
 #  if defined(CONFIG_ARCH_OMAP3)
+        u8                      modes;
        void __iomem            *control_reg;
        u32                     enable_mask;
        u8                      auto_recal_bit;
        u8                      recal_en_bit;
        u8                      recal_st_bit;
+        void __iomem            *autoidle_reg;
+        u32                     autoidle_mask;
+        void __iomem            *idlest_reg;
+        u8                      idlest_bit;
 #  endif
 };
@@ -66,11 +78,14 @@ struct clk {
        void __iomem            *clksel_reg;
        u32                     clksel_mask;
        const struct clksel     *clksel;
-        const struct dpll_data  *dpll_data;
+        struct dpll_data        *dpll_data;
 #else
        __u8                    rate_offset;
        __u8                    src_offset;
 #endif
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;  /* For visible tree hierarchy */
+#endif
 };
 struct cpufreq_frequency_table;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 36a3b62d4d8d..8ac03071f60c 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -47,8 +47,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
+/* IO bases for various OMAP processors */
+struct omap_globals {
+        void __iomem    *tap;           /* Control module ID code */
+        void __iomem    *sdrc;          /* SDRAM Controller */
+        void __iomem    *sms;           /* SDRAM Memory Scheduler */
+        void __iomem    *ctrl;          /* System Control Module */
+        void __iomem    *prm;           /* Power and Reset Management */
+        void __iomem    *cm;            /* Clock Management */
+};
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_343x(void);
+/* These get called from omap2_set_globals_xxxx(), do not call these */
+void omap2_set_globals_memory(struct omap_globals *);
+void omap2_set_globals_control(struct omap_globals *);
+void omap2_set_globals_prcm(struct omap_globals *);
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
index 59c0686f8be7..987553e3eeb9 100644
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -167,8 +167,7 @@
 #ifndef __ASSEMBLY__
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-extern void omap_ctrl_base_set(u32 base);
+extern void __iomem *omap_ctrl_base_get(void);
-extern u32 omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
 extern u32 omap_ctrl_readl(u16 offset);
@@ -176,7 +175,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
 #else
-#define omap_ctrl_base_set(x)           WARN_ON(1)
 #define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
 #define omap_ctrl_readw(x)              0
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index e8a4cf52778b..52db09f83281 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -3,7 +3,7 @@
 *
 * OMAP cpu type detection
 *
- * Copyright (C) 2004 Nokia Corporation
+ * Copyright (C) 2004, 2008 Nokia Corporation
 *
 * Written by Tony Lindgren <tony.lindgren@nokia.com>
 *
@@ -26,6 +26,12 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
+struct omap_chip_id {
+        u8 oc;
+};
+#define OMAP_CHIP_INIT(x)       { .oc = x }
 extern unsigned int system_rev;
 #define omap2_cpu_rev()         ((system_rev >> 12) & 0x0f)
@@ -345,6 +351,33 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP2430_REV_ES1_0      0x24300000
 #define OMAP3430_REV_ES1_0      0x34300000
 #define OMAP3430_REV_ES2_0      0x34301000
+#define OMAP3430_REV_ES2_1      0x34302000
+#define OMAP3430_REV_ES2_2      0x34303000
+/*
+ * omap_chip bits
+ *
+ * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
+ * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
+ * something that is only valid on that particular ES revision.
+ *
+ * These bits may be ORed together to indicate structures that are
+ * available on multiple chip types.
+ *
+ * To test whether a particular structure matches the current OMAP chip type,
+ * use omap_chip_is().
+ *
+ */
+#define CHIP_IS_OMAP2420       (1 << 0)
+#define CHIP_IS_OMAP2430       (1 << 1)
+#define CHIP_IS_OMAP3430       (1 << 2)
+#define CHIP_IS_OMAP3430ES1    (1 << 3)
+#define CHIP_IS_OMAP3430ES2    (1 << 4)
+#define CHIP_IS_OMAP24XX       (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
+int omap_chip_is(struct omap_chip_id oci);
 /*
 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
@@ -362,6 +395,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define is_device_type_gp()     (get_device_type() == DEVICE_TYPE_GP)
 #define is_device_type_bad()    (get_device_type() == DEVICE_TYPE_BAD)
-#endif
+void omap2_check_revision(void);
+#endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
 #endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 24acf090030d..f4dcb9587869 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,108 +22,128 @@
 #define __ASM_ARCH_DMA_H
 /* Hardware registers for omap1 */
-#define OMAP_DMA_BASE                   (0xfffed800)
+#define OMAP1_DMA_BASE                  (0xfffed800)
-#define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
-#define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
+#define OMAP1_DMA_GCR                   0x400
-#define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
+#define OMAP1_DMA_GSCR                  0x404
-#define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
+#define OMAP1_DMA_GRST                  0x408
-#define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
+#define OMAP1_DMA_HW_ID                 0x442
-#define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
+#define OMAP1_DMA_PCH2_ID               0x444
-#define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
+#define OMAP1_DMA_PCH0_ID               0x446
-#define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
+#define OMAP1_DMA_PCH1_ID               0x448
-#define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
+#define OMAP1_DMA_PCHG_ID               0x44a
-#define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
+#define OMAP1_DMA_PCHD_ID               0x44c
-#define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
+#define OMAP1_DMA_CAPS_0_U              0x44e
-#define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
+#define OMAP1_DMA_CAPS_0_L              0x450
-#define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
+#define OMAP1_DMA_CAPS_1_U              0x452
-#define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
+#define OMAP1_DMA_CAPS_1_L              0x454
-#define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
+#define OMAP1_DMA_CAPS_2                0x456
-#define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
+#define OMAP1_DMA_CAPS_3                0x458
-#define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
+#define OMAP1_DMA_CAPS_4                0x45a
-#define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
+#define OMAP1_DMA_PCH2_SR               0x460
-#define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
+#define OMAP1_DMA_PCH0_SR               0x480
-#define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
+#define OMAP1_DMA_PCH1_SR               0x482
+#define OMAP1_DMA_PCHD_SR               0x4c0
-/* Hardware registers for omap2 */
-#if defined(CONFIG_ARCH_OMAP3)
+/* Hardware registers for omap2 and omap3 */
-#define OMAP_DMA4_BASE                  (L4_34XX_BASE + 0x56000)
+#define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
-#else   /* CONFIG_ARCH_OMAP2 */
+#define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
-#define OMAP_DMA4_BASE                  (L4_24XX_BASE + 0x56000)
-#endif
+#define OMAP_DMA4_REVISION              0x00
+#define OMAP_DMA4_GCR                   0x78
-#define OMAP_DMA4_REVISION              (OMAP_DMA4_BASE + 0x00)
+#define OMAP_DMA4_IRQSTATUS_L0          0x08
-#define OMAP_DMA4_GCR_REG               (OMAP_DMA4_BASE + 0x78)
+#define OMAP_DMA4_IRQSTATUS_L1          0x0c
-#define OMAP_DMA4_IRQSTATUS_L0          (OMAP_DMA4_BASE + 0x08)
+#define OMAP_DMA4_IRQSTATUS_L2          0x10
-#define OMAP_DMA4_IRQSTATUS_L1          (OMAP_DMA4_BASE + 0x0c)
+#define OMAP_DMA4_IRQSTATUS_L3          0x14
-#define OMAP_DMA4_IRQSTATUS_L2          (OMAP_DMA4_BASE + 0x10)
+#define OMAP_DMA4_IRQENABLE_L0          0x18
-#define OMAP_DMA4_IRQSTATUS_L3          (OMAP_DMA4_BASE + 0x14)
+#define OMAP_DMA4_IRQENABLE_L1          0x1c
-#define OMAP_DMA4_IRQENABLE_L0          (OMAP_DMA4_BASE + 0x18)
+#define OMAP_DMA4_IRQENABLE_L2          0x20
-#define OMAP_DMA4_IRQENABLE_L1          (OMAP_DMA4_BASE + 0x1c)
+#define OMAP_DMA4_IRQENABLE_L3          0x24
-#define OMAP_DMA4_IRQENABLE_L2          (OMAP_DMA4_BASE + 0x20)
+#define OMAP_DMA4_SYSSTATUS             0x28
-#define OMAP_DMA4_IRQENABLE_L3          (OMAP_DMA4_BASE + 0x24)
+#define OMAP_DMA4_OCP_SYSCONFIG         0x2c
-#define OMAP_DMA4_SYSSTATUS             (OMAP_DMA4_BASE + 0x28)
+#define OMAP_DMA4_CAPS_0                0x64
-#define OMAP_DMA4_OCP_SYSCONFIG         (OMAP_DMA4_BASE + 0x2c)
+#define OMAP_DMA4_CAPS_2                0x6c
-#define OMAP_DMA4_CAPS_0                (OMAP_DMA4_BASE + 0x64)
+#define OMAP_DMA4_CAPS_3                0x70
-#define OMAP_DMA4_CAPS_2                (OMAP_DMA4_BASE + 0x6c)
+#define OMAP_DMA4_CAPS_4                0x74
-#define OMAP_DMA4_CAPS_3                (OMAP_DMA4_BASE + 0x70)
-#define OMAP_DMA4_CAPS_4                (OMAP_DMA4_BASE + 0x74)
+#define OMAP1_LOGICAL_DMA_CH_COUNT      17
+#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
-#ifdef CONFIG_ARCH_OMAP1
-#define OMAP_LOGICAL_DMA_CH_COUNT       17
 /* Common channel specific registers for omap1 */
-#define OMAP_DMA_CSDP_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
+#define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
-#define OMAP_DMA_CCR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
+#define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
-#define OMAP_DMA_CICR_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
+#define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
-#define OMAP_DMA_CSR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
+#define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
-#define OMAP_DMA_CEN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
+#define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
-#define OMAP_DMA_CFN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
+#define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
-#define OMAP_DMA_CSFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
+#define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
-#define OMAP_DMA_CSEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
+#define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
-#define OMAP_DMA_CSAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
+#define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
-#define OMAP_DMA_CDAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
+#define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
-#define OMAP_DMA_CDEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
+#define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
-#define OMAP_DMA_CDFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
+#define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
-#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
+#define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
+#define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
-#else
+#define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
-#define OMAP_LOGICAL_DMA_CH_COUNT       32      /* REVISIT: Is this 32 + 2? */
 /* Common channel specific registers for omap2 */
-#define OMAP_DMA_CCR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
+#define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
-#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
+#define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
-#define OMAP_DMA_CICR_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
+#define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
-#define OMAP_DMA_CSR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
+#define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
-#define OMAP_DMA_CSDP_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
+#define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
-#define OMAP_DMA_CEN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
+#define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
-#define OMAP_DMA_CFN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
+#define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
-#define OMAP_DMA_CSEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
+#define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
-#define OMAP_DMA_CSFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
+#define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
-#define OMAP_DMA_CDEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
+#define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
-#define OMAP_DMA_CDFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
+#define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
-#define OMAP_DMA_CSAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
+#define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
-#define OMAP_DMA_CDAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
+#define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
+#define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
-#endif
 /* Channel specific registers only on omap1 */
-#define OMAP1_DMA_CSSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
+#define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
-#define OMAP1_DMA_CSSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
+#define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
-#define OMAP1_DMA_CDSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
+#define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
-#define OMAP1_DMA_CDSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
+#define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
-#define OMAP1_DMA_COLOR_L_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
+#define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
-#define OMAP1_DMA_CCR2_REG(n)           __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
+#define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
-#define OMAP1_DMA_COLOR_U_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
+#define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
-#define OMAP1_DMA_LCH_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
+#define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
+#define OMAP1_DMA_CCEN(n)               0
+#define OMAP1_DMA_CCFN(n)               0
 /* Channel specific registers only on omap2 */
-#define OMAP2_DMA_CSSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
+#define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
-#define OMAP2_DMA_CDSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
+#define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
-#define OMAP2_DMA_CCEN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
+#define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
-#define OMAP2_DMA_CCFN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
+#define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
-#define OMAP2_DMA_COLOR_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
+#define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
+/* Dummy defines to keep multi-omap compiles happy */
+#define OMAP1_DMA_REVISION              0
+#define OMAP1_DMA_IRQSTATUS_L0          0
+#define OMAP1_DMA_IRQENABLE_L0          0
+#define OMAP1_DMA_OCP_SYSCONFIG         0
+#define OMAP_DMA4_HW_ID                 0
+#define OMAP_DMA4_CAPS_0_L              0
+#define OMAP_DMA4_CAPS_0_U              0
+#define OMAP_DMA4_CAPS_1_L              0
+#define OMAP_DMA4_CAPS_1_U              0
+#define OMAP_DMA4_GSCR                  0
+#define OMAP_DMA4_CPC(n)                0
+#define OMAP_DMA4_LCH_CTRL(n)           0
+#define OMAP_DMA4_COLOR_L(n)            0
+#define OMAP_DMA4_COLOR_U(n)            0
+#define OMAP_DMA4_CCR2(n)               0
+#define OMAP1_DMA_CSSA(n)               0
+#define OMAP1_DMA_CDSA(n)               0
+#define OMAP_DMA4_CSSA_L(n)             0
+#define OMAP_DMA4_CSSA_U(n)             0
+#define OMAP_DMA4_CDSA_L(n)             0
+#define OMAP_DMA4_CDSA_U(n)             0
 /*----------------------------------------------------------------------------*/
@@ -196,63 +216,98 @@
 #define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
 #define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
 #define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
-#define OMAP24XX_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
 #define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
 #define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
 #define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
 #define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
 #define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
 #define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP24XX_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
+#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
-#define OMAP24XX_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
+#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
-#define OMAP24XX_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
+#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
-#define OMAP24XX_DMA_EAC_AC_RD          17      /* S_DMA_16 */
+#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP24XX_DMA_EAC_AC_WR          18      /* S_DMA_17 */
+#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP24XX_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
+#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP24XX_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
+#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP24XX_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
+#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP24XX_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
+#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP24XX_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
+#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP24XX_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
+#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP24XX_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
+#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP24XX_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
+#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
+#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
+#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
+#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
+#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
+#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
+#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
+#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
+#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
+#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
+#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
+#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
+#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
+#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
+#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
+#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
+#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
 #define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
 #define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
 #define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
 #define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MCBSP1_TX          31      /* SDMA_30 */
+#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
-#define OMAP24XX_DMA_MCBSP1_RX          32      /* SDMA_31 */
+#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
-#define OMAP24XX_DMA_MCBSP2_TX          33      /* SDMA_32 */
+#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
-#define OMAP24XX_DMA_MCBSP2_RX          34      /* SDMA_33 */
+#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
-#define OMAP24XX_DMA_SPI1_TX0           35      /* SDMA_34 */
+#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
-#define OMAP24XX_DMA_SPI1_RX0           36      /* SDMA_35 */
+#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
-#define OMAP24XX_DMA_SPI1_TX1           37      /* SDMA_36 */
+#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
-#define OMAP24XX_DMA_SPI1_RX1           38      /* SDMA_37 */
+#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
-#define OMAP24XX_DMA_SPI1_TX2           39      /* SDMA_38 */
+#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
-#define OMAP24XX_DMA_SPI1_RX2           40      /* SDMA_39 */
+#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
-#define OMAP24XX_DMA_SPI1_TX3           41      /* SDMA_40 */
+#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
-#define OMAP24XX_DMA_SPI1_RX3           42      /* SDMA_41 */
+#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
-#define OMAP24XX_DMA_SPI2_TX0           43      /* SDMA_42 */
+#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
-#define OMAP24XX_DMA_SPI2_RX0           44      /* SDMA_43 */
+#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
-#define OMAP24XX_DMA_SPI2_TX1           45      /* SDMA_44 */
+#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
-#define OMAP24XX_DMA_SPI2_RX1           46      /* SDMA_45 */
+#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
+#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
-#define OMAP24XX_DMA_UART1_TX           49      /* SDMA_48 */
+#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
-#define OMAP24XX_DMA_UART1_RX           50      /* SDMA_49 */
+#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
-#define OMAP24XX_DMA_UART2_TX           51      /* SDMA_50 */
+#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
-#define OMAP24XX_DMA_UART2_RX           52      /* SDMA_51 */
+#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
-#define OMAP24XX_DMA_UART3_TX           53      /* SDMA_52 */
+#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
-#define OMAP24XX_DMA_UART3_RX           54      /* SDMA_53 */
+#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
-#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* SDMA_54 */
+#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* SDMA_55 */
+#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
-#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* SDMA_56 */
+#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
-#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* SDMA_57 */
+#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
-#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* SDMA_58 */
+#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
-#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* SDMA_59 */
+#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
-#define OMAP24XX_DMA_MMC1_TX            61      /* SDMA_60 */
+#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
-#define OMAP24XX_DMA_MMC1_RX            62      /* SDMA_61 */
+#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
-#define OMAP24XX_DMA_MS                 63      /* SDMA_62 */
+#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP24XX_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
+#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
+#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
+#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
+#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
+#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
+#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
+#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
+#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
+#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
+#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
+#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
+#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
+#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
+#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
+#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
+#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
+#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
+#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 /*----------------------------------------------------------------------------*/
@@ -358,6 +413,11 @@ enum omap_dma_burst_mode {
        OMAP_DMA_DATA_BURST_16,
 };
+enum end_type {
+        OMAP_DMA_LITTLE_ENDIAN = 0,
+        OMAP_DMA_BIG_ENDIAN
+};
 enum omap_dma_color_mode {
        OMAP_DMA_COLOR_DIS = 0,
        OMAP_DMA_CONSTANT_FILL,
@@ -370,24 +430,34 @@ enum omap_dma_write_mode {
        OMAP_DMA_WRITE_LAST_NON_POSTED
 };
+enum omap_dma_channel_mode {
+        OMAP_DMA_LCH_2D = 0,
+        OMAP_DMA_LCH_G,
+        OMAP_DMA_LCH_P,
+        OMAP_DMA_LCH_PD
+};
 struct omap_dma_channel_params {
        int data_type;          /* data type 8,16,32 */
        int elem_count;         /* number of elements in a frame */
        int frame_count;        /* number of frames in a element */
        int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int src_amode;          /* constant , post increment, indexed , double indexed */
+        int src_amode;          /* constant, post increment, indexed,
+                                        double indexed */
        unsigned long src_start;        /* source address : physical */
        int src_ei;             /* source element index */
        int src_fi;             /* source frame index */
        int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
-        int dst_amode;          /* constant , post increment, indexed , double indexed */
+        int dst_amode;          /* constant, post increment, indexed,
+                                        double indexed */
        unsigned long dst_start;        /* source address : physical */
        int dst_ei;             /* source element index */
        int dst_fi;             /* source frame index */
-        int trigger;            /* trigger attached if the channel is synchronized */
+        int trigger;            /* trigger attached if the channel is
+                                        synchronized */
        int sync_mode;          /* sycn on element, frame , block or packet */
        int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
@@ -404,8 +474,8 @@ struct omap_dma_channel_params {
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
-                            void (* callback)(int lch, u16 ch_status, void *data),
+                        void (*callback)(int lch, u16 ch_status, void *data),
-                            void *data, int *dma_ch);
+                        void *data, int *dma_ch);
 extern void omap_enable_dma_irq(int ch, u16 irq_bits);
 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
 extern void omap_free_dma(int ch);
@@ -418,6 +488,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
                                    u32 color);
 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
+extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
                                    unsigned long src_start,
@@ -436,23 +507,26 @@ extern void omap_set_dma_dest_burst_mode(int lch,
                                         enum omap_dma_burst_mode burst_mode);
 extern void omap_set_dma_params(int lch,
-                                struct omap_dma_channel_params * params);
+                                struct omap_dma_channel_params *params);
-extern void omap_dma_link_lch (int lch_head, int lch_queue);
+extern void omap_dma_link_lch(int lch_head, int lch_queue);
-extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
+extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
 extern int omap_set_dma_callback(int lch,
-                        void (* callback)(int lch, u16 ch_status, void *data),
+                        void (*callback)(int lch, u16 ch_status, void *data),
                        void *data);
 extern dma_addr_t omap_get_dma_src_pos(int lch);
 extern dma_addr_t omap_get_dma_dst_pos(int lch);
-extern int omap_get_dma_src_addr_counter(int lch);
 extern void omap_clear_dma(int lch);
+extern int omap_get_dma_active_status(int lch);
 extern int omap_dma_running(void);
 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
                                       int tparams);
 extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
                                 unsigned char write_prio);
+extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
+extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
+extern int omap_get_dma_index(int lch, int *ei, int *fi);
 /* Chaining APIs */
 #ifndef CONFIG_ARCH_OMAP1
@@ -478,7 +552,7 @@ extern int omap_dma_chain_status(int chain_id);
 #endif
 /* LCD DMA functions */
-extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
                                void *data);
 extern void omap_free_lcd_dma(void);
 extern void omap_setup_lcd_dma(void);
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
index fefb276ed402..02b29e8437ae 100644
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -66,6 +66,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer);
 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
index 6a883e0bdbb8..f420881d2a3b 100644
--- a/include/asm-arm/arch-omap/fpga.h
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -169,30 +169,29 @@ struct h2p2_dbg_fpga {
 #define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
 /* IRQ Numbers for interrupts muxed through the FPGA */
-#define OMAP1510_IH_FPGA_BASE           IH_BOARD_BASE
+#define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
-#define OMAP1510_INT_FPGA_ATN           (OMAP1510_IH_FPGA_BASE + 0)
+#define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
-#define OMAP1510_INT_FPGA_ACK           (OMAP1510_IH_FPGA_BASE + 1)
+#define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
-#define OMAP1510_INT_FPGA2              (OMAP1510_IH_FPGA_BASE + 2)
+#define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
-#define OMAP1510_INT_FPGA3              (OMAP1510_IH_FPGA_BASE + 3)
+#define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
-#define OMAP1510_INT_FPGA4              (OMAP1510_IH_FPGA_BASE + 4)
+#define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
-#define OMAP1510_INT_FPGA5              (OMAP1510_IH_FPGA_BASE + 5)
+#define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
-#define OMAP1510_INT_FPGA6              (OMAP1510_IH_FPGA_BASE + 6)
+#define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
-#define OMAP1510_INT_FPGA7              (OMAP1510_IH_FPGA_BASE + 7)
+#define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
-#define OMAP1510_INT_FPGA8              (OMAP1510_IH_FPGA_BASE + 8)
+#define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
-#define OMAP1510_INT_FPGA9              (OMAP1510_IH_FPGA_BASE + 9)
+#define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
-#define OMAP1510_INT_FPGA10             (OMAP1510_IH_FPGA_BASE + 10)
+#define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
-#define OMAP1510_INT_FPGA11             (OMAP1510_IH_FPGA_BASE + 11)
+#define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
-#define OMAP1510_INT_FPGA12             (OMAP1510_IH_FPGA_BASE + 12)
+#define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
-#define OMAP1510_INT_ETHER              (OMAP1510_IH_FPGA_BASE + 13)
+#define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
-#define OMAP1510_INT_FPGAUART1          (OMAP1510_IH_FPGA_BASE + 14)
+#define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
-#define OMAP1510_INT_FPGAUART2          (OMAP1510_IH_FPGA_BASE + 15)
+#define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
-#define OMAP1510_INT_FPGA_TS            (OMAP1510_IH_FPGA_BASE + 16)
+#define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
-#define OMAP1510_INT_FPGA17             (OMAP1510_IH_FPGA_BASE + 17)
+#define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
-#define OMAP1510_INT_FPGA_CAM           (OMAP1510_IH_FPGA_BASE + 18)
+#define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
-#define OMAP1510_INT_FPGA_RTC_A         (OMAP1510_IH_FPGA_BASE + 19)
+#define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
-#define OMAP1510_INT_FPGA_RTC_B         (OMAP1510_IH_FPGA_BASE + 20)
+#define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
-#define OMAP1510_INT_FPGA_CD            (OMAP1510_IH_FPGA_BASE + 21)
+#define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
-#define OMAP1510_INT_FPGA22             (OMAP1510_IH_FPGA_BASE + 22)
+#define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
-#define OMAP1510_INT_FPGA23             (OMAP1510_IH_FPGA_BASE + 23)
 #endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 91d85b3417b7..45fdfccbd5d4 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -284,6 +284,7 @@
 #include "omap1510.h"
 #include "omap24xx.h"
 #include "omap16xx.h"
+#include "omap34xx.h"
 #ifndef __ASSEMBLER__
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 160578e1f557..0b13557fd30b 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -60,6 +60,7 @@
 #define IO_SIZE         0x40000
 #define IO_VIRT         (IO_PHYS - IO_OFFSET)
 #define IO_ADDRESS(pa)  ((pa) - IO_OFFSET)
+#define OMAP1_IO_ADDRESS(pa)    ((pa) - IO_OFFSET)
 #define io_p2v(pa)      ((pa) - IO_OFFSET)
 #define io_v2p(va)      ((va) + IO_OFFSET)
@@ -91,6 +92,7 @@
 #define IO_OFFSET       0x90000000
 #define IO_ADDRESS(pa)  ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
+#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
 #define io_p2v(pa)      ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
 #define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
@@ -148,6 +150,7 @@
 #define IO_OFFSET               0x90000000
 #define IO_ADDRESS(pa)          ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define OMAP2_IO_ADDRESS(pa)    ((pa) + IO_OFFSET)/* Works for L3 and L4 */
 #define io_p2v(pa)              ((pa) + IO_OFFSET)/* Works for L3 and L4 */
 #define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
@@ -183,35 +186,12 @@
 #define omap_writew(v,a)        (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
 #define omap_writel(v,a)        (*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
-/* 16 bit uses LDRH/STRH, base +/- offset_8 */
-typedef struct { volatile u16 offset[256]; } __regbase16;
-#define __REGV16(vaddr)         ((__regbase16 *)((vaddr)&~0xff)) \
-                                        ->offset[((vaddr)&0xff)>>1]
-#define __REG16(paddr)          __REGV16(io_p2v(paddr))
-/* 8/32 bit uses LDR/STR, base +/- offset_12 */
-typedef struct { volatile u8 offset[4096]; } __regbase8;
-#define __REGV8(vaddr)          ((__regbase8  *)((vaddr)&~4095)) \
-                                        ->offset[((vaddr)&4095)>>0]
-#define __REG8(paddr)           __REGV8(io_p2v(paddr))
-typedef struct { volatile u32 offset[4096]; } __regbase32;
-#define __REGV32(vaddr)         ((__regbase32 *)((vaddr)&~4095)) \
-                                        ->offset[((vaddr)&4095)>>2]
-#define __REG32(paddr)          __REGV32(io_p2v(paddr))
 extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 extern void omap2_map_common_io(void);
 extern void omap2_init_common_hw(void);
-#else
-#define __REG8(paddr)           io_p2v(paddr)
-#define __REG16(paddr)          io_p2v(paddr)
-#define __REG32(paddr)          io_p2v(paddr)
 #endif
 #endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 87973654e625..7464c694859b 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -285,7 +285,41 @@
 #define OMAP_MAX_GPIO_LINES     192
 #define IH_GPIO_BASE            (128 + IH2_BASE)
 #define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
-#define IH_BOARD_BASE           (16 + IH_MPUIO_BASE)
+#define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
+/* External FPGA handles interrupts on Innovator boards */
+#define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
+#ifdef  CONFIG_MACH_OMAP_INNOVATOR
+#define OMAP_FPGA_NR_IRQS       24
+#else
+#define OMAP_FPGA_NR_IRQS       0
+#endif
+#define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
+/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
+#define TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
+#ifdef  CONFIG_TWL4030_CORE
+#define TWL4030_BASE_NR_IRQS    8
+#define TWL4030_PWR_NR_IRQS     8
+#else
+#define TWL4030_BASE_NR_IRQS    0
+#define TWL4030_PWR_NR_IRQS     0
+#endif
+#define TWL4030_IRQ_END         (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
+#define TWL4030_PWR_IRQ_BASE    TWL4030_IRQ_END
+#define TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
+/* External TWL4030 gpio interrupts are optional */
+#define TWL4030_GPIO_IRQ_BASE   TWL4030_PWR_IRQ_END
+#ifdef  CONFIG_TWL4030_GPIO
+#define TWL4030_GPIO_NR_IRQS    18
+#else
+#define TWL4030_GPIO_NR_IRQS    0
+#endif
+#define TWL4030_GPIO_IRQ_END    (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
+/* Total number of interrupts depends on the enabled blocks above */
+#define NR_IRQS                 TWL4030_GPIO_IRQ_END
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
@@ -293,14 +327,6 @@
 extern void omap_init_irq(void);
 #endif
-/*
- * The definition of NR_IRQS is in board-specific header file, which is
- * included via hardware.h
- */
 #include <asm/hardware.h>
-#ifndef NR_IRQS
-#define NR_IRQS                 IH_BOARD_BASE
-#endif
 #endif
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
index c7a0cc1c4e93..26c78f67dc8e 100644
--- a/include/asm-arm/arch-omap/mcbsp.h
+++ b/include/asm-arm/arch-omap/mcbsp.h
@@ -24,7 +24,11 @@
 #ifndef __ASM_ARCH_OMAP_MCBSP_H
 #define __ASM_ARCH_OMAP_MCBSP_H
+#include <linux/completion.h>
+#include <linux/spinlock.h>
 #include <asm/hardware.h>
+#include <asm/arch/clock.h>
 #define OMAP730_MCBSP1_BASE     0xfffb1000
 #define OMAP730_MCBSP2_BASE     0xfffb1800
@@ -40,6 +44,9 @@
 #define OMAP24XX_MCBSP1_BASE    0x48074000
 #define OMAP24XX_MCBSP2_BASE    0x48076000
+#define OMAP34XX_MCBSP1_BASE    0x48074000
+#define OMAP34XX_MCBSP2_BASE    0x49022000
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
 #define OMAP_MCBSP_REG_DRR2     0x00
@@ -74,7 +81,8 @@
 #define OMAP_MCBSP_REG_XCERG    0x3A
 #define OMAP_MCBSP_REG_XCERH    0x3C
-#define OMAP_MAX_MCBSP_COUNT 3
+#define OMAP_MAX_MCBSP_COUNT    3
+#define MAX_MCBSP_CLOCKS        3
 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
@@ -117,7 +125,8 @@
 #define OMAP_MCBSP_REG_XCERG    0x74
 #define OMAP_MCBSP_REG_XCERH    0x78
-#define OMAP_MAX_MCBSP_COUNT 2
+#define OMAP_MAX_MCBSP_COUNT    2
+#define MAX_MCBSP_CLOCKS        2
 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -298,6 +307,55 @@ struct omap_mcbsp_spi_cfg {
        omap_mcbsp_word_length          word_length;
 };
+/* Platform specific configuration */
+struct omap_mcbsp_ops {
+        void (*request)(unsigned int);
+        void (*free)(unsigned int);
+        int (*check)(unsigned int);
+};
+struct omap_mcbsp_platform_data {
+        u32 virt_base;
+        u8 dma_rx_sync, dma_tx_sync;
+        u16 rx_irq, tx_irq;
+        struct omap_mcbsp_ops *ops;
+        char const *clk_name;
+};
+struct omap_mcbsp {
+        struct device *dev;
+        u32 io_base;
+        u8 id;
+        u8 free;
+        omap_mcbsp_word_length rx_word_length;
+        omap_mcbsp_word_length tx_word_length;
+        omap_mcbsp_io_type_t io_type; /* IRQ or poll */
+        /* IRQ based TX/RX */
+        int rx_irq;
+        int tx_irq;
+        /* DMA stuff */
+        u8 dma_rx_sync;
+        short dma_rx_lch;
+        u8 dma_tx_sync;
+        short dma_tx_lch;
+        /* Completion queues */
+        struct completion tx_irq_completion;
+        struct completion rx_irq_completion;
+        struct completion tx_dma_completion;
+        struct completion rx_dma_completion;
+        /* Protect the field .free, while checking if the mcbsp is in use */
+        spinlock_t lock;
+        struct omap_mcbsp_platform_data *pdata;
+        struct clk *clk;
+};
+int omap_mcbsp_init(void);
+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+                                        int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 int omap_mcbsp_request(unsigned int id);
 void omap_mcbsp_free(unsigned int id);
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
new file mode 100644
index 000000000000..aa30c6d10abd
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap34xx.h
@@ -0,0 +1,72 @@
+/*
+ * include/asm-arm/arch-omap/omap34xx.h
+ *
+ * This file contains the processor specific definitions of the TI OMAP34XX.
+ *
+ * Copyright (C) 2007 Texas Instruments.
+ * Copyright (C) 2007 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_OMAP34XX_H
+#define __ASM_ARCH_OMAP34XX_H
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_34XX_BASE            0x48000000
+#define L4_WK_34XX_BASE         0x48300000
+#define L4_WK_OMAP_BASE         L4_WK_34XX_BASE
+#define L4_PER_34XX_BASE        0x49000000
+#define L4_PER_OMAP_BASE        L4_PER_34XX_BASE
+#define L4_EMU_34XX_BASE        0x54000000
+#define L4_EMU_BASE             L4_EMU_34XX_BASE
+#define L3_34XX_BASE            0x68000000
+#define L3_OMAP_BASE            L3_34XX_BASE
+#define OMAP3430_32KSYNCT_BASE  0x48320000
+#define OMAP3430_CM_BASE        0x48004800
+#define OMAP3430_PRM_BASE       0x48306800
+#define OMAP343X_SMS_BASE       0x6C000000
+#define OMAP343X_SDRC_BASE      0x6D000000
+#define OMAP34XX_GPMC_BASE      0x6E000000
+#define OMAP343X_SCM_BASE       0x48002000
+#define OMAP343X_CTRL_BASE      OMAP343X_SCM_BASE
+#define OMAP34XX_IC_BASE        0x48200000
+#define OMAP34XX_IVA_INTC_BASE  0x40000000
+#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
+#define OMAP34XX_HSUSB_HOST_BASE        (L4_34XX_BASE + 0x64000)
+#define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
+#if defined(CONFIG_ARCH_OMAP3430)
+#define OMAP2_32KSYNCT_BASE             OMAP3430_32KSYNCT_BASE
+#define OMAP2_CM_BASE                   OMAP3430_CM_BASE
+#define OMAP2_PRM_BASE                  OMAP3430_PRM_BASE
+#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP34XX_IC_BASE)
+#endif
+#define OMAP34XX_DSP_BASE       0x58000000
+#define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
+#define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
+#define OMAP34XX_DSP_MMU_BASE   (OMAP34XX_DSP_BASE + 0x2000000)
+#endif /* __ASM_ARCH_OMAP34XX_H */
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index bb9bb3fd532f..be59f4a9828b 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -11,6 +11,7 @@
 #ifndef __ARCH_ARM_OMAP_SRAM_H
 #define __ARCH_ARM_OMAP_SRAM_H
+extern int __init omap_sram_init(void);
 extern void * omap_sram_push(void * start, unsigned long size);
 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
@@ -21,17 +22,35 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 /* Do not use these */
-extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
+extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-extern unsigned long sram_reprogram_clock_sz;
+extern unsigned long omap1_sram_reprogram_clock_sz;
-extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
-                          u32 base_cs, u32 force_unlock);
+extern unsigned long omap24xx_sram_reprogram_clock_sz;
-extern unsigned long sram_ddr_init_sz;
-extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
+extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
-extern unsigned long sram_set_prcm_sz;
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap242x_sram_ddr_init_sz;
-extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type);
+extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
-extern unsigned long sram_reprogram_sdrc_sz;
+                                                int bypass);
+extern unsigned long omap242x_sram_set_prcm_sz;
+extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap242x_sram_reprogram_sdrc_sz;
+extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
+                                                u32 base_cs, u32 force_unlock);
+extern unsigned long omap243x_sram_ddr_init_sz;
+extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
+                                                int bypass);
+extern unsigned long omap243x_sram_set_prcm_sz;
+extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
+                                                u32 mem_type);
+extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 #endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
index 8ded218cbea5..65a9c82d3bf7 100644
--- a/include/asm-arm/arch-omap/tc.h
+++ b/include/asm-arm/arch-omap/tc.h
@@ -75,16 +75,14 @@
 #ifndef __ASSEMBLER__
 /* EMIF Slow Interface Configuration Register */
-#define OMAP_EMIFS_CONFIG_REG   __REG32(EMIFS_CONFIG)
 #define OMAP_EMIFS_CONFIG_FR            (1 << 4)
 #define OMAP_EMIFS_CONFIG_PDE           (1 << 3)
 #define OMAP_EMIFS_CONFIG_PWD_EN        (1 << 2)
 #define OMAP_EMIFS_CONFIG_BM            (1 << 1)
 #define OMAP_EMIFS_CONFIG_WP            (1 << 0)
-#define EMIFS_CCS(n)            __REG32(EMIFS_CS0_CONFIG + (4 * (n)))
+#define EMIFS_CCS(n)            (EMIFS_CS0_CONFIG + (4 * (n)))
-#define EMIFS_ACS(n)            __REG32(EMIFS_ACS0 + (4 * (n)))
+#define EMIFS_ACS(n)            (EMIFS_ACS0 + (4 * (n)))
 /* Almost all documentation for chip and board memory maps assumes
 * BM is clear.  Most devel boards have a switch to control booting
@@ -93,13 +91,13 @@
 */
 static inline u32 omap_cs0_phys(void)
 {
-        return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
                        ?  OMAP_CS3_PHYS : 0;
 }
 static inline u32 omap_cs3_phys(void)
 {
-        return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
                        ? 0 : OMAP_CS3_PHYS;
 }
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 2147d18aaeae..ddf1861e6df9 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -34,11 +34,8 @@
 /*
 * OTG and transceiver registers, for OMAPs starting with ARM926
 */
-#define OTG_REG32(offset)               __REG32(OTG_BASE + (offset))
+#define OTG_REV                         (OTG_BASE + 0x00)
-#define OTG_REG16(offset)               __REG16(OTG_BASE + (offset))
+#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
-#define OTG_REV_REG                     OTG_REG32(0x00)
-#define OTG_SYSCON_1_REG                OTG_REG32(0x04)
 #       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
 #       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
 #       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
@@ -47,7 +44,7 @@
 #       define   DEV_IDLE_EN            (1 << 13)
 #       define   OTG_RESET_DONE         (1 << 2)
 #       define   OTG_SOFT_RESET         (1 << 1)
-#define OTG_SYSCON_2_REG                OTG_REG32(0x08)
+#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
 #       define   OTG_EN                 (1 << 31)
 #       define   USBX_SYNCHRO           (1 << 30)
 #       define   OTG_MST16              (1 << 29)
@@ -65,7 +62,7 @@
 #       define   HMC_TLLSPEED           (1 << 7)
 #       define   HMC_TLLATTACH          (1 << 6)
 #       define   OTG_HMC(w)             (((w)>>0)&0x3f)
-#define OTG_CTRL_REG                    OTG_REG32(0x0c)
+#define OTG_CTRL                        (OTG_BASE + 0x0c)
 #       define   OTG_USB2_EN            (1 << 29)
 #       define   OTG_USB2_DP            (1 << 28)
 #       define   OTG_USB2_DM            (1 << 27)
@@ -92,7 +89,7 @@
 #       define   OTG_PD_VBUS            (1 << 2)
 #       define   OTG_PU_VBUS            (1 << 1)
 #       define   OTG_PU_ID              (1 << 0)
-#define OTG_IRQ_EN_REG                  OTG_REG16(0x10)
+#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
 #       define   DRIVER_SWITCH          (1 << 15)
 #       define   A_VBUS_ERR             (1 << 13)
 #       define   A_REQ_TMROUT           (1 << 12)
@@ -102,9 +99,9 @@
 #       define   B_SRP_DONE             (1 << 8)
 #       define   B_SRP_STARTED          (1 << 7)
 #       define   OPRT_CHG               (1 << 0)
-#define OTG_IRQ_SRC_REG                 OTG_REG16(0x14)
+#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
        // same bits as in IRQ_EN
-#define OTG_OUTCTRL_REG                 OTG_REG16(0x18)
+#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
 #       define   OTGVPD                 (1 << 14)
 #       define   OTGVPU                 (1 << 13)
 #       define   OTGPUID                (1 << 12)
@@ -117,13 +114,13 @@
 #       define   USB0VDR                (1 << 2)
 #       define   USB0PDEN               (1 << 1)
 #       define   USB0PUEN               (1 << 0)
-#define OTG_TEST_REG                    OTG_REG16(0x20)
+#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
-#define OTG_VENDOR_CODE_REG             OTG_REG32(0xfc)
+#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
 /*-------------------------------------------------------------------------*/
 /* OMAP1 */
-#define USB_TRANSCEIVER_CTRL_REG        __REG32(0xfffe1000 + 0x0064)
+#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
 #       define  CONF_USB2_UNI_R         (1 << 8)
 #       define  CONF_USB1_UNI_R         (1 << 7)
 #       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
index 50f8c8802206..59f1bc96a23b 100644
--- a/include/asm-arm/arch-orion5x/io.h
+++ b/include/asm-arm/arch-orion5x/io.h
@@ -14,7 +14,6 @@
 #include "orion5x.h"
 #define IO_SPACE_LIMIT          0xffffffff
-#define IO_SPACE_REMAP          ORION5X_PCI_SYS_IO_BASE
 static inline void __iomem *
 __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
@@ -53,15 +52,12 @@ static inline void __iomem *__io(unsigned long addr)
 /*****************************************************************************
 * Helpers to access Orion registers
 ****************************************************************************/
-#define orion5x_read(r)         __raw_readl(r)
-#define orion5x_write(r, val)   __raw_writel(val, r)
 /*
 * These are not preempt-safe.  Locks, if needed, must be taken
 * care of by the caller.
 */
-#define orion5x_setbits(r, mask)        orion5x_write((r), orion5x_read(r) | (mask))
+#define orion5x_setbits(r, mask)        writel(readl(r) | (mask), (r))
-#define orion5x_clrbits(r, mask)        orion5x_write((r), orion5x_read(r) & ~(mask))
+#define orion5x_clrbits(r, mask)        writel(readl(r) & ~(mask), (r))
 #endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
index 206ddd71e193..10257f5c5e9e 100644
--- a/include/asm-arm/arch-orion5x/orion5x.h
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -2,7 +2,7 @@
 * include/asm-arm/arch-orion5x/orion5x.h
 *
 * Generic definitions of Orion SoC flavors:
- *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
+ *  Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
@@ -63,9 +63,11 @@
 /*******************************************************************************
 * Supported Devices & Revisions
 ******************************************************************************/
-/* Orion-1 (88F5181) */
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
 #define MV88F5181_DEV_ID        0x5181
 #define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
 /* Orion-NAS (88F5182) */
 #define MV88F5182_DEV_ID        0x5182
 #define MV88F5182_REV_A2        2
@@ -152,6 +154,7 @@
 #define BRIDGE_MASK             ORION5X_BRIDGE_REG(0x114)
 #define  BRIDGE_INT_TIMER0      0x0002
 #define  BRIDGE_INT_TIMER1      0x0004
+#define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 #define MAIN_IRQ_CAUSE          ORION5X_BRIDGE_REG(0x200)
 #define MAIN_IRQ_MASK           ORION5X_BRIDGE_REG(0x204)
diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
index 5c13d4fafb4e..7548cedf2d76 100644
--- a/include/asm-arm/arch-orion5x/uncompress.h
+++ b/include/asm-arm/arch-orion5x/uncompress.h
@@ -8,23 +8,38 @@
 * warranty of any kind, whether express or implied.
 */
+#include <linux/serial_reg.h>
 #include <asm/arch/orion5x.h>
-#define MV_UART_THR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
+#define SERIAL_BASE     ((unsigned char *)UART0_PHYS_BASE)
-#define MV_UART_LSR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
-#define LSR_THRE        0x20
 static void putc(const char c)
 {
-        int j = 0x1000;
+        unsigned char *base = SERIAL_BASE;
-        while (--j && !(*MV_UART_LSR & LSR_THRE))
+        int i;
+        for (i = 0; i < 0x1000; i++) {
+                if (base[UART_LSR << 2] & UART_LSR_THRE)
+                        break;
                barrier();
-        *MV_UART_THR = c;
+        }
+        base[UART_TX << 2] = c;
 }
 static void flush(void)
 {
+        unsigned char *base = SERIAL_BASE;
+        unsigned char mask;
+        int i;
+        mask = UART_LSR_TEMT | UART_LSR_THRE;
+        for (i = 0; i < 0x1000; i++) {
+                if ((base[UART_LSR << 2] & mask) == mask)
+                        break;
+                barrier();
+        }
 }
 /*
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h
index 52bbe3bc25e1..f82f96dd1053 100644
--- a/include/asm-arm/arch-pxa/audio.h
+++ b/include/asm-arm/arch-pxa/audio.h
@@ -12,4 +12,6 @@ typedef struct {
        void *priv;
 } pxa2xx_audio_ops_t;
+extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
 #endif
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index e25558faa5a4..d9af6dabc899 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -192,15 +192,6 @@ extern int pxa_gpio_get_value(unsigned gpio);
 extern void pxa_gpio_set_value(unsigned gpio, int value);
 /*
- * Routine to enable or disable CKEN
- */
-static inline void __deprecated pxa_set_cken(int clock, int enable)
-{
-        extern void __pxa_set_cken(int clock, int enable);
-        __pxa_set_cken(clock, enable);
-}
-/*
 * return current memory and LCD clock frequency in units of 10kHz
 */
 extern unsigned int get_memclk_frequency_10khz(void);
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
index 99f4f423a8e1..0a50c3c763df 100644
--- a/include/asm-arm/arch-pxa/irda.h
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -16,4 +16,8 @@ struct pxaficp_platform_data {
 extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
+#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
+void pxa2xx_transceiver_mode(struct device *dev, int mode);
+#endif
 #endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 4b2ea1e95c57..dce9308626b7 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -600,418 +600,6 @@
 /*
- * USB Device Controller
- * PXA25x and PXA27x USB device controller registers are different.
- */
-#if defined(CONFIG_PXA25x)
-#define UDC_RES1        __REG(0x40600004)  /* UDC Undocumented - Reserved1 */
-#define UDC_RES2        __REG(0x40600008)  /* UDC Undocumented - Reserved2 */
-#define UDC_RES3        __REG(0x4060000C)  /* UDC Undocumented - Reserved3 */
-#define UDCCR           __REG(0x40600000)  /* UDC Control Register */
-#define UDCCR_UDE       (1 << 0)        /* UDC enable */
-#define UDCCR_UDA       (1 << 1)        /* UDC active */
-#define UDCCR_RSM       (1 << 2)        /* Device resume */
-#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
-#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
-#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
-#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
-#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
-#define UDCCS0          __REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
-#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
-#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
-#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
-#define UDCCS0_SST      (1 << 4)        /* Sent stall */
-#define UDCCS0_FST      (1 << 5)        /* Force stall */
-#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
-#define UDCCS0_SA       (1 << 7)        /* Setup active */
-/* Bulk IN - Endpoint 1,6,11 */
-#define UDCCS1          __REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
-#define UDCCS6          __REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
-#define UDCCS11         __REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
-#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
-#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
-#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
-#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
-/* Bulk OUT - Endpoint 2,7,12 */
-#define UDCCS2          __REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
-#define UDCCS7          __REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
-#define UDCCS12         __REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
-#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
-#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
-#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
-#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
-#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
-#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
-#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
-/* Isochronous IN - Endpoint 3,8,13 */
-#define UDCCS3          __REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
-#define UDCCS8          __REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
-#define UDCCS13         __REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
-#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
-#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
-/* Isochronous OUT - Endpoint 4,9,14 */
-#define UDCCS4          __REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
-#define UDCCS9          __REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
-#define UDCCS14         __REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
-#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
-#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
-#define UDCCS_IO_ROF    (1 << 2)        /* Receive overflow */
-#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
-#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
-#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
-/* Interrupt IN - Endpoint 5,10,15 */
-#define UDCCS5          __REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
-#define UDCCS10         __REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
-#define UDCCS15         __REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
-#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
-#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
-#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
-#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
-#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
-#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
-#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
-#define UFNRH           __REG(0x40600060)  /* UDC Frame Number Register High */
-#define UFNRL           __REG(0x40600064)  /* UDC Frame Number Register Low */
-#define UBCR2           __REG(0x40600068)  /* UDC Byte Count Reg 2 */
-#define UBCR4           __REG(0x4060006c)  /* UDC Byte Count Reg 4 */
-#define UBCR7           __REG(0x40600070)  /* UDC Byte Count Reg 7 */
-#define UBCR9           __REG(0x40600074)  /* UDC Byte Count Reg 9 */
-#define UBCR12          __REG(0x40600078)  /* UDC Byte Count Reg 12 */
-#define UBCR14          __REG(0x4060007c)  /* UDC Byte Count Reg 14 */
-#define UDDR0           __REG(0x40600080)  /* UDC Endpoint 0 Data Register */
-#define UDDR1           __REG(0x40600100)  /* UDC Endpoint 1 Data Register */
-#define UDDR2           __REG(0x40600180)  /* UDC Endpoint 2 Data Register */
-#define UDDR3           __REG(0x40600200)  /* UDC Endpoint 3 Data Register */
-#define UDDR4           __REG(0x40600400)  /* UDC Endpoint 4 Data Register */
-#define UDDR5           __REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
-#define UDDR6           __REG(0x40600600)  /* UDC Endpoint 6 Data Register */
-#define UDDR7           __REG(0x40600680)  /* UDC Endpoint 7 Data Register */
-#define UDDR8           __REG(0x40600700)  /* UDC Endpoint 8 Data Register */
-#define UDDR9           __REG(0x40600900)  /* UDC Endpoint 9 Data Register */
-#define UDDR10          __REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
-#define UDDR11          __REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
-#define UDDR12          __REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
-#define UDDR13          __REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
-#define UDDR14          __REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
-#define UDDR15          __REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
-#define UICR0           __REG(0x40600050)  /* UDC Interrupt Control Register 0 */
-#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
-#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
-#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
-#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
-#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
-#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
-#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
-#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
-#define UICR1           __REG(0x40600054)  /* UDC Interrupt Control Register 1 */
-#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
-#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
-#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
-#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
-#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
-#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
-#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
-#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
-#define USIR0           __REG(0x40600058)  /* UDC Status Interrupt Register 0 */
-#define USIR0_IR0       (1 << 0)        /* Interrupt request ep 0 */
-#define USIR0_IR1       (1 << 1)        /* Interrupt request ep 1 */
-#define USIR0_IR2       (1 << 2)        /* Interrupt request ep 2 */
-#define USIR0_IR3       (1 << 3)        /* Interrupt request ep 3 */
-#define USIR0_IR4       (1 << 4)        /* Interrupt request ep 4 */
-#define USIR0_IR5       (1 << 5)        /* Interrupt request ep 5 */
-#define USIR0_IR6       (1 << 6)        /* Interrupt request ep 6 */
-#define USIR0_IR7       (1 << 7)        /* Interrupt request ep 7 */
-#define USIR1           __REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
-#define USIR1_IR8       (1 << 0)        /* Interrupt request ep 8 */
-#define USIR1_IR9       (1 << 1)        /* Interrupt request ep 9 */
-#define USIR1_IR10      (1 << 2)        /* Interrupt request ep 10 */
-#define USIR1_IR11      (1 << 3)        /* Interrupt request ep 11 */
-#define USIR1_IR12      (1 << 4)        /* Interrupt request ep 12 */
-#define USIR1_IR13      (1 << 5)        /* Interrupt request ep 13 */
-#define USIR1_IR14      (1 << 6)        /* Interrupt request ep 14 */
-#define USIR1_IR15      (1 << 7)        /* Interrupt request ep 15 */
-#elif defined(CONFIG_PXA27x)
-#define UDCCR           __REG(0x40600000) /* UDC Control Register */
-#define UDCCR_OEN       (1 << 31)       /* On-the-Go Enable */
-#define UDCCR_AALTHNP   (1 << 30)       /* A-device Alternate Host Negotiation
-                                           Protocol Port Support */
-#define UDCCR_AHNP      (1 << 29)       /* A-device Host Negotiation Protocol
-                                           Support */
-#define UDCCR_BHNP      (1 << 28)       /* B-device Host Negotiation Protocol
-                                           Enable */
-#define UDCCR_DWRE      (1 << 16)       /* Device Remote Wake-up Enable */
-#define UDCCR_ACN       (0x03 << 11)    /* Active UDC configuration Number */
-#define UDCCR_ACN_S     11
-#define UDCCR_AIN       (0x07 << 8)     /* Active UDC interface Number */
-#define UDCCR_AIN_S     8
-#define UDCCR_AAISN     (0x07 << 5)     /* Active UDC Alternate Interface
-                                           Setting Number */
-#define UDCCR_AAISN_S   5
-#define UDCCR_SMAC      (1 << 4)        /* Switch Endpoint Memory to Active
-                                           Configuration */
-#define UDCCR_EMCE      (1 << 3)        /* Endpoint Memory Configuration
-                                           Error */
-#define UDCCR_UDR       (1 << 2)        /* UDC Resume */
-#define UDCCR_UDA       (1 << 1)        /* UDC Active */
-#define UDCCR_UDE       (1 << 0)        /* UDC Enable */
-#define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
-#define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
-#define UDCICR_FIFOERR  (1 << 1)        /* FIFO Error interrupt for EP */
-#define UDCICR_PKTCOMPL (1 << 0)        /* Packet Complete interrupt for EP */
-#define UDC_INT_FIFOERROR  (0x2)
-#define UDC_INT_PACKETCMP  (0x1)
-#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCICR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
-#define UDCICR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
-#define UDCICR1_IERU    (1 << 29)       /* IntEn - Resume */
-#define UDCICR1_IESU    (1 << 28)       /* IntEn - Suspend */
-#define UDCICR1_IERS    (1 << 27)       /* IntEn - Reset */
-#define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
-#define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
-#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
-#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
-#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
-#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
-#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
-#define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
-#define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
-#define UDCOTGICR_IESF  (1 << 24)       /* OTG SET_FEATURE command recvd */
-#define UDCOTGICR_IEXR  (1 << 17)       /* Extra Transciever Interrupt
-                                           Rising Edge Interrupt Enable */
-#define UDCOTGICR_IEXF  (1 << 16)       /* Extra Transciever Interrupt
-                                           Falling Edge Interrupt Enable */
-#define UDCOTGICR_IEVV40R (1 << 9)      /* OTG Vbus Valid 4.0V Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEVV40F (1 << 8)      /* OTG Vbus Valid 4.0V Falling Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEVV44R (1 << 7)      /* OTG Vbus Valid 4.4V Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEVV44F (1 << 6)      /* OTG Vbus Valid 4.4V Falling Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IESVR (1 << 5)        /* OTG Session Valid Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IESVF (1 << 4)        /* OTG Session Valid Falling Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IESDR (1 << 3)        /* OTG A-Device SRP Detect Rising
-                                           Edge Interrupt Enable */
-#define UDCOTGICR_IESDF (1 << 2)        /* OTG A-Device SRP Detect Falling
-                                           Edge Interrupt Enable */
-#define UDCOTGICR_IEIDR (1 << 1)        /* OTG ID Change Rising Edge
-                                           Interrupt Enable */
-#define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
-                                           Interrupt Enable */
-#define UP2OCR            __REG(0x40600020)  /* USB Port 2 Output Control register */
-#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
-#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
-#define UP2OCR_DPPDE    (1 << 2)        /* Host Port 2 Transceiver D+ Pull Down Enable */
-#define UP2OCR_DMPDE    (1 << 3)        /* Host Port 2 Transceiver D- Pull Down Enable */
-#define UP2OCR_DPPUE    (1 << 4)        /* Host Port 2 Transceiver D+ Pull Up Enable */
-#define UP2OCR_DMPUE    (1 << 5)        /* Host Port 2 Transceiver D- Pull Up Enable */
-#define UP2OCR_DPPUBE   (1 << 6)        /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
-#define UP2OCR_DMPUBE   (1 << 7)        /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
-#define UP2OCR_EXSP             (1 << 8)        /* External Transceiver Speed Control */
-#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
-#define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
-#define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
-#define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
-#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
-#define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
-#define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
-#define UDCCSR0_SA      (1 << 7)        /* Setup Active */
-#define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
-#define UDCCSR0_FST     (1 << 5)        /* Force Stall */
-#define UDCCSR0_SST     (1 << 4)        /* Sent Stall */
-#define UDCCSR0_DME     (1 << 3)        /* DMA Enable */
-#define UDCCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
-#define UDCCSR0_IPR     (1 << 1)        /* IN Packet Ready */
-#define UDCCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
-#define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
-#define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
-#define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
-#define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
-#define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
-#define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
-#define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
-#define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
-#define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
-#define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
-#define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
-#define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
-#define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
-#define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
-#define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
-#define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
-#define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
-#define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
-#define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
-#define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
-#define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
-#define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
-#define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
-#define UDCCSR_DPE      (1 << 9)        /* Data Packet Error */
-#define UDCCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
-#define UDCCSR_SP       (1 << 7)        /* Short Packet Control/Status */
-#define UDCCSR_BNE      (1 << 6)        /* Buffer Not Empty (IN endpoints) */
-#define UDCCSR_BNF      (1 << 6)        /* Buffer Not Full (OUT endpoints) */
-#define UDCCSR_FST      (1 << 5)        /* Force STALL */
-#define UDCCSR_SST      (1 << 4)        /* Sent STALL */
-#define UDCCSR_DME      (1 << 3)        /* DMA Enable */
-#define UDCCSR_TRN      (1 << 2)        /* Tx/Rx NAK */
-#define UDCCSR_PC       (1 << 1)        /* Packet Complete */
-#define UDCCSR_FS       (1 << 0)        /* FIFO needs service */
-#define UDCBCN(x)       __REG2(0x40600200, (x)<<2)
-#define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
-#define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
-#define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
-#define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
-#define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
-#define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
-#define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
-#define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
-#define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
-#define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
-#define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
-#define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
-#define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
-#define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
-#define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
-#define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
-#define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
-#define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
-#define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
-#define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
-#define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
-#define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
-#define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
-#define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
-#define UDCDN(x)        __REG2(0x40600300, (x)<<2)
-#define PHYS_UDCDN(x)   (0x40600300 + ((x)<<2))
-#define PUDCDN(x)       (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
-#define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
-#define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
-#define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
-#define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
-#define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
-#define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
-#define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
-#define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
-#define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
-#define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
-#define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
-#define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
-#define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
-#define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
-#define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
-#define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
-#define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
-#define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
-#define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
-#define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
-#define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
-#define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
-#define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
-#define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
-#define UDCCN(x)       __REG2(0x40600400, (x)<<2)
-#define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
-#define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
-#define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
-#define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
-#define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
-#define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
-#define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
-#define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
-#define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
-#define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
-#define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
-#define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
-#define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
-#define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
-#define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
-#define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
-#define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
-#define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
-#define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
-#define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
-#define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
-#define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
-#define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
-#define UDCCONR_CN      (0x03 << 25)    /* Configuration Number */
-#define UDCCONR_CN_S    (25)
-#define UDCCONR_IN      (0x07 << 22)    /* Interface Number */
-#define UDCCONR_IN_S    (22)
-#define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
-#define UDCCONR_AISN_S  (19)
-#define UDCCONR_EN      (0x0f << 15)    /* Endpoint Number */
-#define UDCCONR_EN_S    (15)
-#define UDCCONR_ET      (0x03 << 13)    /* Endpoint Type: */
-#define UDCCONR_ET_S    (13)
-#define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
-#define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
-#define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
-#define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
-#define UDCCONR_ED      (1 << 12)       /* Endpoint Direction */
-#define UDCCONR_MPS     (0x3ff << 2)    /* Maximum Packet Size */
-#define UDCCONR_MPS_S   (2)
-#define UDCCONR_DE      (1 << 1)        /* Double Buffering Enable */
-#define UDCCONR_EE      (1 << 0)        /* Endpoint Enable */
-#define UDC_INT_FIFOERROR  (0x2)
-#define UDC_INT_PACKETCMP  (0x1)
-#define UDC_FNR_MASK     (0x7ff)
-#define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
-#define UDC_BCR_MASK    (0x3ff)
-#endif
-/*
 * Fast Infrared Communication Port
 */
@@ -1237,120 +825,9 @@
 #endif
 /*
- * Power Manager
+ * Power Manager - see pxa2xx-regs.h
 */
-#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
-#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
-#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
-#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
-#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
-#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
-#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
-#define PSTR            __REG(0x40F00038)       /*Power Manager Standby Config Register */
-#define PSNR            __REG(0x40F0003C)       /*Power Manager Sense Config Register */
-#define PVCR            __REG(0x40F00040)       /*Power Manager VoltageControl Register */
-#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
-#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
-#define PCMD(x) __REG2(0x40F00080, (x)<<2)
-#define PCMD0   __REG(0x40F00080 + 0 * 4)
-#define PCMD1   __REG(0x40F00080 + 1 * 4)
-#define PCMD2   __REG(0x40F00080 + 2 * 4)
-#define PCMD3   __REG(0x40F00080 + 3 * 4)
-#define PCMD4   __REG(0x40F00080 + 4 * 4)
-#define PCMD5   __REG(0x40F00080 + 5 * 4)
-#define PCMD6   __REG(0x40F00080 + 6 * 4)
-#define PCMD7   __REG(0x40F00080 + 7 * 4)
-#define PCMD8   __REG(0x40F00080 + 8 * 4)
-#define PCMD9   __REG(0x40F00080 + 9 * 4)
-#define PCMD10  __REG(0x40F00080 + 10 * 4)
-#define PCMD11  __REG(0x40F00080 + 11 * 4)
-#define PCMD12  __REG(0x40F00080 + 12 * 4)
-#define PCMD13  __REG(0x40F00080 + 13 * 4)
-#define PCMD14  __REG(0x40F00080 + 14 * 4)
-#define PCMD15  __REG(0x40F00080 + 15 * 4)
-#define PCMD16  __REG(0x40F00080 + 16 * 4)
-#define PCMD17  __REG(0x40F00080 + 17 * 4)
-#define PCMD18  __REG(0x40F00080 + 18 * 4)
-#define PCMD19  __REG(0x40F00080 + 19 * 4)
-#define PCMD20  __REG(0x40F00080 + 20 * 4)
-#define PCMD21  __REG(0x40F00080 + 21 * 4)
-#define PCMD22  __REG(0x40F00080 + 22 * 4)
-#define PCMD23  __REG(0x40F00080 + 23 * 4)
-#define PCMD24  __REG(0x40F00080 + 24 * 4)
-#define PCMD25  __REG(0x40F00080 + 25 * 4)
-#define PCMD26  __REG(0x40F00080 + 26 * 4)
-#define PCMD27  __REG(0x40F00080 + 27 * 4)
-#define PCMD28  __REG(0x40F00080 + 28 * 4)
-#define PCMD29  __REG(0x40F00080 + 29 * 4)
-#define PCMD30  __REG(0x40F00080 + 30 * 4)
-#define PCMD31  __REG(0x40F00080 + 31 * 4)
-#define PCMD_MBC        (1<<12)
-#define PCMD_DCE        (1<<11)
-#define PCMD_LC (1<<10)
-/* FIXME:  PCMD_SQC need be checked.   */
-#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
-                                   bit 9 should be 0 all day. */
-#define PVCR_VCSA       (0x1<<14)
-#define PVCR_CommandDelay (0xf80)
-#define PCFR_PI2C_EN    (0x1 << 6)
-#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
-#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
-#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
-#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
-#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
-#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
-#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
-#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
-#define PCFR_RO         (1 << 15)       /* RDH Override */
-#define PCFR_PO         (1 << 14)       /* PH Override */
-#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
-#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
-#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
-#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
-#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
-#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
-#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
-#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
-#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
-#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
-#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
-#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
-#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
-#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
-#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
-#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
-#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
-#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
-#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
-#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
-#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
-#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
-#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
-#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
-#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
-#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
-#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
-#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
-#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
-#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
-#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
-#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
 /*
 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
 */
@@ -1360,52 +837,9 @@
 */
 /*
- * Core Clock
+ * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
 */
-#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
-#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
-#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
-#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
-#define CCCR_N_MASK     0x0380          /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define CCCR_M_MASK     0x0060          /* Memory Frequency to Run Mode Frequency Multiplier */
-#define CCCR_L_MASK     0x001f          /* Crystal Frequency to Memory Frequency Multiplier */
-#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
-#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
-#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
-#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
-#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
-#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
-#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
-#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
-#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
-#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
-#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
-#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
-#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
-#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
-#define CKEN_USB        (11)    /* USB Unit Clock Enable */
-#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
-#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
-#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
-#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
-#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
-#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
-#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
-#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
-#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
-#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
-#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
-#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
-#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
-#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
-#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
-#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
 #ifdef CONFIG_PXA27x
 /* Camera Interface */
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h
new file mode 100644
index 000000000000..840305916b6d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa25x-udc.h
@@ -0,0 +1,163 @@
+#ifndef _ASM_ARCH_PXA25X_UDC_H
+#define _ASM_ARCH_PXA25X_UDC_H
+#ifdef _ASM_ARCH_PXA27X_UDC_H
+#error You can't include both PXA25x and PXA27x UDC support
+#endif
+#define UDC_RES1        __REG(0x40600004)  /* UDC Undocumented - Reserved1 */
+#define UDC_RES2        __REG(0x40600008)  /* UDC Undocumented - Reserved2 */
+#define UDC_RES3        __REG(0x4060000C)  /* UDC Undocumented - Reserved3 */
+#define UDCCR           __REG(0x40600000)  /* UDC Control Register */
+#define UDCCR_UDE       (1 << 0)        /* UDC enable */
+#define UDCCR_UDA       (1 << 1)        /* UDC active */
+#define UDCCR_RSM       (1 << 2)        /* Device resume */
+#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
+#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
+#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
+#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
+#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
+#define UDCCS0          __REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
+#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
+#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
+#define UDCCS0_SST      (1 << 4)        /* Sent stall */
+#define UDCCS0_FST      (1 << 5)        /* Force stall */
+#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
+#define UDCCS0_SA       (1 << 7)        /* Setup active */
+/* Bulk IN - Endpoint 1,6,11 */
+#define UDCCS1          __REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6          __REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11         __REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
+#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
+/* Bulk OUT - Endpoint 2,7,12 */
+#define UDCCS2          __REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7          __REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12         __REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
+#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
+/* Isochronous IN - Endpoint 3,8,13 */
+#define UDCCS3          __REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8          __REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13         __REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
+#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
+/* Isochronous OUT - Endpoint 4,9,14 */
+#define UDCCS4          __REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9          __REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14         __REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
+#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_IO_ROF    (1 << 2)        /* Receive overflow */
+#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
+/* Interrupt IN - Endpoint 5,10,15 */
+#define UDCCS5          __REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10         __REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15         __REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
+#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
+#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
+#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
+#define UFNRH           __REG(0x40600060)  /* UDC Frame Number Register High */
+#define UFNRL           __REG(0x40600064)  /* UDC Frame Number Register Low */
+#define UBCR2           __REG(0x40600068)  /* UDC Byte Count Reg 2 */
+#define UBCR4           __REG(0x4060006c)  /* UDC Byte Count Reg 4 */
+#define UBCR7           __REG(0x40600070)  /* UDC Byte Count Reg 7 */
+#define UBCR9           __REG(0x40600074)  /* UDC Byte Count Reg 9 */
+#define UBCR12          __REG(0x40600078)  /* UDC Byte Count Reg 12 */
+#define UBCR14          __REG(0x4060007c)  /* UDC Byte Count Reg 14 */
+#define UDDR0           __REG(0x40600080)  /* UDC Endpoint 0 Data Register */
+#define UDDR1           __REG(0x40600100)  /* UDC Endpoint 1 Data Register */
+#define UDDR2           __REG(0x40600180)  /* UDC Endpoint 2 Data Register */
+#define UDDR3           __REG(0x40600200)  /* UDC Endpoint 3 Data Register */
+#define UDDR4           __REG(0x40600400)  /* UDC Endpoint 4 Data Register */
+#define UDDR5           __REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
+#define UDDR6           __REG(0x40600600)  /* UDC Endpoint 6 Data Register */
+#define UDDR7           __REG(0x40600680)  /* UDC Endpoint 7 Data Register */
+#define UDDR8           __REG(0x40600700)  /* UDC Endpoint 8 Data Register */
+#define UDDR9           __REG(0x40600900)  /* UDC Endpoint 9 Data Register */
+#define UDDR10          __REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
+#define UDDR11          __REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
+#define UDDR12          __REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
+#define UDDR13          __REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
+#define UDDR14          __REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
+#define UDDR15          __REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
+#define UICR0           __REG(0x40600050)  /* UDC Interrupt Control Register 0 */
+#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
+#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
+#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
+#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
+#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
+#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
+#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
+#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
+#define UICR1           __REG(0x40600054)  /* UDC Interrupt Control Register 1 */
+#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
+#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
+#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
+#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
+#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
+#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
+#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
+#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
+#define USIR0           __REG(0x40600058)  /* UDC Status Interrupt Register 0 */
+#define USIR0_IR0       (1 << 0)        /* Interrupt request ep 0 */
+#define USIR0_IR1       (1 << 1)        /* Interrupt request ep 1 */
+#define USIR0_IR2       (1 << 2)        /* Interrupt request ep 2 */
+#define USIR0_IR3       (1 << 3)        /* Interrupt request ep 3 */
+#define USIR0_IR4       (1 << 4)        /* Interrupt request ep 4 */
+#define USIR0_IR5       (1 << 5)        /* Interrupt request ep 5 */
+#define USIR0_IR6       (1 << 6)        /* Interrupt request ep 6 */
+#define USIR0_IR7       (1 << 7)        /* Interrupt request ep 7 */
+#define USIR1           __REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
+#define USIR1_IR8       (1 << 0)        /* Interrupt request ep 8 */
+#define USIR1_IR9       (1 << 1)        /* Interrupt request ep 9 */
+#define USIR1_IR10      (1 << 2)        /* Interrupt request ep 10 */
+#define USIR1_IR11      (1 << 3)        /* Interrupt request ep 11 */
+#define USIR1_IR12      (1 << 4)        /* Interrupt request ep 12 */
+#define USIR1_IR13      (1 << 5)        /* Interrupt request ep 13 */
+#define USIR1_IR14      (1 << 6)        /* Interrupt request ep 14 */
+#define USIR1_IR15      (1 << 7)        /* Interrupt request ep 15 */
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
new file mode 100644
index 000000000000..bc1cf7d0773a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa27x-udc.h
@@ -0,0 +1,257 @@
+#ifndef _ASM_ARCH_PXA27X_UDC_H
+#define _ASM_ARCH_PXA27X_UDC_H
+#ifdef _ASM_ARCH_PXA25X_UDC_H
+#error You cannot include both PXA25x and PXA27x UDC support
+#endif
+#define UDCCR           __REG(0x40600000) /* UDC Control Register */
+#define UDCCR_OEN       (1 << 31)       /* On-the-Go Enable */
+#define UDCCR_AALTHNP   (1 << 30)       /* A-device Alternate Host Negotiation
+                                           Protocol Port Support */
+#define UDCCR_AHNP      (1 << 29)       /* A-device Host Negotiation Protocol
+                                           Support */
+#define UDCCR_BHNP      (1 << 28)       /* B-device Host Negotiation Protocol
+                                           Enable */
+#define UDCCR_DWRE      (1 << 16)       /* Device Remote Wake-up Enable */
+#define UDCCR_ACN       (0x03 << 11)    /* Active UDC configuration Number */
+#define UDCCR_ACN_S     11
+#define UDCCR_AIN       (0x07 << 8)     /* Active UDC interface Number */
+#define UDCCR_AIN_S     8
+#define UDCCR_AAISN     (0x07 << 5)     /* Active UDC Alternate Interface
+                                           Setting Number */
+#define UDCCR_AAISN_S   5
+#define UDCCR_SMAC      (1 << 4)        /* Switch Endpoint Memory to Active
+                                           Configuration */
+#define UDCCR_EMCE      (1 << 3)        /* Endpoint Memory Configuration
+                                           Error */
+#define UDCCR_UDR       (1 << 2)        /* UDC Resume */
+#define UDCCR_UDA       (1 << 1)        /* UDC Active */
+#define UDCCR_UDE       (1 << 0)        /* UDC Enable */
+#define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
+#define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
+#define UDCICR_FIFOERR  (1 << 1)        /* FIFO Error interrupt for EP */
+#define UDCICR_PKTCOMPL (1 << 0)        /* Packet Complete interrupt for EP */
+#define UDC_INT_FIFOERROR  (0x2)
+#define UDC_INT_PACKETCMP  (0x1)
+#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCICR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
+#define UDCICR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
+#define UDCICR1_IERU    (1 << 29)       /* IntEn - Resume */
+#define UDCICR1_IESU    (1 << 28)       /* IntEn - Suspend */
+#define UDCICR1_IERS    (1 << 27)       /* IntEn - Reset */
+#define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
+#define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
+#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
+#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
+#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
+#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
+#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
+#define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
+#define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
+#define UDCOTGICR_IESF  (1 << 24)       /* OTG SET_FEATURE command recvd */
+#define UDCOTGICR_IEXR  (1 << 17)       /* Extra Transciever Interrupt
+                                           Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEXF  (1 << 16)       /* Extra Transciever Interrupt
+                                           Falling Edge Interrupt Enable */
+#define UDCOTGICR_IEVV40R (1 << 9)      /* OTG Vbus Valid 4.0V Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV40F (1 << 8)      /* OTG Vbus Valid 4.0V Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV44R (1 << 7)      /* OTG Vbus Valid 4.4V Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV44F (1 << 6)      /* OTG Vbus Valid 4.4V Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESVR (1 << 5)        /* OTG Session Valid Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESVF (1 << 4)        /* OTG Session Valid Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESDR (1 << 3)        /* OTG A-Device SRP Detect Rising
+                                           Edge Interrupt Enable */
+#define UDCOTGICR_IESDF (1 << 2)        /* OTG A-Device SRP Detect Falling
+                                           Edge Interrupt Enable */
+#define UDCOTGICR_IEIDR (1 << 1)        /* OTG ID Change Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
+                                           Interrupt Enable */
+#define UP2OCR            __REG(0x40600020)  /* USB Port 2 Output Control register */
+#define UP3OCR            __REG(0x40600024)  /* USB Port 2 Output Control register */
+#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
+#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
+#define UP2OCR_DPPDE    (1 << 2)        /* Host Port 2 Transceiver D+ Pull Down Enable */
+#define UP2OCR_DMPDE    (1 << 3)        /* Host Port 2 Transceiver D- Pull Down Enable */
+#define UP2OCR_DPPUE    (1 << 4)        /* Host Port 2 Transceiver D+ Pull Up Enable */
+#define UP2OCR_DMPUE    (1 << 5)        /* Host Port 2 Transceiver D- Pull Up Enable */
+#define UP2OCR_DPPUBE   (1 << 6)        /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
+#define UP2OCR_DMPUBE   (1 << 7)        /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
+#define UP2OCR_EXSP             (1 << 8)        /* External Transceiver Speed Control */
+#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
+#define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
+#define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
+#define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
+#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
+#define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
+#define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
+#define UDCCSR0_SA      (1 << 7)        /* Setup Active */
+#define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
+#define UDCCSR0_FST     (1 << 5)        /* Force Stall */
+#define UDCCSR0_SST     (1 << 4)        /* Sent Stall */
+#define UDCCSR0_DME     (1 << 3)        /* DMA Enable */
+#define UDCCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
+#define UDCCSR0_IPR     (1 << 1)        /* IN Packet Ready */
+#define UDCCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
+#define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
+#define UDCCSR_DPE      (1 << 9)        /* Data Packet Error */
+#define UDCCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
+#define UDCCSR_SP       (1 << 7)        /* Short Packet Control/Status */
+#define UDCCSR_BNE      (1 << 6)        /* Buffer Not Empty (IN endpoints) */
+#define UDCCSR_BNF      (1 << 6)        /* Buffer Not Full (OUT endpoints) */
+#define UDCCSR_FST      (1 << 5)        /* Force STALL */
+#define UDCCSR_SST      (1 << 4)        /* Sent STALL */
+#define UDCCSR_DME      (1 << 3)        /* DMA Enable */
+#define UDCCSR_TRN      (1 << 2)        /* Tx/Rx NAK */
+#define UDCCSR_PC       (1 << 1)        /* Packet Complete */
+#define UDCCSR_FS       (1 << 0)        /* FIFO needs service */
+#define UDCBCN(x)       __REG2(0x40600200, (x)<<2)
+#define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
+#define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
+#define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
+#define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
+#define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
+#define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
+#define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
+#define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
+#define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
+#define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
+#define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
+#define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
+#define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
+#define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
+#define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
+#define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
+#define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
+#define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
+#define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
+#define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
+#define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
+#define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
+#define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
+#define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
+#define UDCDN(x)        __REG2(0x40600300, (x)<<2)
+#define PHYS_UDCDN(x)   (0x40600300 + ((x)<<2))
+#define PUDCDN(x)       (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
+#define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
+#define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
+#define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
+#define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
+#define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
+#define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
+#define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
+#define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
+#define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
+#define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
+#define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
+#define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
+#define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
+#define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
+#define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
+#define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
+#define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
+#define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
+#define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
+#define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
+#define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
+#define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
+#define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
+#define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
+#define UDCCN(x)       __REG2(0x40600400, (x)<<2)
+#define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
+#define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
+#define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
+#define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
+#define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
+#define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
+#define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
+#define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
+#define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
+#define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
+#define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
+#define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
+#define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
+#define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
+#define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
+#define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
+#define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
+#define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
+#define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
+#define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
+#define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
+#define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
+#define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
+#define UDCCONR_CN      (0x03 << 25)    /* Configuration Number */
+#define UDCCONR_CN_S    (25)
+#define UDCCONR_IN      (0x07 << 22)    /* Interface Number */
+#define UDCCONR_IN_S    (22)
+#define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
+#define UDCCONR_AISN_S  (19)
+#define UDCCONR_EN      (0x0f << 15)    /* Endpoint Number */
+#define UDCCONR_EN_S    (15)
+#define UDCCONR_ET      (0x03 << 13)    /* Endpoint Type: */
+#define UDCCONR_ET_S    (13)
+#define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
+#define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
+#define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
+#define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
+#define UDCCONR_ED      (1 << 12)       /* Endpoint Direction */
+#define UDCCONR_MPS     (0x3ff << 2)    /* Maximum Packet Size */
+#define UDCCONR_MPS_S   (2)
+#define UDCCONR_DE      (1 << 1)        /* Double Buffering Enable */
+#define UDCCONR_EE      (1 << 0)        /* Endpoint Enable */
+#define UDC_INT_FIFOERROR  (0x2)
+#define UDC_INT_PACKETCMP  (0x1)
+#define UDC_FNR_MASK     (0x7ff)
+#define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
+#define UDC_BCR_MASK    (0x3ff)
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
index b81cd63cb2eb..6ef1dd09970b 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ARCH_PXA2XX_GPIO_H
 #define __ASM_ARCH_PXA2XX_GPIO_H
+#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
 /* GPIO alternate function assignments */
 #define GPIO1_RST               1       /* reset */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
index 9553b54fa5bc..73e0a329cf7f 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -81,4 +81,166 @@
 #endif
+/*
+ * Power Manager
+ */
+#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
+#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
+#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
+#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
+#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
+#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
+#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
+#define PSTR            __REG(0x40F00038)       /* Power Manager Standby Config Register */
+#define PSNR            __REG(0x40F0003C)       /* Power Manager Sense Config Register */
+#define PVCR            __REG(0x40F00040)       /* Power Manager VoltageControl Register */
+#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
+#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
+#define PCMD(x) __REG2(0x40F00080, (x)<<2)
+#define PCMD0   __REG(0x40F00080 + 0 * 4)
+#define PCMD1   __REG(0x40F00080 + 1 * 4)
+#define PCMD2   __REG(0x40F00080 + 2 * 4)
+#define PCMD3   __REG(0x40F00080 + 3 * 4)
+#define PCMD4   __REG(0x40F00080 + 4 * 4)
+#define PCMD5   __REG(0x40F00080 + 5 * 4)
+#define PCMD6   __REG(0x40F00080 + 6 * 4)
+#define PCMD7   __REG(0x40F00080 + 7 * 4)
+#define PCMD8   __REG(0x40F00080 + 8 * 4)
+#define PCMD9   __REG(0x40F00080 + 9 * 4)
+#define PCMD10  __REG(0x40F00080 + 10 * 4)
+#define PCMD11  __REG(0x40F00080 + 11 * 4)
+#define PCMD12  __REG(0x40F00080 + 12 * 4)
+#define PCMD13  __REG(0x40F00080 + 13 * 4)
+#define PCMD14  __REG(0x40F00080 + 14 * 4)
+#define PCMD15  __REG(0x40F00080 + 15 * 4)
+#define PCMD16  __REG(0x40F00080 + 16 * 4)
+#define PCMD17  __REG(0x40F00080 + 17 * 4)
+#define PCMD18  __REG(0x40F00080 + 18 * 4)
+#define PCMD19  __REG(0x40F00080 + 19 * 4)
+#define PCMD20  __REG(0x40F00080 + 20 * 4)
+#define PCMD21  __REG(0x40F00080 + 21 * 4)
+#define PCMD22  __REG(0x40F00080 + 22 * 4)
+#define PCMD23  __REG(0x40F00080 + 23 * 4)
+#define PCMD24  __REG(0x40F00080 + 24 * 4)
+#define PCMD25  __REG(0x40F00080 + 25 * 4)
+#define PCMD26  __REG(0x40F00080 + 26 * 4)
+#define PCMD27  __REG(0x40F00080 + 27 * 4)
+#define PCMD28  __REG(0x40F00080 + 28 * 4)
+#define PCMD29  __REG(0x40F00080 + 29 * 4)
+#define PCMD30  __REG(0x40F00080 + 30 * 4)
+#define PCMD31  __REG(0x40F00080 + 31 * 4)
+#define PCMD_MBC        (1<<12)
+#define PCMD_DCE        (1<<11)
+#define PCMD_LC (1<<10)
+/* FIXME:  PCMD_SQC need be checked.   */
+#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
+                                   bit 9 should be 0 all day. */
+#define PVCR_VCSA       (0x1<<14)
+#define PVCR_CommandDelay (0xf80)
+#define PCFR_PI2C_EN    (0x1 << 6)
+#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
+#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
+#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
+#define PSSR_STS        (1 << 3)        /* Standby Mode Status */
+#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
+#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
+#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
+#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
+#define PCFR_RO         (1 << 15)       /* RDH Override */
+#define PCFR_PO         (1 << 14)       /* PH Override */
+#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
+#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
+#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
+#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
+#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
+#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
+#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
+#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
+#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
+#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
+#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
+#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
+#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
+#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
+#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
+#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
+#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
+#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
+#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
+#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
+#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
+#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
+#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
+#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
+#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
+#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
+#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
+#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
+#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
+#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
+#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
+#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
+/*
+ * PXA2xx specific Core clock definitions
+ */
+#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
+#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
+#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
+#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
+#define CCCR_N_MASK     0x0380  /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define CCCR_M_MASK     0x0060  /* Memory Frequency to Run Mode Frequency Multiplier */
+#define CCCR_L_MASK     0x001f  /* Crystal Frequency to Memory Frequency Multiplier */
+#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */
+#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
+#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
+#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
+#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
+#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
+#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
+#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
+#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
+#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
+#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
+#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
+#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
+#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
+#define CKEN_USB        (11)    /* USB Unit Clock Enable */
+#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
+#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
+#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
+#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
+#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
+#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
+#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
+#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
+#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
+#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
+#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
+#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
+#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
+#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
+#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
+#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
 #endif
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index 9aa6c2e939e8..ba7e132de1b3 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -12,6 +12,7 @@
 #include <asm/proc-fns.h>
 #include "hardware.h"
+#include "pxa2xx-regs.h"
 #include "pxa-regs.h"
 static inline void arch_idle(void)
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index 4881b80f0f90..de577de8d18c 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -15,7 +15,6 @@ struct platform_mmc_slot {
 extern struct platform_mmc_slot zylonite_mmc_slot[];
-extern int gpio_backlight;
 extern int gpio_eth_irq;
 extern int wm9713_irq;
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index b4da08d7a336..6bd2295c0e01 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -126,7 +126,7 @@ static inline unsigned sz __in##fnsuffix (unsigned int port)		\
        return (unsigned sz)value;                                              \
 }
-static inline void __iomem *__ioaddr(unsigned int port)
+static inline void __iomem *__deprecated __ioaddr(unsigned int port)
 {
        void __iomem *ret;
        if (__PORT_PCIO(port))
@@ -232,8 +232,7 @@ DECLARE_IO(int,l,"")
        result;                                                                 \
 })
-#define __ioaddrc(port)         \
+#define __ioaddrc(port)         __ioaddr(port)
-        ((__PORT_PCIO(port) ? PCIO_BASE : IO_BASE) + ((port) << 2))
 #define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
 #define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index fce832820825..911393b2c6f0 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -56,6 +56,21 @@
 #endif
 /*
+ * This can be used to enable code to cacheline align the destination
+ * pointer when bulk writing to memory.  Experiments on StrongARM and
+ * XScale didn't show this a worthwhile thing to do when the cache is not
+ * set to write-allocate (this would need further testing on XScale when WA
+ * is used).
+ *
+ * On Feroceon there is much to gain however, regardless of cache mode.
+ */
+#ifdef CONFIG_CPU_FEROCEON
+#define CALGN(code...) code
+#else
+#define CALGN(code...)
+#endif
+/*
 * Enable and disable interrupts
 */
 #if __LINUX_ARM_ARCH__ >= 6
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 759a97b56eed..70b0fe724b62 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -95,11 +95,7 @@
 #endif
 #if defined(CONFIG_CPU_FEROCEON)
-# ifdef _CACHE
+# define MULTI_CACHE 1
-#  define MULTI_CACHE 1
-# else
-#  define _CACHE feroceon
-# endif
 #endif
 #if defined(CONFIG_CPU_V6)
@@ -410,6 +406,13 @@ extern void flush_dcache_page(struct page *);
 extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
+static inline void __flush_icache_all(void)
+{
+        asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
+            :
+            : "r" (0));
+}
 #define ARCH_HAS_FLUSH_ANON_PAGE
 static inline void flush_anon_page(struct vm_area_struct *vma,
                         struct page *page, unsigned long vmaddr)
diff --git a/include/asm-arm/dyntick.h b/include/asm-arm/dyntick.h
deleted file mode 100644
index 19fab2d2b760..000000000000
--- a/include/asm-arm/dyntick.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASMARM_DYNTICK_H
-#define _ASMARM_DYNTICK_H
-#include <asm/mach/time.h>
-#endif /* _ASMARM_DYNTICK_H */
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
index 684fe0645239..5e22881a630d 100644
--- a/include/asm-arm/ecard.h
+++ b/include/asm-arm/ecard.h
@@ -85,19 +85,6 @@
 #define MAX_ECARDS      9
-typedef enum {                          /* Cards address space          */
-        ECARD_IOC,
-        ECARD_MEMC,
-        ECARD_EASI
-} card_type_t;
-typedef enum {                          /* Speed for ECARD_IOC space    */
-        ECARD_SLOW       = 0,
-        ECARD_MEDIUM     = 1,
-        ECARD_FAST       = 2,
-        ECARD_SYNC       = 3
-} card_speed_t;
 struct ecard_id {                       /* Card ID structure            */
        unsigned short  manufacturer;
        unsigned short  product;
@@ -190,16 +177,6 @@ struct in_chunk_dir {
 };
 /*
- * ecard_claim: claim an expansion card entry
- */
-#define ecard_claim(ec) ((ec)->claimed = 1)
-/*
- * ecard_release: release an expansion card entry
- */
-#define ecard_release(ec) ((ec)->claimed = 0)
-/*
 * Read a chunk from an expansion card
 * cd : where to put read data
 * ec : expansion card info struct
@@ -209,18 +186,6 @@ struct in_chunk_dir {
 extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num);
 /*
- * Obtain the address of a card.  This returns the "old style" address
- * and should no longer be used.
- */
-static inline unsigned int __deprecated
-ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed)
-{
-        extern unsigned int __ecard_address(struct expansion_card *,
-                                            card_type_t, card_speed_t);
-        return __ecard_address(ec, type, speed);
-}
-/*
 * Request and release ecard resources
 */
 extern int ecard_request_resources(struct expansion_card *ec);
diff --git a/include/asm-arm/ftrace.h b/include/asm-arm/ftrace.h
new file mode 100644
index 000000000000..584ef9a8e5a5
--- /dev/null
+++ b/include/asm-arm/ftrace.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_ARM_FTRACE
+#define _ASM_ARM_FTRACE
+#ifdef CONFIG_FTRACE
+#define MCOUNT_ADDR             ((long)(mcount))
+#define MCOUNT_INSN_SIZE        4 /* sizeof mcount call */
+#ifndef __ASSEMBLY__
+extern void mcount(void);
+#endif
+#endif
+#endif /* _ASM_ARM_FTRACE */
diff --git a/include/asm-arm/hardware/iop3xx-gpio.h b/include/asm-arm/hardware/iop3xx-gpio.h
new file mode 100644
index 000000000000..0c9331f9ac24
--- /dev/null
+++ b/include/asm-arm/hardware/iop3xx-gpio.h
@@ -0,0 +1,73 @@
+/*
+ * linux/include/asm-arm/hardware/iop3xx-gpio.h
+ *
+ * IOP3xx GPIO wrappers
+ *
+ * Copyright (c) 2008 Arnaud Patard <arnaud.patard@rtp-net.org>
+ * Based on IXP4XX gpio.h file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
+#define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
+#include <asm/hardware.h>
+#include <asm-generic/gpio.h>
+#define IOP3XX_N_GPIOS  8
+static inline int gpio_get_value(unsigned gpio)
+{
+        if (gpio > IOP3XX_N_GPIOS)
+                return __gpio_get_value(gpio);
+        return gpio_line_get(gpio);
+}
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        if (gpio > IOP3XX_N_GPIOS) {
+                __gpio_set_value(gpio, value);
+                return;
+        }
+        gpio_line_set(gpio, value);
+}
+static inline int gpio_cansleep(unsigned gpio)
+{
+        if (gpio < IOP3XX_N_GPIOS)
+                return 0;
+        else
+                return __gpio_cansleep(gpio);
+}
+/*
+ * The GPIOs are not generating any interrupt
+ * Note : manuals are not clear about this
+ */
+static inline int gpio_to_irq(int gpio)
+{
+        return -EINVAL;
+}
+static inline int irq_to_gpio(int gpio)
+{
+        return -EINVAL;
+}
+#endif
diff --git a/include/asm-arm/hw_irq.h b/include/asm-arm/hw_irq.h
index 98d594a973d6..f1a08a500604 100644
--- a/include/asm-arm/hw_irq.h
+++ b/include/asm-arm/hw_irq.h
@@ -6,15 +6,4 @@
 #include <asm/mach/irq.h>
-#if defined(CONFIG_NO_IDLE_HZ)
-# include <asm/dyntick.h>
-# define handle_dynamic_tick(action)                                    \
-        if (!(action->flags & IRQF_TIMER) && system_timer->dyn_tick) {  \
-                write_seqlock(&xtime_lock);                             \
-                if (system_timer->dyn_tick->state & DYN_TICK_ENABLED)   \
-                        system_timer->dyn_tick->handler(irq, NULL);     \
-                write_sequnlock(&xtime_lock);                           \
-        }
-#endif
 #endif
diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h
index 47fe34d692da..c8986bb99ed5 100644
--- a/include/asm-arm/kexec.h
+++ b/include/asm-arm/kexec.h
@@ -14,8 +14,6 @@
 #define KEXEC_ARCH KEXEC_ARCH_ARM
-#define KEXEC_BOOT_PARAMS_SIZE 1536
 #define KEXEC_ARM_ATAGS_OFFSET  0x1000
 #define KEXEC_ARM_ZIMAGE_OFFSET 0x8000
diff --git a/include/asm-arm/kprobes.h b/include/asm-arm/kprobes.h
index c042194d3ab5..b1a37876942d 100644
--- a/include/asm-arm/kprobes.h
+++ b/include/asm-arm/kprobes.h
@@ -59,6 +59,7 @@ struct kprobe_ctlblk {
 };
 void arch_remove_kprobe(struct kprobe *);
+void kretprobe_trampoline(void);
 int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr);
 int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr);
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 5dc357013b79..2fd36ea0130d 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -41,30 +41,8 @@ struct sys_timer {
 #ifndef CONFIG_GENERIC_TIME
        unsigned long           (*offset)(void);
 #endif
-#ifdef CONFIG_NO_IDLE_HZ
-        struct dyn_tick_timer   *dyn_tick;
-#endif
-};
-#ifdef CONFIG_NO_IDLE_HZ
-#define DYN_TICK_ENABLED        (1 << 1)
-struct dyn_tick_timer {
-        spinlock_t      lock;
-        unsigned int    state;                  /* Current state */
-        int             (*enable)(void);        /* Enables dynamic tick */
-        int             (*disable)(void);       /* Disables dynamic tick */
-        void            (*reprogram)(unsigned long); /* Reprograms the timer */
-        int             (*handler)(int, void *);
 };
-void timer_dyn_reprogram(void);
-#else
-#define timer_dyn_reprogram()   do { } while (0)
-#endif
 extern struct sys_timer *system_timer;
 extern void timer_tick(void);
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 6913d02ca5d6..91b9dfdfed52 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -97,6 +97,11 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #ifdef CONFIG_MMU
        unsigned int cpu = smp_processor_id();
+#ifdef CONFIG_SMP
+        /* check for possible thread migration */
+        if (!cpus_empty(next->cpu_vm_mask) && !cpu_isset(cpu, next->cpu_vm_mask))
+                __flush_icache_all();
+#endif
        if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) {
                check_context(next);
                cpu_switch_mm(next->pgd, next);
diff --git a/include/asm-arm/plat-orion/cache-feroceon-l2.h b/include/asm-arm/plat-orion/cache-feroceon-l2.h
new file mode 100644
index 000000000000..ba4e016d3ec0
--- /dev/null
+++ b/include/asm-arm/plat-orion/cache-feroceon-l2.h
@@ -0,0 +1,11 @@
+/*
+ * include/asm-arm/plat-orion/cache-feroceon-l2.h
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+extern void __init feroceon_l2_init(int l2_wt_override);
diff --git a/include/asm-arm/plat-orion/orion_nand.h b/include/asm-arm/plat-orion/orion_nand.h
index ffd3852a0dd7..ad4ce94c1998 100644
--- a/include/asm-arm/plat-orion/orion_nand.h
+++ b/include/asm-arm/plat-orion/orion_nand.h
@@ -18,6 +18,7 @@ struct orion_nand_data {
        u8 ale;         /* address line number connected to ALE */
        u8 cle;         /* address line number connected to CLE */
        u8 width;       /* buswidth */
+        u8 chip_delay;
 };
diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h
index 6434ac685d21..e61b7bd97af5 100644
--- a/include/asm-arm/plat-orion/pcie.h
+++ b/include/asm-arm/plat-orion/pcie.h
@@ -14,6 +14,7 @@
 u32 orion_pcie_dev_id(void __iomem *base);
 u32 orion_pcie_rev(void __iomem *base);
 int orion_pcie_link_up(void __iomem *base);
+int orion_pcie_x4_mode(void __iomem *base);
 int orion_pcie_get_local_bus_nr(void __iomem *base);
 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
 void orion_pcie_setup(void __iomem *base,
diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h
deleted file mode 100644
index 1a5c9232a91e..000000000000
--- a/include/asm-arm/rtc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  linux/include/asm-arm/rtc.h
- *
- *  Copyright (C) 2003 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_RTC_H
-#define ASMARM_RTC_H
-struct module;
-struct rtc_ops {
-        struct module   *owner;
-        int             (*open)(void);
-        void            (*release)(void);
-        int             (*ioctl)(unsigned int, unsigned long);
-        int             (*read_time)(struct rtc_time *);
-        int             (*set_time)(struct rtc_time *);
-        int             (*read_alarm)(struct rtc_wkalrm *);
-        int             (*set_alarm)(struct rtc_wkalrm *);
-        int             (*proc)(char *buf);
-};
-void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *);
-void rtc_update(unsigned long, unsigned long);
-int register_rtc(struct rtc_ops *);
-void unregister_rtc(struct rtc_ops *);
-static inline int rtc_periodic_alarm(struct rtc_time *tm)
-{
-        return  (tm->tm_year == -1) ||
-                ((unsigned)tm->tm_mon >= 12) ||
-                ((unsigned)(tm->tm_mday - 1) >= 31) ||
-                ((unsigned)tm->tm_hour > 23) ||
-                ((unsigned)tm->tm_min > 59) ||
-                ((unsigned)tm->tm_sec > 59);
-}
-#endif
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8c6bc1bb9d1a..909656c747ef 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -39,6 +39,7 @@
 #define TLB_V6_D_ASID   (1 << 17)
 #define TLB_V6_I_ASID   (1 << 18)
+#define TLB_L2CLEAN_FR  (1 << 29)               /* Feroceon */
 #define TLB_DCLEAN      (1 << 30)
 #define TLB_WB          (1 << 31)
@@ -51,6 +52,7 @@
 *        v4    - ARMv4 without write buffer
 *        v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
 *        v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
+ *        fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
 *        v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
 */
 #undef _TLB
@@ -103,6 +105,23 @@
 # define v4wbi_always_flags     (-1UL)
 #endif
+#define fr_tlb_flags    (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
+                         TLB_V4_I_FULL | TLB_V4_D_FULL | \
+                         TLB_V4_I_PAGE | TLB_V4_D_PAGE)
+#ifdef CONFIG_CPU_TLB_FEROCEON
+# define fr_possible_flags      fr_tlb_flags
+# define fr_always_flags        fr_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB v4wbi
+# endif
+#else
+# define fr_possible_flags      0
+# define fr_always_flags        (-1UL)
+#endif
 #define v4wb_tlb_flags  (TLB_WB | TLB_DCLEAN | \
                         TLB_V4_I_FULL | TLB_V4_D_FULL | \
                         TLB_V4_D_PAGE)
@@ -245,12 +264,14 @@ extern struct cpu_tlb_fns cpu_tlb;
 #define possible_tlb_flags      (v3_possible_flags | \
                                 v4_possible_flags | \
                                 v4wbi_possible_flags | \
+                                 fr_possible_flags | \
                                 v4wb_possible_flags | \
                                 v6wbi_possible_flags)
 #define always_tlb_flags        (v3_always_flags & \
                                 v4_always_flags & \
                                 v4wbi_always_flags & \
+                                 fr_always_flags & \
                                 v4wb_always_flags & \
                                 v6wbi_always_flags)
@@ -417,6 +438,11 @@ static inline void flush_pmd_entry(pmd_t *pmd)
        if (tlb_flag(TLB_DCLEAN))
                asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
                        : : "r" (pmd) : "cc");
+        if (tlb_flag(TLB_L2CLEAN_FR))
+                asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
+                        : : "r" (pmd) : "cc");
        if (tlb_flag(TLB_WB))
                dsb();
 }
@@ -428,6 +454,10 @@ static inline void clean_pmd_entry(pmd_t *pmd)
        if (tlb_flag(TLB_DCLEAN))
                asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
                        : : "r" (pmd) : "cc");
+        if (tlb_flag(TLB_L2CLEAN_FR))
+                asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
+                        : : "r" (pmd) : "cc");
 }
 #undef tlb_flag
author	Ben Dooks <ben-linux@fluff.org>	2008-07-15 15:19:14 -0400
committer	Ben Dooks <ben-linux@fluff.org>	2008-07-15 15:19:14 -0400
commit	0c17e4ceedd35c78b1c7413dbd16279a350be6bc (patch)
tree	313b3b9ca04727f3704464e01d8dd97da1dd534b /include/asm-arm
parent	19c1d6a34abf73d0baf8e325d018c920fa78dddc (diff)
parent	b9d2252c1e44fa83a4e65fdc9eb93db6297c55af (diff)