diff options
author | Roland Dreier <rolandd@cisco.com> | 2005-10-24 13:55:29 -0400 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2005-10-24 13:55:29 -0400 |
commit | ec329a135974f1c400214dab02f09584d4beeba9 (patch) | |
tree | 235be754f76f4e7d51975d2434f226cfc75cdd08 /include/asm-arm | |
parent | bbf207860931b6a033d0fbcd170ae2332c0d8216 (diff) | |
parent | 5d7edb3c1a01310725d86f0d83fb3be45685dc82 (diff) |
Manual merge of for-linus to upstream (fix conflicts in drivers/infiniband/core/ucm.c)
Diffstat (limited to 'include/asm-arm')
-rw-r--r-- | include/asm-arm/arch-ixp4xx/entry-macro.S | 9 | ||||
-rw-r--r-- | include/asm-arm/arch-ixp4xx/hardware.h | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 2 | ||||
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-clock.h | 21 | ||||
-rw-r--r-- | include/asm-arm/locks.h | 4 |
5 files changed, 26 insertions, 12 deletions
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S index 455da64832de..323b0bc4a39c 100644 --- a/include/asm-arm/arch-ixp4xx/entry-macro.S +++ b/include/asm-arm/arch-ixp4xx/entry-macro.S | |||
@@ -15,25 +15,26 @@ | |||
15 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) | 15 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) |
16 | ldr \irqstat, [\irqstat] @ get interrupts | 16 | ldr \irqstat, [\irqstat] @ get interrupts |
17 | cmp \irqstat, #0 | 17 | cmp \irqstat, #0 |
18 | beq 1001f | 18 | beq 1001f @ upper IRQ? |
19 | clz \irqnr, \irqstat | 19 | clz \irqnr, \irqstat |
20 | mov \base, #31 | 20 | mov \base, #31 |
21 | subs \irqnr, \base, \irqnr | 21 | sub \irqnr, \base, \irqnr |
22 | b 1002f @ lower IRQ being | ||
23 | @ handled | ||
22 | 24 | ||
23 | 1001: | 25 | 1001: |
24 | /* | 26 | /* |
25 | * IXP465 has an upper IRQ status register | 27 | * IXP465 has an upper IRQ status register |
26 | */ | 28 | */ |
27 | #if defined(CONFIG_CPU_IXP46X) | 29 | #if defined(CONFIG_CPU_IXP46X) |
28 | bne 1002f | ||
29 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET) | 30 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET) |
30 | ldr \irqstat, [\irqstat] @ get upper interrupts | 31 | ldr \irqstat, [\irqstat] @ get upper interrupts |
31 | mov \irqnr, #63 | 32 | mov \irqnr, #63 |
32 | clz \irqstat, \irqstat | 33 | clz \irqstat, \irqstat |
33 | cmp \irqstat, #32 | 34 | cmp \irqstat, #32 |
34 | subne \irqnr, \irqnr, \irqstat | 35 | subne \irqnr, \irqnr, \irqstat |
35 | 1002: | ||
36 | #endif | 36 | #endif |
37 | 1002: | ||
37 | .endm | 38 | .endm |
38 | 39 | ||
39 | 40 | ||
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h index 4ac964b9078a..55d85eea8c1a 100644 --- a/include/asm-arm/arch-ixp4xx/hardware.h +++ b/include/asm-arm/arch-ixp4xx/hardware.h | |||
@@ -27,7 +27,7 @@ | |||
27 | 27 | ||
28 | #define pcibios_assign_all_busses() 1 | 28 | #define pcibios_assign_all_busses() 1 |
29 | 29 | ||
30 | #if defined(CONFIG_CPU_IXP465) && !defined(__ASSEMBLY__) | 30 | #if defined(CONFIG_CPU_IXP46X) && !defined(__ASSEMBLY__) |
31 | extern unsigned int processor_id; | 31 | extern unsigned int processor_id; |
32 | #define cpu_is_ixp465() ((processor_id & 0xffffffc0) == 0x69054200) | 32 | #define cpu_is_ixp465() ((processor_id & 0xffffffc0) == 0x69054200) |
33 | #else | 33 | #else |
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 13fa2deb4ddd..3af7165ab0d7 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
@@ -653,7 +653,7 @@ | |||
653 | 653 | ||
654 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ | 654 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ |
655 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ | 655 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ |
656 | #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ | 656 | #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ |
657 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ | 657 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ |
658 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ | 658 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ |
659 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ | 659 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ |
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index 16f4c3cc1388..34360706e016 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h | |||
@@ -18,7 +18,9 @@ | |||
18 | * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) | 18 | * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) |
19 | * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA | 19 | * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA |
20 | * 27-Aug-2005 Ben Dooks Add clock-slow info | 20 | * 27-Aug-2005 Ben Dooks Add clock-slow info |
21 | */ | 21 | * 20-Oct-2005 Ben Dooks Fixed overflow in PLL (Guillaume Gourat) |
22 | * 20-Oct-2005 Ben Dooks Add masks for DCLK (Guillaume Gourat) | ||
23 | */ | ||
22 | 24 | ||
23 | #ifndef __ASM_ARM_REGS_CLOCK | 25 | #ifndef __ASM_ARM_REGS_CLOCK |
24 | #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" | 26 | #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" |
@@ -66,11 +68,16 @@ | |||
66 | #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) | 68 | #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) |
67 | #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) | 69 | #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) |
68 | #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) | 70 | #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) |
71 | #define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4) | ||
72 | #define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8) | ||
69 | 73 | ||
70 | #define S3C2410_DCLKCON_DCLK1EN (1<<16) | 74 | #define S3C2410_DCLKCON_DCLK1EN (1<<16) |
71 | #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) | 75 | #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) |
72 | #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) | 76 | #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) |
73 | #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) | 77 | #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) |
78 | #define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24) | ||
79 | #define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20) | ||
80 | #define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24) | ||
74 | 81 | ||
75 | #define S3C2410_CLKDIVN_PDIVN (1<<0) | 82 | #define S3C2410_CLKDIVN_PDIVN (1<<0) |
76 | #define S3C2410_CLKDIVN_HDIVN (1<<1) | 83 | #define S3C2410_CLKDIVN_HDIVN (1<<1) |
@@ -83,10 +90,13 @@ | |||
83 | 90 | ||
84 | #ifndef __ASSEMBLY__ | 91 | #ifndef __ASSEMBLY__ |
85 | 92 | ||
93 | #include <asm/div64.h> | ||
94 | |||
86 | static inline unsigned int | 95 | static inline unsigned int |
87 | s3c2410_get_pll(int pllval, int baseclk) | 96 | s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) |
88 | { | 97 | { |
89 | int mdiv, pdiv, sdiv; | 98 | unsigned int mdiv, pdiv, sdiv; |
99 | uint64_t fvco; | ||
90 | 100 | ||
91 | mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; | 101 | mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; |
92 | pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; | 102 | pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; |
@@ -96,7 +106,10 @@ s3c2410_get_pll(int pllval, int baseclk) | |||
96 | pdiv &= S3C2410_PLLCON_PDIVMASK; | 106 | pdiv &= S3C2410_PLLCON_PDIVMASK; |
97 | sdiv &= S3C2410_PLLCON_SDIVMASK; | 107 | sdiv &= S3C2410_PLLCON_SDIVMASK; |
98 | 108 | ||
99 | return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv); | 109 | fvco = (uint64_t)baseclk * (mdiv + 8); |
110 | do_div(fvco, (pdiv + 2) << sdiv); | ||
111 | |||
112 | return (unsigned int)fvco; | ||
100 | } | 113 | } |
101 | 114 | ||
102 | #endif /* __ASSEMBLY__ */ | 115 | #endif /* __ASSEMBLY__ */ |
diff --git a/include/asm-arm/locks.h b/include/asm-arm/locks.h index f08dc8447913..852220eecdbc 100644 --- a/include/asm-arm/locks.h +++ b/include/asm-arm/locks.h | |||
@@ -103,7 +103,7 @@ | |||
103 | ({ \ | 103 | ({ \ |
104 | smp_mb(); \ | 104 | smp_mb(); \ |
105 | __asm__ __volatile__( \ | 105 | __asm__ __volatile__( \ |
106 | "@ up_op_read\n" \ | 106 | "@ up_op_write\n" \ |
107 | "1: ldrex lr, [%0]\n" \ | 107 | "1: ldrex lr, [%0]\n" \ |
108 | " adds lr, lr, %1\n" \ | 108 | " adds lr, lr, %1\n" \ |
109 | " strex ip, lr, [%0]\n" \ | 109 | " strex ip, lr, [%0]\n" \ |
@@ -231,7 +231,7 @@ | |||
231 | #define __up_op_write(ptr,wake) \ | 231 | #define __up_op_write(ptr,wake) \ |
232 | ({ \ | 232 | ({ \ |
233 | __asm__ __volatile__( \ | 233 | __asm__ __volatile__( \ |
234 | "@ up_op_read\n" \ | 234 | "@ up_op_write\n" \ |
235 | " mrs ip, cpsr\n" \ | 235 | " mrs ip, cpsr\n" \ |
236 | " orr lr, ip, #128\n" \ | 236 | " orr lr, ip, #128\n" \ |
237 | " msr cpsr_c, lr\n" \ | 237 | " msr cpsr_c, lr\n" \ |