diff options
| author | Lennert Buytenhek <buytenh@wantstofly.org> | 2006-09-18 18:21:38 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-25 05:25:45 -0400 |
| commit | 38ce73ebd74a9a1738b73619557f2397c59ba628 (patch) | |
| tree | 02c812c665d0bb9c6872f81ad64328306fa3157f /include/asm-arm | |
| parent | 0b29de4a6ac0936f56b974a3c19bd9c24ac5b5d7 (diff) | |
[ARM] 3825/1: iop3xx: use cp6 enable/disable macros
Add CP6 enable/disable sequences to the timekeeping code and the IRQ
code. As a result, we can't depend on CP6 access being enabled when
we enter get_irqnr_and_base anymore, so switch the latter over to
using memory-mapped accesses for now.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
| -rw-r--r-- | include/asm-arm/arch-iop32x/entry-macro.S | 3 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop33x/entry-macro.S | 5 |
2 files changed, 5 insertions, 3 deletions
diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S index 52d9435c6a34..00038c17317a 100644 --- a/include/asm-arm/arch-iop32x/entry-macro.S +++ b/include/asm-arm/arch-iop32x/entry-macro.S | |||
| @@ -17,7 +17,8 @@ | |||
| 17 | */ | 17 | */ |
| 18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 19 | mov \irqnr, #0 | 19 | mov \irqnr, #0 |
| 20 | mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC | 20 | ldr \base, =IOP3XX_REG_ADDR(0x07D8) |
| 21 | ldr \irqstat, [\base] @ Read IINTSRC | ||
| 21 | cmp \irqstat, #0 | 22 | cmp \irqstat, #0 |
| 22 | beq 1001f | 23 | beq 1001f |
| 23 | clz \irqnr, \irqstat | 24 | clz \irqnr, \irqstat |
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S index 980ec9b1ac83..57f6ea0069e4 100644 --- a/include/asm-arm/arch-iop33x/entry-macro.S +++ b/include/asm-arm/arch-iop33x/entry-macro.S | |||
| @@ -17,10 +17,11 @@ | |||
| 17 | */ | 17 | */ |
| 18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 19 | mov \irqnr, #0 | 19 | mov \irqnr, #0 |
| 20 | mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0 | 20 | ldr \base, =IOP3XX_REG_ADDR(0x7A0) |
| 21 | ldr \irqstat, [\base] @ Read IINTSRC0 | ||
| 21 | cmp \irqstat, #0 | 22 | cmp \irqstat, #0 |
| 22 | bne 1002f | 23 | bne 1002f |
| 23 | mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1 | 24 | ldr \irqstat, [\base, #4] @ Read IINTSRC1 |
| 24 | cmp \irqstat, #0 | 25 | cmp \irqstat, #0 |
| 25 | beq 1001f | 26 | beq 1001f |
| 26 | clz \irqnr, \irqstat | 27 | clz \irqnr, \irqstat |