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authorDavid Woodhouse <David.Woodhouse@intel.com>2008-07-25 10:40:14 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2008-07-25 10:40:14 -0400
commitff877ea80efa2015b6263766f78ee42c2a1b32f9 (patch)
tree85205005c611ab774702148558321c6fb92f1ccd /include/asm-arm
parent30821fee4f0cb3e6d241d9f7ddc37742212e3eb7 (diff)
parentd37e6bf68fc1eb34a4ad21d9ae8890ed37ea80e7 (diff)
Merge branch 'linux-next' of git://git.infradead.org/~dedekind/ubi-2.6
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-at91/at91_mci.h4
-rw-r--r--include/asm-arm/arch-at91/at91_pmc.h7
-rw-r--r--include/asm-arm/arch-at91/at91cap9.h2
-rw-r--r--include/asm-arm/arch-at91/at91cap9_matrix.h5
-rw-r--r--include/asm-arm/arch-at91/at91sam9260.h11
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl.h2
-rw-r--r--include/asm-arm/arch-at91/board.h6
-rw-r--r--include/asm-arm/arch-at91/cpu.h7
-rw-r--r--include/asm-arm/arch-at91/hardware.h2
-rw-r--r--include/asm-arm/arch-at91/timex.h22
-rw-r--r--include/asm-arm/arch-ebsa285/hardware.h26
-rw-r--r--include/asm-arm/arch-ebsa285/memory.h19
-rw-r--r--include/asm-arm/arch-ebsa285/vmalloc.h4
-rw-r--r--include/asm-arm/arch-imx/hardware.h8
-rw-r--r--include/asm-arm/arch-imx/imx-dma.h2
-rw-r--r--include/asm-arm/arch-imx/imx-uart.h2
-rw-r--r--include/asm-arm/arch-iop13xx/adma.h18
-rw-r--r--include/asm-arm/arch-iop13xx/dma.h2
-rw-r--r--include/asm-arm/arch-iop32x/gpio.h6
-rw-r--r--include/asm-arm/arch-iop33x/gpio.h6
-rw-r--r--include/asm-arm/arch-ixp4xx/fsg.h50
-rw-r--r--include/asm-arm/arch-ixp4xx/hardware.h1
-rw-r--r--include/asm-arm/arch-ixp4xx/irqs.h7
-rw-r--r--include/asm-arm/arch-kirkwood/debug-macro.S20
-rw-r--r--include/asm-arm/arch-kirkwood/dma.h1
-rw-r--r--include/asm-arm/arch-kirkwood/entry-macro.S40
-rw-r--r--include/asm-arm/arch-kirkwood/hardware.h21
-rw-r--r--include/asm-arm/arch-kirkwood/io.h26
-rw-r--r--include/asm-arm/arch-kirkwood/irqs.h63
-rw-r--r--include/asm-arm/arch-kirkwood/kirkwood.h100
-rw-r--r--include/asm-arm/arch-kirkwood/memory.h14
-rw-r--r--include/asm-arm/arch-kirkwood/system.h37
-rw-r--r--include/asm-arm/arch-kirkwood/timex.h11
-rw-r--r--include/asm-arm/arch-kirkwood/uncompress.h47
-rw-r--r--include/asm-arm/arch-kirkwood/vmalloc.h5
-rw-r--r--include/asm-arm/arch-loki/debug-macro.S20
-rw-r--r--include/asm-arm/arch-loki/dma.h1
-rw-r--r--include/asm-arm/arch-loki/entry-macro.S30
-rw-r--r--include/asm-arm/arch-loki/hardware.h15
-rw-r--r--include/asm-arm/arch-loki/io.h26
-rw-r--r--include/asm-arm/arch-loki/irqs.h58
-rw-r--r--include/asm-arm/arch-loki/loki.h97
-rw-r--r--include/asm-arm/arch-loki/memory.h14
-rw-r--r--include/asm-arm/arch-loki/system.h37
-rw-r--r--include/asm-arm/arch-loki/timex.h11
-rw-r--r--include/asm-arm/arch-loki/uncompress.h47
-rw-r--r--include/asm-arm/arch-loki/vmalloc.h5
-rw-r--r--include/asm-arm/arch-msm/irqs.h1
-rw-r--r--include/asm-arm/arch-msm/timex.h1
-rw-r--r--include/asm-arm/arch-mv78xx0/debug-macro.S20
-rw-r--r--include/asm-arm/arch-mv78xx0/dma.h1
-rw-r--r--include/asm-arm/arch-mv78xx0/entry-macro.S39
-rw-r--r--include/asm-arm/arch-mv78xx0/hardware.h21
-rw-r--r--include/asm-arm/arch-mv78xx0/io.h26
-rw-r--r--include/asm-arm/arch-mv78xx0/irqs.h91
-rw-r--r--include/asm-arm/arch-mv78xx0/memory.h14
-rw-r--r--include/asm-arm/arch-mv78xx0/mv78xx0.h126
-rw-r--r--include/asm-arm/arch-mv78xx0/system.h37
-rw-r--r--include/asm-arm/arch-mv78xx0/timex.h9
-rw-r--r--include/asm-arm/arch-mv78xx0/uncompress.h47
-rw-r--r--include/asm-arm/arch-mv78xx0/vmalloc.h5
-rw-r--r--include/asm-arm/arch-mxc/board-mx27ads.h354
-rw-r--r--include/asm-arm/arch-mxc/board-mx31ads.h5
-rw-r--r--include/asm-arm/arch-mxc/board-mx31lite.h38
-rw-r--r--include/asm-arm/arch-mxc/board-pcm037.h27
-rw-r--r--include/asm-arm/arch-mxc/board-pcm038.h41
-rw-r--r--include/asm-arm/arch-mxc/clock.h67
-rw-r--r--include/asm-arm/arch-mxc/common.h6
-rw-r--r--include/asm-arm/arch-mxc/debug-macro.S49
-rw-r--r--include/asm-arm/arch-mxc/gpio.h42
-rw-r--r--include/asm-arm/arch-mxc/hardware.h38
-rw-r--r--include/asm-arm/arch-mxc/iim.h77
-rw-r--r--include/asm-arm/arch-mxc/imx-uart.h32
-rw-r--r--include/asm-arm/arch-mxc/iomux-mx1-mx2.h372
-rw-r--r--include/asm-arm/arch-mxc/iomux-mx3.h501
-rw-r--r--include/asm-arm/arch-mxc/irqs.h13
-rw-r--r--include/asm-arm/arch-mxc/mx27.h302
-rw-r--r--include/asm-arm/arch-mxc/mx31.h21
-rw-r--r--include/asm-arm/arch-mxc/mxc.h152
-rw-r--r--include/asm-arm/arch-mxc/mxc_timer.h158
-rw-r--r--include/asm-arm/arch-ns9xxx/hardware.h4
-rw-r--r--include/asm-arm/arch-omap/board-2430sdp.h5
-rw-r--r--include/asm-arm/arch-omap/board-h3.h6
-rw-r--r--include/asm-arm/arch-omap/board-innovator.h3
-rw-r--r--include/asm-arm/arch-omap/board-perseus2.h6
-rw-r--r--include/asm-arm/arch-omap/clock.h17
-rw-r--r--include/asm-arm/arch-omap/common.h15
-rw-r--r--include/asm-arm/arch-omap/control.h4
-rw-r--r--include/asm-arm/arch-omap/cpu.h39
-rw-r--r--include/asm-arm/arch-omap/dma.h378
-rw-r--r--include/asm-arm/arch-omap/dmtimer.h1
-rw-r--r--include/asm-arm/arch-omap/fpga.h49
-rw-r--r--include/asm-arm/arch-omap/hardware.h1
-rw-r--r--include/asm-arm/arch-omap/io.h26
-rw-r--r--include/asm-arm/arch-omap/irqs.h44
-rw-r--r--include/asm-arm/arch-omap/mcbsp.h62
-rw-r--r--include/asm-arm/arch-omap/omap34xx.h72
-rw-r--r--include/asm-arm/arch-omap/sram.h37
-rw-r--r--include/asm-arm/arch-omap/tc.h10
-rw-r--r--include/asm-arm/arch-omap/usb.h23
-rw-r--r--include/asm-arm/arch-orion5x/io.h8
-rw-r--r--include/asm-arm/arch-orion5x/orion5x.h7
-rw-r--r--include/asm-arm/arch-orion5x/uncompress.h29
-rw-r--r--include/asm-arm/arch-pxa/audio.h2
-rw-r--r--include/asm-arm/arch-pxa/cm-x270.h50
-rw-r--r--include/asm-arm/arch-pxa/eseries-gpio.h50
-rw-r--r--include/asm-arm/arch-pxa/eseries-irq.h27
-rw-r--r--include/asm-arm/arch-pxa/hardware.h40
-rw-r--r--include/asm-arm/arch-pxa/irda.h4
-rw-r--r--include/asm-arm/arch-pxa/irqs.h3
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa2xx.h1
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa930.h491
-rw-r--r--include/asm-arm/arch-pxa/mfp.h8
-rw-r--r--include/asm-arm/arch-pxa/palmtx.h106
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h570
-rw-r--r--include/asm-arm/arch-pxa/pxa25x-udc.h163
-rw-r--r--include/asm-arm/arch-pxa/pxa27x-udc.h257
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-gpio.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-regs.h162
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx_spi.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx_nand.h2
-rw-r--r--include/asm-arm/arch-pxa/pxafb.h3
-rw-r--r--include/asm-arm/arch-pxa/regs-lcd.h6
-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h16
-rw-r--r--include/asm-arm/arch-pxa/system.h18
-rw-r--r--include/asm-arm/arch-pxa/tosa.h50
-rw-r--r--include/asm-arm/arch-pxa/tosa_bt.h22
-rw-r--r--include/asm-arm/arch-pxa/uncompress.h13
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h3
-rw-r--r--include/asm-arm/arch-rpc/io.h5
-rw-r--r--include/asm-arm/arch-s3c2410/gpio.h74
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h2
-rw-r--r--include/asm-arm/arch-s3c2410/regs-sdi.h20
-rw-r--r--include/asm-arm/assembler.h15
-rw-r--r--include/asm-arm/cacheflush.h13
-rw-r--r--include/asm-arm/dyntick.h6
-rw-r--r--include/asm-arm/ecard.h35
-rw-r--r--include/asm-arm/ftrace.h14
-rw-r--r--include/asm-arm/hardware/iop3xx-adma.h4
-rw-r--r--include/asm-arm/hardware/iop3xx-gpio.h73
-rw-r--r--include/asm-arm/hw_irq.h11
-rw-r--r--include/asm-arm/kexec.h2
-rw-r--r--include/asm-arm/kgdb.h104
-rw-r--r--include/asm-arm/kprobes.h1
-rw-r--r--include/asm-arm/mach/time.h22
-rw-r--r--include/asm-arm/mach/udc_pxa2xx.h1
-rw-r--r--include/asm-arm/mmu_context.h5
-rw-r--r--include/asm-arm/plat-orion/cache-feroceon-l2.h11
-rw-r--r--include/asm-arm/plat-orion/mv_xor.h28
-rw-r--r--include/asm-arm/plat-orion/orion_nand.h1
-rw-r--r--include/asm-arm/plat-orion/pcie.h1
-rw-r--r--include/asm-arm/plat-s3c/regs-timer.h9
-rw-r--r--include/asm-arm/plat-s3c24xx/devs.h7
-rw-r--r--include/asm-arm/plat-s3c24xx/mci.h15
-rw-r--r--include/asm-arm/rtc.h43
-rw-r--r--include/asm-arm/smp.h3
-rw-r--r--include/asm-arm/tlbflush.h30
-rw-r--r--include/asm-arm/traps.h2
158 files changed, 5783 insertions, 1389 deletions
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
index 1551fc24eb43..400ec10014b4 100644
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ b/include/asm-arm/arch-at91/at91_mci.h
@@ -75,6 +75,10 @@
75#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) 75#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
76#define AT91_MCI_TRTYP_STREAM (2 << 19) 76#define AT91_MCI_TRTYP_STREAM (2 << 19)
77 77
78#define AT91_MCI_BLKR 0x18 /* Block Register */
79#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
80#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */
81
78#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ 82#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
79#define AT91_MCR_RDR 0x30 /* Receive Data Register */ 83#define AT91_MCR_RDR 0x30 /* Receive Data Register */
80#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ 84#define AT91_MCR_TDR 0x34 /* Transmit Data Register */
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index c2b13c280155..2001e81f2267 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -39,10 +39,14 @@
39#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ 39#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
40 40
41#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ 41#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
42#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
43#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
44#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
45#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
42 46
43#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ 47#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
44#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 48#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
45#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ 49#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
46#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 50#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
47 51
48#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ 52#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
@@ -97,6 +101,7 @@
97#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 101#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
98#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 102#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
99#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ 103#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
104#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
100#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ 105#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
101#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ 106#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
102#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ 107#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
index bac83adb5050..6f14d9053ac7 100644
--- a/include/asm-arm/arch-at91/at91cap9.h
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -118,7 +118,7 @@
118#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ 118#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
119 119
120#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ 120#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
121#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */ 121#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
122#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ 122#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
123 123
124#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 124#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
index a641686b6c3d..ddbd4873c842 100644
--- a/include/asm-arm/arch-at91/at91cap9_matrix.h
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -106,6 +106,11 @@
106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ 106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ 107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
108 108
109#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
110#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
111#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
112#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
113
109#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ 114#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
110#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ 115#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
111#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 116#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index c8934fe34dc5..889872a3f2a9 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -6,6 +6,8 @@
6 * Common definitions. 6 * Common definitions.
7 * Based on AT91SAM9260 datasheet revision A (Preliminary). 7 * Based on AT91SAM9260 datasheet revision A (Preliminary).
8 * 8 *
9 * Includes also definitions for AT91SAM9XE and AT91SAM9G families
10 *
9 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License, or
@@ -123,5 +125,14 @@
123#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ 125#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
124#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 126#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
125 127
128#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
129#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
130
131#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
132#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
133#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
134#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
135
136#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
126 137
127#endif 138#endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 16d2832f6c0a..622e56f81d42 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -110,6 +110,6 @@
110#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ 110#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
111 111
112#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ 112#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
113#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ 113#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
114 114
115#endif 115#endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 6296922a6843..48bbd854f57d 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -36,6 +36,7 @@
36#include <linux/i2c.h> 36#include <linux/i2c.h>
37#include <linux/leds.h> 37#include <linux/leds.h>
38#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
39#include <linux/usb/atmel_usba_udc.h>
39 40
40 /* USB Device */ 41 /* USB Device */
41struct at91_udc_data { 42struct at91_udc_data {
@@ -45,6 +46,9 @@ struct at91_udc_data {
45}; 46};
46extern void __init at91_add_device_udc(struct at91_udc_data *data); 47extern void __init at91_add_device_udc(struct at91_udc_data *data);
47 48
49 /* USB High Speed Device */
50extern void __init at91_add_device_usba(struct usba_platform_data *data);
51
48 /* Compact Flash */ 52 /* Compact Flash */
49struct at91_cf_data { 53struct at91_cf_data {
50 u8 irq_pin; /* I/O IRQ */ 54 u8 irq_pin; /* I/O IRQ */
@@ -73,7 +77,7 @@ struct at91_eth_data {
73}; 77};
74extern void __init at91_add_device_eth(struct at91_eth_data *data); 78extern void __init at91_add_device_eth(struct at91_eth_data *data);
75 79
76#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9) 80#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
77#define eth_platform_data at91_eth_data 81#define eth_platform_data at91_eth_data
78#endif 82#endif
79 83
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 7145166826a2..52df794205cb 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,6 +21,7 @@
21#define ARCH_ID_AT91SAM9260 0x019803a0 21#define ARCH_ID_AT91SAM9260 0x019803a0
22#define ARCH_ID_AT91SAM9261 0x019703a0 22#define ARCH_ID_AT91SAM9261 0x019703a0
23#define ARCH_ID_AT91SAM9263 0x019607a0 23#define ARCH_ID_AT91SAM9263 0x019607a0
24#define ARCH_ID_AT91SAM9G20 0x019905a0
24#define ARCH_ID_AT91SAM9RL64 0x019b03a0 25#define ARCH_ID_AT91SAM9RL64 0x019b03a0
25#define ARCH_ID_AT91CAP9 0x039A03A0 26#define ARCH_ID_AT91CAP9 0x039A03A0
26 27
@@ -63,6 +64,12 @@ static inline unsigned long at91_arch_identify(void)
63#define cpu_is_at91sam9260() (0) 64#define cpu_is_at91sam9260() (0)
64#endif 65#endif
65 66
67#ifdef CONFIG_ARCH_AT91SAM9G20
68#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
69#else
70#define cpu_is_at91sam9g20() (0)
71#endif
72
66#ifdef CONFIG_ARCH_AT91SAM9261 73#ifdef CONFIG_ARCH_AT91SAM9261
67#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) 74#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
68#else 75#else
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 2c826d8247a3..016a3a3f6633 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -18,7 +18,7 @@
18 18
19#if defined(CONFIG_ARCH_AT91RM9200) 19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <asm/arch/at91rm9200.h> 20#include <asm/arch/at91rm9200.h>
21#elif defined(CONFIG_ARCH_AT91SAM9260) 21#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
22#include <asm/arch/at91sam9260.h> 22#include <asm/arch/at91sam9260.h>
23#elif defined(CONFIG_ARCH_AT91SAM9261) 23#elif defined(CONFIG_ARCH_AT91SAM9261)
24#include <asm/arch/at91sam9261.h> 24#include <asm/arch/at91sam9261.h>
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index f1933b0fa43f..298d8313cdac 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -27,14 +27,29 @@
27 27
28#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) 28#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
29 29
30#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) 30#elif defined(CONFIG_ARCH_AT91SAM9260)
31
32#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
33#define AT91SAM9_MASTER_CLOCK 90000000
34#else
35#define AT91SAM9_MASTER_CLOCK 99300000
36#endif
37
38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
39
40#elif defined(CONFIG_ARCH_AT91SAM9261)
31 41
32#define AT91SAM9_MASTER_CLOCK 99300000 42#define AT91SAM9_MASTER_CLOCK 99300000
33#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
34 44
35#elif defined(CONFIG_ARCH_AT91SAM9263) 45#elif defined(CONFIG_ARCH_AT91SAM9263)
36 46
47#if defined(CONFIG_MACH_USB_A9263)
48#define AT91SAM9_MASTER_CLOCK 90000000
49#else
37#define AT91SAM9_MASTER_CLOCK 99959500 50#define AT91SAM9_MASTER_CLOCK 99959500
51#endif
52
38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 53#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
39 54
40#elif defined(CONFIG_ARCH_AT91SAM9RL) 55#elif defined(CONFIG_ARCH_AT91SAM9RL)
@@ -42,6 +57,11 @@
42#define AT91SAM9_MASTER_CLOCK 100000000 57#define AT91SAM9_MASTER_CLOCK 100000000
43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 58#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
44 59
60#elif defined(CONFIG_ARCH_AT91SAM9G20)
61
62#define AT91SAM9_MASTER_CLOCK 132096000
63#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
64
45#elif defined(CONFIG_ARCH_AT91CAP9) 65#elif defined(CONFIG_ARCH_AT91CAP9)
46 66
47#define AT91CAP9_MASTER_CLOCK 100000000 67#define AT91CAP9_MASTER_CLOCK 100000000
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h
index daad8ee2d194..74610c2c63d4 100644
--- a/include/asm-arm/arch-ebsa285/hardware.h
+++ b/include/asm-arm/arch-ebsa285/hardware.h
@@ -14,7 +14,6 @@
14 14
15#include <asm/arch/memory.h> 15#include <asm/arch/memory.h>
16 16
17#ifdef CONFIG_ARCH_FOOTBRIDGE
18/* Virtual Physical Size 17/* Virtual Physical Size
19 * 0xff800000 0x40000000 1MB X-Bus 18 * 0xff800000 0x40000000 1MB X-Bus
20 * 0xff000000 0x7c000000 1MB PCI I/O space 19 * 0xff000000 0x7c000000 1MB PCI I/O space
@@ -50,31 +49,6 @@
50#define PCIMEM_SIZE 0x01000000 49#define PCIMEM_SIZE 0x01000000
51#define PCIMEM_BASE 0xf0000000 50#define PCIMEM_BASE 0xf0000000
52 51
53#elif defined(CONFIG_ARCH_CO285)
54/*
55 * This is the COEBSA285 cut-down mapping
56 */
57#define PCIMEM_SIZE 0x80000000
58#define PCIMEM_BASE 0x80000000
59
60#define WFLUSH_SIZE 0x01000000
61#define WFLUSH_BASE 0x7d000000
62
63#define ARMCSR_SIZE 0x00100000
64#define ARMCSR_BASE 0x7cf00000
65
66#define XBUS_SIZE 0x00020000
67#define XBUS_BASE 0x7cee0000
68
69#define PCIO_SIZE 0x00010000
70#define PCIO_BASE 0x7ced0000
71
72#else
73
74#error "Undefined footbridge architecture"
75
76#endif
77
78#define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 52#define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000))
79#define XBUS_LED_AMBER (1 << 0) 53#define XBUS_LED_AMBER (1 << 0)
80#define XBUS_LED_GREEN (1 << 1) 54#define XBUS_LED_GREEN (1 << 1)
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index cbd7ae64bcc9..9019a3bf5ab9 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -42,8 +42,6 @@ extern unsigned long __bus_to_virt(unsigned long);
42 42
43#endif 43#endif
44 44
45#if defined(CONFIG_ARCH_FOOTBRIDGE)
46
47/* Task size and page offset at 3GB */ 45/* Task size and page offset at 3GB */
48#define TASK_SIZE UL(0xbf000000) 46#define TASK_SIZE UL(0xbf000000)
49#define PAGE_OFFSET UL(0xc0000000) 47#define PAGE_OFFSET UL(0xc0000000)
@@ -53,23 +51,6 @@ extern unsigned long __bus_to_virt(unsigned long);
53 */ 51 */
54#define FLUSH_BASE 0xf9000000 52#define FLUSH_BASE 0xf9000000
55 53
56#elif defined(CONFIG_ARCH_CO285)
57
58/* Task size and page offset at 1.5GB */
59#define TASK_SIZE UL(0x5f000000)
60#define PAGE_OFFSET UL(0x60000000)
61
62/*
63 * Cache flushing area.
64 */
65#define FLUSH_BASE 0x7e000000
66
67#else
68
69#error "Undefined footbridge architecture"
70
71#endif
72
73/* 54/*
74 * Physical DRAM offset. 55 * Physical DRAM offset.
75 */ 56 */
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
index 02598200997d..e487d7e8c8a6 100644
--- a/include/asm-arm/arch-ebsa285/vmalloc.h
+++ b/include/asm-arm/arch-ebsa285/vmalloc.h
@@ -7,8 +7,4 @@
7 */ 7 */
8 8
9 9
10#ifdef CONFIG_ARCH_FOOTBRIDGE
11#define VMALLOC_END (PAGE_OFFSET + 0x30000000) 10#define VMALLOC_END (PAGE_OFFSET + 0x30000000)
12#else
13#define VMALLOC_END (PAGE_OFFSET + 0x20000000)
14#endif
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h
index adffb6acf42a..6542ca5e8c33 100644
--- a/include/asm-arm/arch-imx/hardware.h
+++ b/include/asm-arm/arch-imx/hardware.h
@@ -73,14 +73,6 @@
73 */ 73 */
74extern void imx_gpio_mode( int gpio_mode ); 74extern void imx_gpio_mode( int gpio_mode );
75 75
76/* get frequencies in Hz */
77extern unsigned int imx_get_system_clk(void);
78extern unsigned int imx_get_mcu_clk(void);
79extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
80extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12] */
81extern unsigned int imx_get_perclk3(void); /* SSI */
82extern unsigned int imx_get_hclk(void); /* SDRAM, CSI, Memory Stick,*/
83 /* I2C, DMA */
84#endif 76#endif
85 77
86#define MAXIRQNUM 62 78#define MAXIRQNUM 62
diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h
index 5b1066da4e1f..44d89c35539a 100644
--- a/include/asm-arm/arch-imx/imx-dma.h
+++ b/include/asm-arm/arch-imx/imx-dma.h
@@ -88,7 +88,7 @@ int imx_dma_request(imx_dmach_t dma_ch, const char *name);
88 88
89void imx_dma_free(imx_dmach_t dma_ch); 89void imx_dma_free(imx_dmach_t dma_ch);
90 90
91int imx_dma_request_by_prio(imx_dmach_t *pdma_ch, const char *name, imx_dma_prio prio); 91imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio);
92 92
93 93
94#endif /* _ASM_ARCH_IMX_DMA_H */ 94#endif /* _ASM_ARCH_IMX_DMA_H */
diff --git a/include/asm-arm/arch-imx/imx-uart.h b/include/asm-arm/arch-imx/imx-uart.h
index 3a685e1780ea..d54eb1d48026 100644
--- a/include/asm-arm/arch-imx/imx-uart.h
+++ b/include/asm-arm/arch-imx/imx-uart.h
@@ -4,6 +4,8 @@
4#define IMXUART_HAVE_RTSCTS (1<<0) 4#define IMXUART_HAVE_RTSCTS (1<<0)
5 5
6struct imxuart_platform_data { 6struct imxuart_platform_data {
7 int (*init)(struct platform_device *pdev);
8 void (*exit)(struct platform_device *pdev);
7 unsigned int flags; 9 unsigned int flags;
8}; 10};
9 11
diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h
index 90d14ee564f5..ef4f5da2029f 100644
--- a/include/asm-arm/arch-iop13xx/adma.h
+++ b/include/asm-arm/arch-iop13xx/adma.h
@@ -198,17 +198,13 @@ iop_chan_memset_slot_count(size_t len, int *slots_per_op)
198static inline int 198static inline int
199iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) 199iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
200{ 200{
201 int num_slots; 201 static const char slot_count_table[] = { 1, 2, 2, 2,
202 /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1 202 2, 3, 3, 3,
203 * (1 source => 8 bytes) (1 slot => 32 bytes) 203 3, 4, 4, 4,
204 */ 204 4, 5, 5, 5,
205 num_slots = 1 + (((src_cnt - 1) << 3) >> 5); 205 };
206 if (((src_cnt - 1) << 3) & 0x1f) 206 *slots_per_op = slot_count_table[src_cnt - 1];
207 num_slots++; 207 return *slots_per_op;
208
209 *slots_per_op = num_slots;
210
211 return num_slots;
212} 208}
213 209
214#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) 210#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
index 2e15da53ff79..d79846fbb394 100644
--- a/include/asm-arm/arch-iop13xx/dma.h
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -1,3 +1,3 @@
1#ifndef _IOP13XX_DMA_H 1#ifndef _IOP13XX_DMA_H
2#define _IOP13XX_DMA_H_ 2#define _IOP13XX_DMA_H
3#endif 3#endif
diff --git a/include/asm-arm/arch-iop32x/gpio.h b/include/asm-arm/arch-iop32x/gpio.h
new file mode 100644
index 000000000000..708f4ec9db1d
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/gpio.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_ARCH_IOP32X_GPIO_H
2#define __ASM_ARCH_IOP32X_GPIO_H
3
4#include <asm/hardware/iop3xx-gpio.h>
5
6#endif
diff --git a/include/asm-arm/arch-iop33x/gpio.h b/include/asm-arm/arch-iop33x/gpio.h
new file mode 100644
index 000000000000..ddd55bba9bb9
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/gpio.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_ARCH_IOP33X_GPIO_H
2#define __ASM_ARCH_IOP33X_GPIO_H
3
4#include <asm/hardware/iop3xx-gpio.h>
5
6#endif
diff --git a/include/asm-arm/arch-ixp4xx/fsg.h b/include/asm-arm/arch-ixp4xx/fsg.h
new file mode 100644
index 000000000000..c0100cc7981c
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/fsg.h
@@ -0,0 +1,50 @@
1/*
2 * include/asm-arm/arch-ixp4xx/fsg.h
3 *
4 * Freecom FSG-3 platform specific definitions
5 *
6 * Author: Rod Whitby <rod@whitby.id.au>
7 * Author: Tomasz Chmielewski <mangoo@wpkg.org>
8 * Maintainers: http://www.nslu2-linux.org
9 *
10 * Based on coyote.h by
11 * Copyright 2004 (c) MontaVista, Software, Inc.
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <asm/hardware.h>"
20#endif
21
22#define FSG_SDA_PIN 12
23#define FSG_SCL_PIN 13
24
25/*
26 * FSG PCI IRQs
27 */
28#define FSG_PCI_MAX_DEV 3
29#define FSG_PCI_IRQ_LINES 3
30
31
32/* PCI controller GPIO to IRQ pin mappings */
33#define FSG_PCI_INTA_PIN 6
34#define FSG_PCI_INTB_PIN 7
35#define FSG_PCI_INTC_PIN 5
36
37/* Buttons */
38
39#define FSG_SB_GPIO 4 /* sync button */
40#define FSG_RB_GPIO 9 /* reset button */
41#define FSG_UB_GPIO 10 /* usb button */
42
43/* LEDs */
44
45#define FSG_LED_WLAN_BIT 0
46#define FSG_LED_WAN_BIT 1
47#define FSG_LED_SATA_BIT 2
48#define FSG_LED_USB_BIT 4
49#define FSG_LED_RING_BIT 5
50#define FSG_LED_SYNC_BIT 7
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 73e8dc36f6a4..fa723a627854 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -45,5 +45,6 @@
45#include "nslu2.h" 45#include "nslu2.h"
46#include "nas100d.h" 46#include "nas100d.h"
47#include "dsmg600.h" 47#include "dsmg600.h"
48#include "fsg.h"
48 49
49#endif /* _ASM_ARCH_HARDWARE_H */ 50#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
index 11801605047b..674af4a84147 100644
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -128,4 +128,11 @@
128#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 128#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
129#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 129#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
130 130
131/*
132 * Freecom FSG-3 Board IRQs
133 */
134#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6
135#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7
136#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5
137
131#endif 138#endif
diff --git a/include/asm-arm/arch-kirkwood/debug-macro.S b/include/asm-arm/arch-kirkwood/debug-macro.S
new file mode 100644
index 000000000000..f55fb8ad9ee4
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-kirkwood/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <asm/arch/kirkwood.h>
10
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @ MMU enabled?
14 ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE
15 ldrne \rx, =KIRKWOOD_REGS_VIRT_BASE
16 orr \rx, \rx, #0x00012000
17 .endm
18
19#define UART_SHIFT 2
20#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-kirkwood/dma.h b/include/asm-arm/arch-kirkwood/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/dma.h
@@ -0,0 +1 @@
/* empty */
diff --git a/include/asm-arm/arch-kirkwood/entry-macro.S b/include/asm-arm/arch-kirkwood/entry-macro.S
new file mode 100644
index 000000000000..fc6a43d9355c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/entry-macro.S
@@ -0,0 +1,40 @@
1/*
2 * include/asm-arm/arch-kirkwood/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell Kirkwood platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/kirkwood.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 @ check low interrupts
25 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
27 mov \irqnr, #31
28 ands \irqstat, \irqstat, \tmp
29 bne 1001f
30
31 @ if no low interrupts set, check high interrupts
32 ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
33 ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
34 mov \irqnr, #63
35 ands \irqstat, \irqstat, \tmp
36
37 @ find first active interrupt source
381001: clzne \irqstat, \irqstat
39 subne \irqnr, \irqnr, \irqstat
40 .endm
diff --git a/include/asm-arm/arch-kirkwood/hardware.h b/include/asm-arm/arch-kirkwood/hardware.h
new file mode 100644
index 000000000000..e695719771a5
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/hardware.h
@@ -0,0 +1,21 @@
1/*
2 * include/asm-arm/arch-kirkwood/hardware.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "kirkwood.h"
13
14#define pcibios_assign_all_busses() 1
15
16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
19
20
21#endif
diff --git a/include/asm-arm/arch-kirkwood/io.h b/include/asm-arm/arch-kirkwood/io.h
new file mode 100644
index 000000000000..0ef6e95f5d5b
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/io.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-kirkwood/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "kirkwood.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
19 + KIRKWOOD_PCIE_IO_VIRT_BASE);
20}
21
22#define __io(a) __io(a)
23#define __mem_pci(a) (a)
24
25
26#endif
diff --git a/include/asm-arm/arch-kirkwood/irqs.h b/include/asm-arm/arch-kirkwood/irqs.h
new file mode 100644
index 000000000000..2e7b5da6335c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/irqs.h
@@ -0,0 +1,63 @@
1/*
2 * include/asm-arm/arch-kirkwood/irqs.h
3 *
4 * IRQ definitions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14#include "kirkwood.h" /* need GPIO_MAX */
15
16/*
17 * Low Interrupt Controller
18 */
19#define IRQ_KIRKWOOD_HIGH_SUM 0
20#define IRQ_KIRKWOOD_BRIDGE 1
21#define IRQ_KIRKWOOD_HOST2CPU 2
22#define IRQ_KIRKWOOD_CPU2HOST 3
23#define IRQ_KIRKWOOD_XOR_00 5
24#define IRQ_KIRKWOOD_XOR_01 6
25#define IRQ_KIRKWOOD_XOR_10 7
26#define IRQ_KIRKWOOD_XOR_11 8
27#define IRQ_KIRKWOOD_PCIE 9
28#define IRQ_KIRKWOOD_GE00_SUM 11
29#define IRQ_KIRKWOOD_GE01_SUM 15
30#define IRQ_KIRKWOOD_USB 19
31#define IRQ_KIRKWOOD_SATA 21
32#define IRQ_KIRKWOOD_CRYPTO 22
33#define IRQ_KIRKWOOD_SPI 23
34#define IRQ_KIRKWOOD_I2S 24
35#define IRQ_KIRKWOOD_TS_0 26
36#define IRQ_KIRKWOOD_SDIO 28
37#define IRQ_KIRKWOOD_TWSI 29
38#define IRQ_KIRKWOOD_AVB 30
39#define IRQ_KIRKWOOD_TDMI 31
40
41/*
42 * High Interrupt Controller
43 */
44#define IRQ_KIRKWOOD_UART_0 33
45#define IRQ_KIRKWOOD_UART_1 34
46#define IRQ_KIRKWOOD_GPIO_LOW_0_7 35
47#define IRQ_KIRKWOOD_GPIO_LOW_8_15 36
48#define IRQ_KIRKWOOD_GPIO_LOW_16_23 37
49#define IRQ_KIRKWOOD_GPIO_LOW_24_31 38
50#define IRQ_KIRKWOOD_GPIO_HIGH_0_7 39
51#define IRQ_KIRKWOOD_GPIO_HIGH_8_15 40
52#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
53
54/*
55 * KIRKWOOD General Purpose Pins
56 */
57#define IRQ_KIRKWOOD_GPIO_START 64
58#define NR_GPIO_IRQS GPIO_MAX
59
60#define NR_IRQS (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
61
62
63#endif
diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h
new file mode 100644
index 000000000000..bb31b315c350
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/kirkwood.h
@@ -0,0 +1,100 @@
1/*
2 * include/asm-arm/arch-kirkwood/kirkwood.h
3 *
4 * Generic definitions for Marvell Kirkwood SoC flavors:
5 * 88F6180, 88F6192 and 88F6281.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __ASM_ARCH_KIRKWOOD_H
13#define __ASM_ARCH_KIRKWOOD_H
14
15/*
16 * Marvell Kirkwood address maps.
17 *
18 * phys
19 * e0000000 PCIe Memory space
20 * f1000000 on-chip peripheral registers
21 * f2000000 PCIe I/O space
22 * f3000000 NAND controller address window
23 *
24 * virt phys size
25 * fee00000 f1000000 1M on-chip peripheral registers
26 * fef00000 f2000000 1M PCIe I/O space
27 */
28
29#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000
30#define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K
31 * is the minimal window size
32 */
33
34#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
35#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000
36#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
37#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
38
39#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
40#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000
41#define KIRKWOOD_REGS_SIZE SZ_1M
42
43#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
44#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
45
46/*
47 * MBUS bridge registers.
48 */
49#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
50#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
51#define CPU_RESET 0x00000002
52#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
53#define SOFT_RESET_OUT_EN 0x00000004
54#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
55#define SOFT_RESET 0x00000001
56#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
57#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
58#define BRIDGE_INT_TIMER0 0x0002
59#define BRIDGE_INT_TIMER1 0x0004
60#define BRIDGE_INT_TIMER1_CLR (~0x0004)
61#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
62#define IRQ_CAUSE_LOW_OFF 0x0000
63#define IRQ_MASK_LOW_OFF 0x0004
64#define IRQ_CAUSE_HIGH_OFF 0x0010
65#define IRQ_MASK_HIGH_OFF 0x0014
66#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
67#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
68#define L2_WRITETHROUGH 0x00000010
69
70/*
71 * Register Map
72 */
73#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
74#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500)
75
76#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
77#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
78#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
79#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
80#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
81#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
82#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
83#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
84#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
85#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
86
87#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
88
89#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
90
91#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
92#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
93
94#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
95
96
97#define GPIO_MAX 50
98
99
100#endif
diff --git a/include/asm-arm/arch-kirkwood/memory.h b/include/asm-arm/arch-kirkwood/memory.h
new file mode 100644
index 000000000000..e5108f408ce6
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/memory.h
@@ -0,0 +1,14 @@
1/*
2 * include/asm-arm/arch-kirkwood/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PHYS_OFFSET UL(0x00000000)
9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif
diff --git a/include/asm-arm/arch-kirkwood/system.h b/include/asm-arm/arch-kirkwood/system.h
new file mode 100644
index 000000000000..8dde7e379855
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/system.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-kirkwood/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <asm/arch/hardware.h>
13#include <asm/arch/kirkwood.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode)
21{
22 /*
23 * Enable soft reset to assert RSTOUTn.
24 */
25 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
26
27 /*
28 * Assert soft reset.
29 */
30 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
31
32 while (1)
33 ;
34}
35
36
37#endif
diff --git a/include/asm-arm/arch-kirkwood/timex.h b/include/asm-arm/arch-kirkwood/timex.h
new file mode 100644
index 000000000000..82122e134e3c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/timex.h
@@ -0,0 +1,11 @@
1/*
2 * include/asm-arm/arch-kirkwood/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
10
11#define KIRKWOOD_TCLK 166666667
diff --git a/include/asm-arm/arch-kirkwood/uncompress.h b/include/asm-arm/arch-kirkwood/uncompress.h
new file mode 100644
index 000000000000..a9062b6d7680
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/uncompress.h
@@ -0,0 +1,47 @@
1/*
2 * include/asm-arm/arch-kirkwood/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/serial_reg.h>
10#include <asm/arch/kirkwood.h>
11
12#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
13
14static void putc(const char c)
15{
16 unsigned char *base = SERIAL_BASE;
17 int i;
18
19 for (i = 0; i < 0x1000; i++) {
20 if (base[UART_LSR << 2] & UART_LSR_THRE)
21 break;
22 barrier();
23 }
24
25 base[UART_TX << 2] = c;
26}
27
28static void flush(void)
29{
30 unsigned char *base = SERIAL_BASE;
31 unsigned char mask;
32 int i;
33
34 mask = UART_LSR_TEMT | UART_LSR_THRE;
35
36 for (i = 0; i < 0x1000; i++) {
37 if ((base[UART_LSR << 2] & mask) == mask)
38 break;
39 barrier();
40 }
41}
42
43/*
44 * nothing to do
45 */
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-kirkwood/vmalloc.h b/include/asm-arm/arch-kirkwood/vmalloc.h
new file mode 100644
index 000000000000..41852c6e77f3
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-kirkwood/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe800000
diff --git a/include/asm-arm/arch-loki/debug-macro.S b/include/asm-arm/arch-loki/debug-macro.S
new file mode 100644
index 000000000000..585502e96513
--- /dev/null
+++ b/include/asm-arm/arch-loki/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-loki/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <asm/arch/loki.h>
10
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @ MMU enabled?
14 ldreq \rx, =LOKI_REGS_PHYS_BASE
15 ldrne \rx, =LOKI_REGS_VIRT_BASE
16 orr \rx, \rx, #0x00012000
17 .endm
18
19#define UART_SHIFT 2
20#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-loki/dma.h b/include/asm-arm/arch-loki/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-loki/dma.h
@@ -0,0 +1 @@
/* empty */
diff --git a/include/asm-arm/arch-loki/entry-macro.S b/include/asm-arm/arch-loki/entry-macro.S
new file mode 100644
index 000000000000..693257cdbeb8
--- /dev/null
+++ b/include/asm-arm/arch-loki/entry-macro.S
@@ -0,0 +1,30 @@
1/*
2 * include/asm-arm/arch-loki/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/loki.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 ldr \irqstat, [\base, #IRQ_CAUSE_OFF]
25 ldr \tmp, [\base, #IRQ_MASK_OFF]
26 mov \irqnr, #0
27 ands \irqstat, \irqstat, \tmp
28 clzne \irqnr, \irqstat
29 rsbne \irqnr, \irqnr, #31
30 .endm
diff --git a/include/asm-arm/arch-loki/hardware.h b/include/asm-arm/arch-loki/hardware.h
new file mode 100644
index 000000000000..f65b01c733b6
--- /dev/null
+++ b/include/asm-arm/arch-loki/hardware.h
@@ -0,0 +1,15 @@
1/*
2 * include/asm-arm/arch-loki/hardware.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "loki.h"
13
14
15#endif
diff --git a/include/asm-arm/arch-loki/io.h b/include/asm-arm/arch-loki/io.h
new file mode 100644
index 000000000000..e7418a915e75
--- /dev/null
+++ b/include/asm-arm/arch-loki/io.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-loki/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "loki.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
19 + LOKI_PCIE0_IO_VIRT_BASE);
20}
21
22#define __io(a) __io(a)
23#define __mem_pci(a) (a)
24
25
26#endif
diff --git a/include/asm-arm/arch-loki/irqs.h b/include/asm-arm/arch-loki/irqs.h
new file mode 100644
index 000000000000..7e4971438072
--- /dev/null
+++ b/include/asm-arm/arch-loki/irqs.h
@@ -0,0 +1,58 @@
1/*
2 * include/asm-arm/arch-loki/irqs.h
3 *
4 * IRQ definitions for Marvell Loki (88RC8480) SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14#include "loki.h" /* need GPIO_MAX */
15
16/*
17 * Interrupt Controller
18 */
19#define IRQ_LOKI_PCIE_A_CPU_DRBL 0
20#define IRQ_LOKI_CPU_PCIE_A_DRBL 1
21#define IRQ_LOKI_PCIE_B_CPU_DRBL 2
22#define IRQ_LOKI_CPU_PCIE_B_DRBL 3
23#define IRQ_LOKI_COM_A_ERR 6
24#define IRQ_LOKI_COM_A_IN 7
25#define IRQ_LOKI_COM_A_OUT 8
26#define IRQ_LOKI_COM_B_ERR 9
27#define IRQ_LOKI_COM_B_IN 10
28#define IRQ_LOKI_COM_B_OUT 11
29#define IRQ_LOKI_DMA_A 12
30#define IRQ_LOKI_DMA_B 13
31#define IRQ_LOKI_SAS_A 14
32#define IRQ_LOKI_SAS_B 15
33#define IRQ_LOKI_DDR 16
34#define IRQ_LOKI_XOR 17
35#define IRQ_LOKI_BRIDGE 18
36#define IRQ_LOKI_PCIE_A_ERR 20
37#define IRQ_LOKI_PCIE_A_INT 21
38#define IRQ_LOKI_PCIE_B_ERR 22
39#define IRQ_LOKI_PCIE_B_INT 23
40#define IRQ_LOKI_GBE_A_INT 24
41#define IRQ_LOKI_GBE_B_INT 25
42#define IRQ_LOKI_DEV_ERR 26
43#define IRQ_LOKI_UART0 27
44#define IRQ_LOKI_UART1 28
45#define IRQ_LOKI_TWSI 29
46#define IRQ_LOKI_GPIO_23_0 30
47#define IRQ_LOKI_GPIO_25_24 31
48
49/*
50 * Loki General Purpose Pins
51 */
52#define IRQ_LOKI_GPIO_START 32
53#define NR_GPIO_IRQS GPIO_MAX
54
55#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
56
57
58#endif
diff --git a/include/asm-arm/arch-loki/loki.h b/include/asm-arm/arch-loki/loki.h
new file mode 100644
index 000000000000..5dd05ee0a4e6
--- /dev/null
+++ b/include/asm-arm/arch-loki/loki.h
@@ -0,0 +1,97 @@
1/*
2 * include/asm-arm/arch-loki/loki.h
3 *
4 * Generic definitions for Marvell Loki (88RC8480) SoC flavors
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_LOKI_H
12#define __ASM_ARCH_LOKI_H
13
14/*
15 * Marvell Loki (88RC8480) address maps.
16 *
17 * phys
18 * d0000000 on-chip peripheral registers
19 * e0000000 PCIe 0 Memory space
20 * e8000000 PCIe 1 Memory space
21 * f0000000 PCIe 0 I/O space
22 * f0100000 PCIe 1 I/O space
23 *
24 * virt phys size
25 * fed00000 d0000000 1M on-chip peripheral registers
26 * fee00000 f0000000 64K PCIe 0 I/O space
27 * fef00000 f0100000 64K PCIe 1 I/O space
28 */
29
30#define LOKI_REGS_PHYS_BASE 0xd0000000
31#define LOKI_REGS_VIRT_BASE 0xfed00000
32#define LOKI_REGS_SIZE SZ_1M
33
34#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
35#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
36#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
37#define LOKI_PCIE0_IO_SIZE SZ_64K
38
39#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
40#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
41#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
42#define LOKI_PCIE1_IO_SIZE SZ_64K
43
44#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
45#define LOKI_PCIE0_MEM_SIZE SZ_128M
46
47#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
48#define LOKI_PCIE1_MEM_SIZE SZ_128M
49
50/*
51 * Register Map
52 */
53#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
54#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
55#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
56#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
57#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
58#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
59
60#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
61#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
62#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
63#define SOFT_RESET_OUT_EN 0x00000004
64#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
65#define SOFT_RESET 0x00000001
66#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
67#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
68#define BRIDGE_INT_TIMER0 0x0002
69#define BRIDGE_INT_TIMER1 0x0004
70#define BRIDGE_INT_TIMER1_CLR 0x0004
71#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
72#define IRQ_CAUSE_OFF 0x0000
73#define IRQ_MASK_OFF 0x0004
74#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
75
76#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
77
78#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
79
80#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
81
82#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
83
84#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
85#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
86
87#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
88#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
89
90#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
91#define DDR_REG(x) (DDR_VIRT_BASE | (x))
92
93
94#define GPIO_MAX 8
95
96
97#endif
diff --git a/include/asm-arm/arch-loki/memory.h b/include/asm-arm/arch-loki/memory.h
new file mode 100644
index 000000000000..835101e49875
--- /dev/null
+++ b/include/asm-arm/arch-loki/memory.h
@@ -0,0 +1,14 @@
1/*
2 * include/asm-arm/arch-loki/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PHYS_OFFSET UL(0x00000000)
9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif
diff --git a/include/asm-arm/arch-loki/system.h b/include/asm-arm/arch-loki/system.h
new file mode 100644
index 000000000000..a3568ac8ec35
--- /dev/null
+++ b/include/asm-arm/arch-loki/system.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-loki/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <asm/arch/hardware.h>
13#include <asm/arch/loki.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode)
21{
22 /*
23 * Enable soft reset to assert RSTOUTn.
24 */
25 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
26
27 /*
28 * Assert soft reset.
29 */
30 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
31
32 while (1)
33 ;
34}
35
36
37#endif
diff --git a/include/asm-arm/arch-loki/timex.h b/include/asm-arm/arch-loki/timex.h
new file mode 100644
index 000000000000..940014f97cae
--- /dev/null
+++ b/include/asm-arm/arch-loki/timex.h
@@ -0,0 +1,11 @@
1/*
2 * include/asm-arm/arch-loki/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
10
11#define LOKI_TCLK 180000000
diff --git a/include/asm-arm/arch-loki/uncompress.h b/include/asm-arm/arch-loki/uncompress.h
new file mode 100644
index 000000000000..89a0cf88d3a5
--- /dev/null
+++ b/include/asm-arm/arch-loki/uncompress.h
@@ -0,0 +1,47 @@
1/*
2 * include/asm-arm/arch-loki/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/serial_reg.h>
10#include <asm/arch/loki.h>
11
12#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
13
14static void putc(const char c)
15{
16 unsigned char *base = SERIAL_BASE;
17 int i;
18
19 for (i = 0; i < 0x1000; i++) {
20 if (base[UART_LSR << 2] & UART_LSR_THRE)
21 break;
22 barrier();
23 }
24
25 base[UART_TX << 2] = c;
26}
27
28static void flush(void)
29{
30 unsigned char *base = SERIAL_BASE;
31 unsigned char mask;
32 int i;
33
34 mask = UART_LSR_TEMT | UART_LSR_THRE;
35
36 for (i = 0; i < 0x1000; i++) {
37 if ((base[UART_LSR << 2] & mask) == mask)
38 break;
39 barrier();
40 }
41}
42
43/*
44 * nothing to do
45 */
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-loki/vmalloc.h b/include/asm-arm/arch-loki/vmalloc.h
new file mode 100644
index 000000000000..f5be06220491
--- /dev/null
+++ b/include/asm-arm/arch-loki/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-loki/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe800000
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
index 565430cfaa7e..e62a108b1857 100644
--- a/include/asm-arm/arch-msm/irqs.h
+++ b/include/asm-arm/arch-msm/irqs.h
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#ifndef __ASM_ARCH_MSM_IRQS_H 17#ifndef __ASM_ARCH_MSM_IRQS_H
18#define __ASM_ARCH_MSM_IRQS_H
18 19
19/* MSM ARM11 Interrupt Numbers */ 20/* MSM ARM11 Interrupt Numbers */
20/* See 80-VE113-1 A, pp219-221 */ 21/* See 80-VE113-1 A, pp219-221 */
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h
index 154b23fb3599..8724487ab4c9 100644
--- a/include/asm-arm/arch-msm/timex.h
+++ b/include/asm-arm/arch-msm/timex.h
@@ -14,6 +14,7 @@
14 */ 14 */
15 15
16#ifndef __ASM_ARCH_MSM_TIMEX_H 16#ifndef __ASM_ARCH_MSM_TIMEX_H
17#define __ASM_ARCH_MSM_TIMEX_H
17 18
18#define CLOCK_TICK_RATE 1000000 19#define CLOCK_TICK_RATE 1000000
19 20
diff --git a/include/asm-arm/arch-mv78xx0/debug-macro.S b/include/asm-arm/arch-mv78xx0/debug-macro.S
new file mode 100644
index 000000000000..d0595bd645e5
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-mv78xx0/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <asm/arch/mv78xx0.h>
10
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @ MMU enabled?
14 ldreq \rx, =MV78XX0_REGS_PHYS_BASE
15 ldrne \rx, =MV78XX0_REGS_VIRT_BASE
16 orr \rx, \rx, #0x00012000
17 .endm
18
19#define UART_SHIFT 2
20#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-mv78xx0/dma.h b/include/asm-arm/arch-mv78xx0/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/dma.h
@@ -0,0 +1 @@
/* empty */
diff --git a/include/asm-arm/arch-mv78xx0/entry-macro.S b/include/asm-arm/arch-mv78xx0/entry-macro.S
new file mode 100644
index 000000000000..e9a606b12669
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * include/asm-arm/arch-mv78xx0/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell MV78xx0 platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/mv78xx0.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 @ check low interrupts
25 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
27 mov \irqnr, #31
28 ands \irqstat, \irqstat, \tmp
29
30 @ if no low interrupts set, check high interrupts
31 ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
32 ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF]
33 moveq \irqnr, #63
34 andeqs \irqstat, \irqstat, \tmp
35
36 @ find first active interrupt source
37 clzne \irqstat, \irqstat
38 subne \irqnr, \irqnr, \irqstat
39 .endm
diff --git a/include/asm-arm/arch-mv78xx0/hardware.h b/include/asm-arm/arch-mv78xx0/hardware.h
new file mode 100644
index 000000000000..8e17926086c6
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/hardware.h
@@ -0,0 +1,21 @@
1/*
2 * include/asm-arm/arch-mv78xx0/hardware.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "mv78xx0.h"
13
14#define pcibios_assign_all_busses() 1
15
16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
19
20
21#endif
diff --git a/include/asm-arm/arch-mv78xx0/io.h b/include/asm-arm/arch-mv78xx0/io.h
new file mode 100644
index 000000000000..415d4c98e3d1
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/io.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-mv78xx0/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "mv78xx0.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
19 + MV78XX0_PCIE_IO_VIRT_BASE(0));
20}
21
22#define __io(a) __io(a)
23#define __mem_pci(a) (a)
24
25
26#endif
diff --git a/include/asm-arm/arch-mv78xx0/irqs.h b/include/asm-arm/arch-mv78xx0/irqs.h
new file mode 100644
index 000000000000..75930450cd65
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/irqs.h
@@ -0,0 +1,91 @@
1/*
2 * include/asm-arm/arch-mv78xx0/irqs.h
3 *
4 * IRQ definitions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14#include "mv78xx0.h" /* need GPIO_MAX */
15
16/*
17 * MV78xx0 Low Interrupt Controller
18 */
19#define IRQ_MV78XX0_ERR 0
20#define IRQ_MV78XX0_SPI 1
21#define IRQ_MV78XX0_I2C_0 2
22#define IRQ_MV78XX0_I2C_1 3
23#define IRQ_MV78XX0_IDMA_0 4
24#define IRQ_MV78XX0_IDMA_1 5
25#define IRQ_MV78XX0_IDMA_2 6
26#define IRQ_MV78XX0_IDMA_3 7
27#define IRQ_MV78XX0_TIMER_0 8
28#define IRQ_MV78XX0_TIMER_1 9
29#define IRQ_MV78XX0_TIMER_2 10
30#define IRQ_MV78XX0_TIMER_3 11
31#define IRQ_MV78XX0_UART_0 12
32#define IRQ_MV78XX0_UART_1 13
33#define IRQ_MV78XX0_UART_2 14
34#define IRQ_MV78XX0_UART_3 15
35#define IRQ_MV78XX0_USB_0 16
36#define IRQ_MV78XX0_USB_1 17
37#define IRQ_MV78XX0_USB_2 18
38#define IRQ_MV78XX0_CRYPTO 19
39#define IRQ_MV78XX0_SDIO_0 20
40#define IRQ_MV78XX0_SDIO_1 21
41#define IRQ_MV78XX0_XOR_0 22
42#define IRQ_MV78XX0_XOR_1 23
43#define IRQ_MV78XX0_I2S_0 24
44#define IRQ_MV78XX0_I2S_1 25
45#define IRQ_MV78XX0_SATA 26
46#define IRQ_MV78XX0_TDMI 27
47
48/*
49 * MV78xx0 High Interrupt Controller
50 */
51#define IRQ_MV78XX0_PCIE_00 32
52#define IRQ_MV78XX0_PCIE_01 33
53#define IRQ_MV78XX0_PCIE_02 34
54#define IRQ_MV78XX0_PCIE_03 35
55#define IRQ_MV78XX0_PCIE_10 36
56#define IRQ_MV78XX0_PCIE_11 37
57#define IRQ_MV78XX0_PCIE_12 38
58#define IRQ_MV78XX0_PCIE_13 39
59#define IRQ_MV78XX0_GE00_SUM 40
60#define IRQ_MV78XX0_GE00_RX 41
61#define IRQ_MV78XX0_GE00_TX 42
62#define IRQ_MV78XX0_GE00_MISC 43
63#define IRQ_MV78XX0_GE01_SUM 44
64#define IRQ_MV78XX0_GE01_RX 45
65#define IRQ_MV78XX0_GE01_TX 46
66#define IRQ_MV78XX0_GE01_MISC 47
67#define IRQ_MV78XX0_GE10_SUM 48
68#define IRQ_MV78XX0_GE10_RX 49
69#define IRQ_MV78XX0_GE10_TX 50
70#define IRQ_MV78XX0_GE10_MISC 51
71#define IRQ_MV78XX0_GE11_SUM 52
72#define IRQ_MV78XX0_GE11_RX 53
73#define IRQ_MV78XX0_GE11_TX 54
74#define IRQ_MV78XX0_GE11_MISC 55
75#define IRQ_MV78XX0_GPIO_0_7 56
76#define IRQ_MV78XX0_GPIO_8_15 57
77#define IRQ_MV78XX0_GPIO_16_23 58
78#define IRQ_MV78XX0_GPIO_24_31 59
79#define IRQ_MV78XX0_DB_IN 60
80#define IRQ_MV78XX0_DB_OUT 61
81
82/*
83 * MV78XX0 General Purpose Pins
84 */
85#define IRQ_MV78XX0_GPIO_START 64
86#define NR_GPIO_IRQS GPIO_MAX
87
88#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
89
90
91#endif
diff --git a/include/asm-arm/arch-mv78xx0/memory.h b/include/asm-arm/arch-mv78xx0/memory.h
new file mode 100644
index 000000000000..721a6b185b91
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/memory.h
@@ -0,0 +1,14 @@
1/*
2 * include/asm-arm/arch-mv78xx0/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PHYS_OFFSET UL(0x00000000)
9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif
diff --git a/include/asm-arm/arch-mv78xx0/mv78xx0.h b/include/asm-arm/arch-mv78xx0/mv78xx0.h
new file mode 100644
index 000000000000..9f5d83c73faa
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/mv78xx0.h
@@ -0,0 +1,126 @@
1/*
2 * include/asm-arm/arch-mv78xx0/mv78xx0.h
3 *
4 * Generic definitions for Marvell MV78xx0 SoC flavors:
5 * MV781x0 and MV782x0.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __ASM_ARCH_MV78XX0_H
13#define __ASM_ARCH_MV78XX0_H
14
15/*
16 * Marvell MV78xx0 address maps.
17 *
18 * phys
19 * c0000000 PCIe Memory space
20 * f0800000 PCIe #0 I/O space
21 * f0900000 PCIe #1 I/O space
22 * f0a00000 PCIe #2 I/O space
23 * f0b00000 PCIe #3 I/O space
24 * f0c00000 PCIe #4 I/O space
25 * f0d00000 PCIe #5 I/O space
26 * f0e00000 PCIe #6 I/O space
27 * f0f00000 PCIe #7 I/O space
28 * f1000000 on-chip peripheral registers
29 *
30 * virt phys size
31 * fe400000 f102x000 16K core-specific peripheral registers
32 * fe700000 f0800000 1M PCIe #0 I/O space
33 * fe800000 f0900000 1M PCIe #1 I/O space
34 * fe900000 f0a00000 1M PCIe #2 I/O space
35 * fea00000 f0b00000 1M PCIe #3 I/O space
36 * feb00000 f0c00000 1M PCIe #4 I/O space
37 * fec00000 f0d00000 1M PCIe #5 I/O space
38 * fed00000 f0e00000 1M PCIe #6 I/O space
39 * fee00000 f0f00000 1M PCIe #7 I/O space
40 * fef00000 f1000000 1M on-chip peripheral registers
41 */
42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
45#define MV78XX0_CORE_REGS_SIZE SZ_16K
46
47#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
49#define MV78XX0_PCIE_IO_SIZE SZ_1M
50
51#define MV78XX0_REGS_PHYS_BASE 0xf1000000
52#define MV78XX0_REGS_VIRT_BASE 0xfef00000
53#define MV78XX0_REGS_SIZE SZ_1M
54
55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
56#define MV78XX0_PCIE_MEM_SIZE 0x30000000
57
58/*
59 * Core-specific peripheral registers.
60 */
61#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
62#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
63#define L2_WRITETHROUGH 0x00020000
64#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
65#define SOFT_RESET_OUT_EN 0x00000004
66#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
67#define SOFT_RESET 0x00000001
68#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
69#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
70#define BRIDGE_INT_TIMER0 0x0002
71#define BRIDGE_INT_TIMER1 0x0004
72#define BRIDGE_INT_TIMER1_CLR (~0x0004)
73#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
74#define IRQ_CAUSE_LOW_OFF 0x0004
75#define IRQ_CAUSE_HIGH_OFF 0x0008
76#define IRQ_MASK_LOW_OFF 0x0010
77#define IRQ_MASK_HIGH_OFF 0x0014
78#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
79
80/*
81 * Register Map
82 */
83#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
84#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
85#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700)
86
87#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
88#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
89#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
90#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
91#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
92#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
93#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
94#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
95#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200)
96#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200)
97#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300)
98#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300)
99
100#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000)
101#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000)
102
103#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000)
104#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000)
105#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000)
106#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000)
107
108#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000)
109#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000)
110#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000)
111
112#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000)
113#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000)
114
115#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000)
116#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000)
117#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000)
118#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000)
119
120#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
121
122
123#define GPIO_MAX 32
124
125
126#endif
diff --git a/include/asm-arm/arch-mv78xx0/system.h b/include/asm-arm/arch-mv78xx0/system.h
new file mode 100644
index 000000000000..7eb47d376db9
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/system.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-mv78xx0/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <asm/arch/hardware.h>
13#include <asm/arch/mv78xx0.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode)
21{
22 /*
23 * Enable soft reset to assert RSTOUTn.
24 */
25 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
26
27 /*
28 * Assert soft reset.
29 */
30 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
31
32 while (1)
33 ;
34}
35
36
37#endif
diff --git a/include/asm-arm/arch-mv78xx0/timex.h b/include/asm-arm/arch-mv78xx0/timex.h
new file mode 100644
index 000000000000..a854b1ccbd01
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/timex.h
@@ -0,0 +1,9 @@
1/*
2 * include/asm-arm/arch-mv78xx0/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-mv78xx0/uncompress.h b/include/asm-arm/arch-mv78xx0/uncompress.h
new file mode 100644
index 000000000000..3bfe0a293ef7
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/uncompress.h
@@ -0,0 +1,47 @@
1/*
2 * include/asm-arm/arch-mv78xx0/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/serial_reg.h>
10#include <asm/arch/mv78xx0.h>
11
12#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
13
14static void putc(const char c)
15{
16 unsigned char *base = SERIAL_BASE;
17 int i;
18
19 for (i = 0; i < 0x1000; i++) {
20 if (base[UART_LSR << 2] & UART_LSR_THRE)
21 break;
22 barrier();
23 }
24
25 base[UART_TX << 2] = c;
26}
27
28static void flush(void)
29{
30 unsigned char *base = SERIAL_BASE;
31 unsigned char mask;
32 int i;
33
34 mask = UART_LSR_TEMT | UART_LSR_THRE;
35
36 for (i = 0; i < 0x1000; i++) {
37 if ((base[UART_LSR << 2] & mask) == mask)
38 break;
39 barrier();
40 }
41}
42
43/*
44 * nothing to do
45 */
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-mv78xx0/vmalloc.h b/include/asm-arm/arch-mv78xx0/vmalloc.h
new file mode 100644
index 000000000000..f2c512197579
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-mv78xx0/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe000000
diff --git a/include/asm-arm/arch-mxc/board-mx27ads.h b/include/asm-arm/arch-mxc/board-mx27ads.h
new file mode 100644
index 000000000000..61e66dac90ef
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx27ads.h
@@ -0,0 +1,354 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
16
17/* external interrupt multiplexer */
18#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
19
20#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
21#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
22#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
23#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
24
25#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
26 MXC_MAX_VIRTUAL_INTS)
27
28/*
29 * MXC UART EVB board level configurations
30 */
31
32#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000)
33#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000)
34#define MXC_LL_EXTUART_16BIT_BUS
35
36#define MXC_LL_UART_PADDR UART1_BASE_ADDR
37#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
38
39/*
40 * @name Memory Size parameters
41 */
42
43/*
44 * Size of SDRAM memory
45 */
46#define SDRAM_MEM_SIZE SZ_128M
47
48/*
49 * PBC Controller parameters
50 */
51
52/*
53 * Base address of PBC controller, CS4
54 */
55#define PBC_BASE_ADDRESS 0xEB000000
56#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset))
57
58/*
59 * PBC Interupt name definitions
60 */
61#define PBC_GPIO1_0 0
62#define PBC_GPIO1_1 1
63#define PBC_GPIO1_2 2
64#define PBC_GPIO1_3 3
65#define PBC_GPIO1_4 4
66#define PBC_GPIO1_5 5
67
68#define PBC_INTR_MAX_NUM 6
69#define PBC_INTR_SHARED_MAX_NUM 8
70
71/* When the PBC address connection is fixed in h/w, defined as 1 */
72#define PBC_ADDR_SH 0
73
74/* Offsets for the PBC Controller register */
75/*
76 * PBC Board version register offset
77 */
78#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
79/*
80 * PBC Board control register 1 set address.
81 */
82#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
83/*
84 * PBC Board control register 1 clear address.
85 */
86#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
87/*
88 * PBC Board control register 2 set address.
89 */
90#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
91/*
92 * PBC Board control register 2 clear address.
93 */
94#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
95/*
96 * PBC Board control register 3 set address.
97 */
98#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
99/*
100 * PBC Board control register 3 clear address.
101 */
102#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
103/*
104 * PBC Board control register 3 set address.
105 */
106#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
107/*
108 * PBC Board control register 4 clear address.
109 */
110#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
111/*PBC_ADDR_SH
112 * PBC Board status register 1.
113 */
114#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
115/*
116 * PBC Board interrupt status register.
117 */
118#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
119/*
120 * PBC Board interrupt current status register.
121 */
122#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
123/*
124 * PBC Interrupt mask register set address.
125 */
126#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
127/*
128 * PBC Interrupt mask register clear address.
129 */
130#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
131/*
132 * External UART A.
133 */
134#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
135/*
136 * UART 4 Expanding Signal Status.
137 */
138#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
139/*
140 * UART 4 Expanding Signal Control Set.
141 */
142#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
143/*
144 * UART 4 Expanding Signal Control Clear.
145 */
146#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
147/*
148 * Ethernet Controller IO base address.
149 */
150#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
151/*
152 * Ethernet Controller Memory base address.
153 */
154#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
155/*
156 * Ethernet Controller DMA base address.
157 */
158#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
159
160/* PBC Board Version Register bit definition */
161#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
162#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
163
164/* PBC Board Control Register 1 bit definitions */
165#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
166#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
167#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
168#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
169#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
170
171/* PBC Board Control Register 2 bit definitions */
172#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
173#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
174#define PBC_BCTRL2_ATAFEC_EN 0X0010
175#define PBC_BCTRL2_ATAFEC_SEL 0X0020
176#define PBC_BCTRL2_ATA_EN 0X0040
177#define PBC_BCTRL2_IRDA_SD 0X0080
178#define PBC_BCTRL2_IRDA_EN 0X0100
179#define PBC_BCTRL2_CCTL10 0X0200
180#define PBC_BCTRL2_CCTL11 0X0400
181
182/* PBC Board Control Register 3 bit definitions */
183#define PBC_BCTRL3_HSH_EN 0X0020
184#define PBC_BCTRL3_FSH_MOD 0X0040
185#define PBC_BCTRL3_OTG_HS_EN 0X0080
186#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
187#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
188#define PBC_BCTRL3_USB_OTG_ON 0X0800
189#define PBC_BCTRL3_USB_FSH_ON 0X1000
190
191/* PBC Board Control Register 4 bit definitions */
192#define PBC_BCTRL4_REGEN_SEL 0X0001
193#define PBC_BCTRL4_USER_OFF 0X0002
194#define PBC_BCTRL4_VIB_EN 0X0004
195#define PBC_BCTRL4_PWRGT1_EN 0X0008
196#define PBC_BCTRL4_PWRGT2_EN 0X0010
197#define PBC_BCTRL4_STDBY_PRI 0X0020
198
199#ifndef __ASSEMBLY__
200/*
201 * Enumerations for SD cards and memory stick card. This corresponds to
202 * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
203 */
204enum mxc_card_no {
205 MXC_CARD_SD2 = 0,
206 MXC_CARD_SD3,
207 MXC_CARD_MS,
208 MXC_CARD_SD1,
209 MXC_CARD_MIN = MXC_CARD_SD2,
210 MXC_CARD_MAX = MXC_CARD_SD1,
211};
212#endif
213
214#define MXC_CPLD_VER_1_50 0x01
215
216/*
217 * PBC BSTAT Register bit definitions
218 */
219#define PBC_BSTAT_PRI_INT 0X0001
220#define PBC_BSTAT_USB_BYP 0X0002
221#define PBC_BSTAT_ATA_IOCS16 0X0004
222#define PBC_BSTAT_ATA_CBLID 0X0008
223#define PBC_BSTAT_ATA_DASP 0X0010
224#define PBC_BSTAT_PWR_RDY 0X0020
225#define PBC_BSTAT_SD3_WP 0X0100
226#define PBC_BSTAT_SD2_WP 0X0200
227#define PBC_BSTAT_SD1_WP 0X0400
228#define PBC_BSTAT_SD3_DET 0X0800
229#define PBC_BSTAT_SD2_DET 0X1000
230#define PBC_BSTAT_SD1_DET 0X2000
231#define PBC_BSTAT_MS_DET 0X4000
232#define PBC_BSTAT_SD3_DET_BIT 11
233#define PBC_BSTAT_SD2_DET_BIT 12
234#define PBC_BSTAT_SD1_DET_BIT 13
235#define PBC_BSTAT_MS_DET_BIT 14
236#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
237 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
238 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
239 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
240 0x0))))
241
242/*
243 * PBC UART Control Register bit definitions
244 */
245#define PBC_UCTRL_DCE_DCD 0X0001
246#define PBC_UCTRL_DCE_DSR 0X0002
247#define PBC_UCTRL_DCE_RI 0X0004
248#define PBC_UCTRL_DTE_DTR 0X0100
249
250/*
251 * PBC UART Status Register bit definitions
252 */
253#define PBC_USTAT_DTE_DCD 0X0001
254#define PBC_USTAT_DTE_DSR 0X0002
255#define PBC_USTAT_DTE_RI 0X0004
256#define PBC_USTAT_DCE_DTR 0X0100
257
258/*
259 * PBC Interupt mask register bit definitions
260 */
261#define PBC_INTR_SD3_R_EN_BIT 4
262#define PBC_INTR_SD2_R_EN_BIT 0
263#define PBC_INTR_SD1_R_EN_BIT 6
264#define PBC_INTR_MS_R_EN_BIT 5
265#define PBC_INTR_SD3_EN_BIT 13
266#define PBC_INTR_SD2_EN_BIT 12
267#define PBC_INTR_MS_EN_BIT 14
268#define PBC_INTR_SD1_EN_BIT 15
269
270#define PBC_INTR_SD2_R_EN 0x0001
271#define PBC_INTR_LOW_BAT 0X0002
272#define PBC_INTR_OTG_FSOVER 0X0004
273#define PBC_INTR_FSH_OVER 0X0008
274#define PBC_INTR_SD3_R_EN 0x0010
275#define PBC_INTR_MS_R_EN 0x0020
276#define PBC_INTR_SD1_R_EN 0x0040
277#define PBC_INTR_FEC_INT 0X0080
278#define PBC_INTR_ENET_INT 0X0100
279#define PBC_INTR_OTGFS_INT 0X0200
280#define PBC_INTR_XUART_INT 0X0400
281#define PBC_INTR_CCTL12 0X0800
282#define PBC_INTR_SD2_EN 0x1000
283#define PBC_INTR_SD3_EN 0x2000
284#define PBC_INTR_MS_EN 0x4000
285#define PBC_INTR_SD1_EN 0x8000
286
287
288
289/* For interrupts like xuart, enet etc */
290#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
291#define MXC_MAX_EXP_IO_LINES 16
292
293/*
294 * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
295 *
296 */
297#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
298#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
299#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
300#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
301#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
302#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
303#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
304#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
305#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
306#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
307#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
308#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
309#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
310#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
311#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
312
313/*
314 * This is System IRQ used by CS8900A for interrupt generation
315 * taken from platform.h
316 */
317#define CS8900AIRQ EXPIO_INT_ENET_INT
318/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
319#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
320
321#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
322
323/*
324* This is used to detect if the CPLD version is for mx27 evb board rev-a
325*/
326#define PBC_CPLD_VERSION_IS_REVA() \
327 ((__raw_readw(PBC_VERSION_REG) & \
328 (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
329 == 0)
330
331/* This is used to active or inactive ata signal in CPLD .
332 * It is dependent with hardware
333 */
334#define PBC_ATA_SIGNAL_ACTIVE() \
335 __raw_writew( \
336 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
337 PBC_BCTRL2_CLEAR_REG)
338
339#define PBC_ATA_SIGNAL_INACTIVE() \
340 __raw_writew( \
341 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
342 PBC_BCTRL2_SET_REG)
343
344#define MXC_BD_LED1 (1 << 5)
345#define MXC_BD_LED2 (1 << 6)
346#define MXC_BD_LED_ON(led) \
347 __raw_writew(led, PBC_BCTRL1_SET_REG)
348#define MXC_BD_LED_OFF(led) \
349 __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
350
351/* to determine the correct external crystal reference */
352#define CKIH_27MHZ_BIT_SET (1 << 3)
353
354#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
index 8590127760a8..1bc6fb0f9a83 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -109,4 +109,9 @@
109 109
110#define MXC_MAX_EXP_IO_LINES 16 110#define MXC_MAX_EXP_IO_LINES 16
111 111
112/* mandatory for CONFIG_LL_DEBUG */
113
114#define MXC_LL_UART_PADDR UART1_BASE_ADDR
115#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
116
112#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ 117#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31lite.h b/include/asm-arm/arch-mxc/board-mx31lite.h
new file mode 100644
index 000000000000..e4e5cf5ad7db
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31lite.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
12#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
13
14#define MXC_MAX_EXP_IO_LINES 16
15
16
17/*
18 * Memory Size parameters
19 */
20
21/*
22 * Size of SDRAM memory
23 */
24#define SDRAM_MEM_SIZE SZ_128M
25/*
26 * Size of MBX buffer memory
27 */
28#define MXC_MBX_MEM_SIZE SZ_16M
29/*
30 * Size of memory available to kernel
31 */
32#define MEM_SIZE (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE)
33
34#define MXC_LL_UART_PADDR UART1_BASE_ADDR
35#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
36
37#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
38
diff --git a/include/asm-arm/arch-mxc/board-pcm037.h b/include/asm-arm/arch-mxc/board-pcm037.h
new file mode 100644
index 000000000000..82232ba3c8fc
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm037.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
20#define __ASM_ARCH_MXC_BOARD_PCM037_H__
21
22/* mandatory for CONFIG_LL_DEBUG */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
26
27#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/include/asm-arm/arch-mxc/board-pcm038.h b/include/asm-arm/arch-mxc/board-pcm038.h
new file mode 100644
index 000000000000..750c62afd90f
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm038.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
20#define __ASM_ARCH_MXC_BOARD_PCM038_H__
21
22/* mandatory for CONFIG_LL_DEBUG */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
26
27#ifndef __ASSEMBLY__
28/*
29 * This CPU module needs a baseboard to work. After basic initializing
30 * its own devices, it calls baseboard's init function.
31 * TODO: Add your own baseboard init function and call it from
32 * inside pcm038_init().
33 *
34 * This example here is for the development board. Refer pcm970-baseboard.c
35 */
36
37extern void pcm970_baseboard_init(void);
38
39#endif
40
41#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/include/asm-arm/arch-mxc/clock.h b/include/asm-arm/arch-mxc/clock.h
new file mode 100644
index 000000000000..24caa2b7c91d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/clock.h
@@ -0,0 +1,67 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_CLOCK_H__
21#define __ASM_ARCH_MXC_CLOCK_H__
22
23#ifndef __ASSEMBLY__
24#include <linux/list.h>
25
26struct module;
27
28struct clk {
29 struct list_head node;
30 struct module *owner;
31 const char *name;
32 int id;
33 /* Source clock this clk depends on */
34 struct clk *parent;
35 /* Secondary clock to enable/disable with this clock */
36 struct clk *secondary;
37 /* Reference count of clock enable/disable */
38 __s8 usecount;
39 /* Register bit position for clock's enable/disable control. */
40 u8 enable_shift;
41 /* Register address for clock's enable/disable control. */
42 u32 enable_reg;
43 u32 flags;
44 /* get the current clock rate (always a fresh value) */
45 unsigned long (*get_rate) (struct clk *);
46 /* Function ptr to set the clock to a new rate. The rate must match a
47 supported rate returned from round_rate. Leave blank if clock is not
48 programmable */
49 int (*set_rate) (struct clk *, unsigned long);
50 /* Function ptr to round the requested clock rate to the nearest
51 supported rate that is less than or equal to the requested rate. */
52 unsigned long (*round_rate) (struct clk *, unsigned long);
53 /* Function ptr to enable the clock. Leave blank if clock can not
54 be gated. */
55 int (*enable) (struct clk *);
56 /* Function ptr to disable the clock. Leave blank if clock can not
57 be gated. */
58 void (*disable) (struct clk *);
59 /* Function ptr to set the parent clock of the clock. */
60 int (*set_parent) (struct clk *, struct clk *);
61};
62
63int clk_register(struct clk *clk);
64void clk_unregister(struct clk *clk);
65
66#endif /* __ASSEMBLY__ */
67#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
index 23b4350edbd6..a6d2e24aab15 100644
--- a/include/asm-arm/arch-mxc/common.h
+++ b/include/asm-arm/arch-mxc/common.h
@@ -11,10 +11,10 @@
11#ifndef __ASM_ARCH_MXC_COMMON_H__ 11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__ 12#define __ASM_ARCH_MXC_COMMON_H__
13 13
14struct sys_timer;
15
16extern void mxc_map_io(void); 14extern void mxc_map_io(void);
17extern void mxc_init_irq(void); 15extern void mxc_init_irq(void);
18extern struct sys_timer mxc_timer; 16extern void mxc_timer_init(const char *clk_timer);
17extern int mxc_clocks_init(unsigned long fref);
18extern int mxc_register_gpios(void);
19 19
20#endif 20#endif
diff --git a/include/asm-arm/arch-mxc/debug-macro.S b/include/asm-arm/arch-mxc/debug-macro.S
new file mode 100644
index 000000000000..575087f8561a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/debug-macro.S
@@ -0,0 +1,49 @@
1/* linux/include/asm-arm/arch-imx/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <asm/arch/hardware.h>
15
16#ifdef CONFIG_MACH_MX31ADS
17#include <asm/arch/board-mx31ads.h>
18#endif
19#ifdef CONFIG_MACH_PCM037
20#include <asm/arch/board-pcm037.h>
21#endif
22#ifdef CONFIG_MACH_MX31LITE
23#include <asm/arch/board-mx31lite.h>
24#endif
25#ifdef CONFIG_MACH_MX27ADS
26#include <asm/arch/board-mx27ads.h>
27#endif
28#ifdef CONFIG_MACH_PCM038
29#include <asm/arch/board-pcm038.h>
30#endif
31 .macro addruart,rx
32 mrc p15, 0, \rx, c1, c0
33 tst \rx, #1 @ MMU enabled?
34 ldreq \rx, =MXC_LL_UART_PADDR @ physical
35 ldrne \rx, =MXC_LL_UART_VADDR @ virtual
36 .endm
37
38 .macro senduart,rd,rx
39 str \rd, [\rx, #0x40] @ TXDATA
40 .endm
41
42 .macro waituart,rd,rx
43 .endm
44
45 .macro busyuart,rd,rx
461002: ldr \rd, [\rx, #0x98] @ SR2
47 tst \rd, #1 << 3 @ TXDC
48 beq 1002b @ wait until transmit done
49 .endm
diff --git a/include/asm-arm/arch-mxc/gpio.h b/include/asm-arm/arch-mxc/gpio.h
new file mode 100644
index 000000000000..d393e15f5a6b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/gpio.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_GPIO_H__
20#define __ASM_ARCH_MXC_GPIO_H__
21
22#include <asm/hardware.h>
23#include <asm-generic/gpio.h>
24
25/* use gpiolib dispatchers */
26#define gpio_get_value __gpio_get_value
27#define gpio_set_value __gpio_set_value
28#define gpio_cansleep __gpio_cansleep
29
30#define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio))
31#define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES)
32
33struct mxc_gpio_port {
34 void __iomem *base;
35 int irq;
36 int virtual_irq_start;
37 struct gpio_chip chip;
38};
39
40int mxc_gpio_init(struct mxc_gpio_port*, int);
41
42#endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
index e87ff0679d5e..37cddbaaade7 100644
--- a/include/asm-arm/arch-mxc/hardware.h
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -1,11 +1,20 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 4 *
5/* 5 * This program is free software; you can redistribute it and/or
6 * This program is free software; you can redistribute it and/or modify 6 * modify it under the terms of the GNU General Public License
7 * it under the terms of the GNU General Public License version 2 as 7 * as published by the Free Software Foundation; either version 2
8 * published by the Free Software Foundation. 8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
9 */ 18 */
10 19
11#ifndef __ASM_ARCH_MXC_HARDWARE_H__ 20#ifndef __ASM_ARCH_MXC_HARDWARE_H__
@@ -17,15 +26,12 @@
17# include <asm/arch/mx31.h> 26# include <asm/arch/mx31.h>
18#endif 27#endif
19 28
20#include <asm/arch/mxc.h> 29#ifdef CONFIG_ARCH_MX2
21 30# ifdef CONFIG_MACH_MX27
22/* 31# include <asm/arch/mx27.h>
23 * --------------------------------------------------------------------------- 32# endif
24 * Board specific defines
25 * ---------------------------------------------------------------------------
26 */
27#ifdef CONFIG_MACH_MX31ADS
28# include <asm/arch/board-mx31ads.h>
29#endif 33#endif
30 34
35#include <asm/arch/mxc.h>
36
31#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 37#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/iim.h b/include/asm-arm/arch-mxc/iim.h
new file mode 100644
index 000000000000..315bffadafda
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iim.h
@@ -0,0 +1,77 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_IIM_H__
21#define __ASM_ARCH_MXC_IIM_H__
22
23/* Register offsets */
24#define MXC_IIMSTAT 0x0000
25#define MXC_IIMSTATM 0x0004
26#define MXC_IIMERR 0x0008
27#define MXC_IIMEMASK 0x000C
28#define MXC_IIMFCTL 0x0010
29#define MXC_IIMUA 0x0014
30#define MXC_IIMLA 0x0018
31#define MXC_IIMSDAT 0x001C
32#define MXC_IIMPREV 0x0020
33#define MXC_IIMSREV 0x0024
34#define MXC_IIMPRG_P 0x0028
35#define MXC_IIMSCS0 0x002C
36#define MXC_IIMSCS1 0x0030
37#define MXC_IIMSCS2 0x0034
38#define MXC_IIMSCS3 0x0038
39#define MXC_IIMFBAC0 0x0800
40#define MXC_IIMJAC 0x0804
41#define MXC_IIMHWV1 0x0808
42#define MXC_IIMHWV2 0x080C
43#define MXC_IIMHAB0 0x0810
44#define MXC_IIMHAB1 0x0814
45/* Definitions for i.MX27 TO2 */
46#define MXC_IIMMAC 0x0814
47#define MXC_IIMPREV_FUSE 0x0818
48#define MXC_IIMSREV_FUSE 0x081C
49#define MXC_IIMSJC_CHALL_0 0x0820
50#define MXC_IIMSJC_CHALL_7 0x083C
51#define MXC_IIMFB0UC17 0x0840
52#define MXC_IIMFB0UC255 0x0BFC
53#define MXC_IIMFBAC1 0x0C00
54/* Definitions for i.MX27 TO2 */
55#define MXC_IIMSUID 0x0C04
56#define MXC_IIMKEY0 0x0C04
57#define MXC_IIMKEY20 0x0C54
58#define MXC_IIMSJC_RESP_0 0x0C58
59#define MXC_IIMSJC_RESP_7 0x0C74
60#define MXC_IIMFB1UC30 0x0C78
61#define MXC_IIMFB1UC255 0x0FFC
62
63/* Bit definitions */
64
65#define MXC_IIMHWV1_WLOCK (0x1 << 7)
66#define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6)
67#define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5)
68#define MXC_IIMHWV1_BOOT_INT (0x1 << 4)
69#define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3)
70#define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2)
71#define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1)
72
73#define MXC_IIMHWV2_WLOCK (0x1 << 7)
74#define MXC_IIMHWV2_BP_SDMA (0x1 << 6)
75#define MXC_IIMHWV2_SCM_DCM (0x1 << 5)
76
77#endif /* __ASM_ARCH_MXC_IIM_H__ */
diff --git a/include/asm-arm/arch-mxc/imx-uart.h b/include/asm-arm/arch-mxc/imx-uart.h
new file mode 100644
index 000000000000..83fb72c4048a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/imx-uart.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef ASMARM_ARCH_UART_H
20#define ASMARM_ARCH_UART_H
21
22#define IMXUART_HAVE_RTSCTS (1<<0)
23
24struct imxuart_platform_data {
25 int (*init)(struct platform_device *pdev);
26 int (*exit)(struct platform_device *pdev);
27 unsigned int flags;
28};
29
30int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata);
31
32#endif
diff --git a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
new file mode 100644
index 000000000000..076d37b38eb2
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
@@ -0,0 +1,372 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef _MXC_GPIO_MX1_MX2_H
20#define _MXC_GPIO_MX1_MX2_H
21
22#include <linux/io.h>
23
24#define MXC_GPIO_ALLOC_MODE_NORMAL 0
25#define MXC_GPIO_ALLOC_MODE_NO_ALLOC 1
26#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC 2
27#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY 4
28#define MXC_GPIO_ALLOC_MODE_RELEASE 8
29
30/*
31 * GPIO Module and I/O Multiplexer
32 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
33 */
34#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
35#define MXC_DDIR(x) (0x00 + ((x) << 8))
36#define MXC_OCR1(x) (0x04 + ((x) << 8))
37#define MXC_OCR2(x) (0x08 + ((x) << 8))
38#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
39#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
40#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
41#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
42#define MXC_DR(x) (0x1c + ((x) << 8))
43#define MXC_GIUS(x) (0x20 + ((x) << 8))
44#define MXC_SSR(x) (0x24 + ((x) << 8))
45#define MXC_ICR1(x) (0x28 + ((x) << 8))
46#define MXC_ICR2(x) (0x2c + ((x) << 8))
47#define MXC_IMR(x) (0x30 + ((x) << 8))
48#define MXC_ISR(x) (0x34 + ((x) << 8))
49#define MXC_GPR(x) (0x38 + ((x) << 8))
50#define MXC_SWR(x) (0x3c + ((x) << 8))
51#define MXC_PUEN(x) (0x40 + ((x) << 8))
52
53#ifdef CONFIG_ARCH_MX1
54# define GPIO_PORT_MAX 3
55#endif
56#ifdef CONFIG_ARCH_MX2
57# define GPIO_PORT_MAX 5
58#endif
59
60#ifndef GPIO_PORT_MAX
61# error "GPIO config port count unknown!"
62#endif
63
64#define GPIO_PIN_MASK 0x1f
65
66#define GPIO_PORT_SHIFT 5
67#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
68
69#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
70#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
71#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
72#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
73#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
74#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
75
76#define GPIO_OUT (1 << 8)
77#define GPIO_IN (0 << 8)
78#define GPIO_PUEN (1 << 9)
79
80#define GPIO_PF (1 << 10)
81#define GPIO_AF (1 << 11)
82
83#define GPIO_OCR_SHIFT 12
84#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
85#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
86#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
87#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
88#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
89
90#define GPIO_AOUT_SHIFT 14
91#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
92#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
93#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
94#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
95#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
96
97#define GPIO_BOUT_SHIFT 16
98#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
99#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
100#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
101#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
102#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
103
104extern void mxc_gpio_mode(int gpio_mode);
105extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
106 int alloc_mode, const char *label);
107
108/*-------------------------------------------------------------------------*/
109
110/* assignements for GPIO alternate/primary functions */
111
112/* FIXME: This list is not completed. The correct directions are
113 * missing on some (many) pins
114 */
115#ifdef CONFIG_ARCH_MX1
116#define PA0_AIN_SPI2_CLK (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0)
117#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
118#define PA1_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1)
119#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
120#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
121#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
122#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
123#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
124#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
125#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
126#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
127#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
128#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
129#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
130#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
131#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
132#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
133#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
134#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
135#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
136#define PA17_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17)
137#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
138#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
139#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
140#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
141#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
142#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
143#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
144#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
145#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
146#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
147#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
148#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
149#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
150#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
151#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
152#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
153#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
154#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
155#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
156#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
157#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
158#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
159#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
160#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
161#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
162#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
163#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
164#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
165#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
166#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
167#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
168#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
169#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
170#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
171#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
172#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
173#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
174#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
175#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
176#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
177#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
178#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
179#define PB22_PFUSBD_RCV (GPIO_PORTB | GPIO_PF | 22)
180#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
181#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
182#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
183#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
184#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
185#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
186#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
187#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
188#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
189#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
190#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
191#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
192#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
193#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
194#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
195#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
196#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
197#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
198#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
199#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
200#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
201#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
202#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
203#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
204#define PC24_BIN_UART3_RI (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
205#define PC25_BIN_UART3_DSR (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
206#define PC26_AOUT_UART3_DTR (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26)
207#define PC27_BIN_UART3_DCD (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
208#define PC28_BIN_UART3_CTS (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
209#define PC29_AOUT_UART3_RTS (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29)
210#define PC30_BIN_UART3_TX (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30)
211#define PC31_AOUT_UART3_RX (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
212#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
213#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
214#define PD7_AF_UART2_DTR (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
215#define PD7_AIN_SPI2_SCLK (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7)
216#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
217#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
218#define PD8_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8)
219#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
220#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
221#define PD9_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9)
222#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
223#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
224#define PD10_AIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10)
225#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
226#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
227#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
228#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
229#define PD15_PF_LD0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
230#define PD16_PF_LD1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
231#define PD17_PF_LD2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
232#define PD18_PF_LD3 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
233#define PD19_PF_LD4 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
234#define PD20_PF_LD5 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
235#define PD21_PF_LD6 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
236#define PD22_PF_LD7 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
237#define PD23_PF_LD8 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
238#define PD24_PF_LD9 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
239#define PD25_PF_LD10 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
240#define PD26_PF_LD11 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
241#define PD27_PF_LD12 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
242#define PD28_PF_LD13 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
243#define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
244#define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
245#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
246#define PD31_BIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31)
247#endif
248
249#ifdef CONFIG_ARCH_MX2
250#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
251#define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
252#define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
253#define PA8_PF_LD2 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
254#define PA9_PF_LD3 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
255#define PA10_PF_LD4 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
256#define PA11_PF_LD5 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
257#define PA12_PF_LD6 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
258#define PA13_PF_LD7 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
259#define PA14_PF_LD8 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
260#define PA15_PF_LD9 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
261#define PA16_PF_LD10 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
262#define PA17_PF_LD11 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
263#define PA18_PF_LD12 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
264#define PA19_PF_LD13 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
265#define PA20_PF_LD14 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
266#define PA21_PF_LD15 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
267#define PA22_PF_LD16 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
268#define PA23_PF_LD17 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
269#define PA24_PF_REV (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
270#define PA25_PF_CLS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
271#define PA26_PF_PS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
272#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
273#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
274#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
275#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
276#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
277#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
278#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
279#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
280#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 11)
281#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
282#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
283#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
284#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 13)
285#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
286#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
287#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
288#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
289#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
290#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
291#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
292#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 19)
293#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
294#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
295#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
296#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21)
297#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26)
298#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
299#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
300#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31)
301#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
302#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6)
303#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16)
304#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17)
305#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18)
306#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 19)
307#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 20)
308#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 21)
309#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 22)
310#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 23)
311#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 24)
312#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 25)
313#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 26)
314#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 27)
315#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 28)
316#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 29)
317#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 30)
318#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 31)
319#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
320#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
321#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
322#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
323#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
324#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
325#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
326#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
327#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
328#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
329#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
330#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
331#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
332#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
333#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
334#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
335#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
336#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
337#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
338#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
339#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
340#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
341#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
342#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
343#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30)
344#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31)
345#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
346#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
347#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
348#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
349#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
350#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
351#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
352#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
353#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
354#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
355#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
356#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
357#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
358#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18)
359#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
360#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
361#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
362#endif
363
364/* decode irq number to use with IMR(x), ISR(x) and friends */
365#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5)
366
367#define IRQ_GPIOA(x) (MXC_MAX_INT_LINES + x)
368#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
369#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
370#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
371
372#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/include/asm-arm/arch-mxc/iomux-mx3.h b/include/asm-arm/arch-mxc/iomux-mx3.h
new file mode 100644
index 000000000000..7509e7692f08
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx3.h
@@ -0,0 +1,501 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MACH_MX31_IOMUX_H__
21#define __MACH_MX31_IOMUX_H__
22
23#include <linux/types.h>
24
25/*
26 * various IOMUX output functions
27 */
28
29#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
30#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
31#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
32#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
33#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
34#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
35#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
36#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
37#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
38#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
39#define IOMUX_ICONFIG_FUNC 2 /* used as function */
40#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
41#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
42
43#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
44#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
45#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
46#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
47
48/*
49 * various IOMUX pad functions
50 */
51enum iomux_pad_config {
52 PAD_CTL_NOLOOPBACK = 0x0 << 9,
53 PAD_CTL_LOOPBACK = 0x1 << 9,
54 PAD_CTL_PKE_NONE = 0x0 << 8,
55 PAD_CTL_PKE_ENABLE = 0x1 << 8,
56 PAD_CTL_PUE_KEEPER = 0x0 << 7,
57 PAD_CTL_PUE_PUD = 0x1 << 7,
58 PAD_CTL_100K_PD = 0x0 << 5,
59 PAD_CTL_100K_PU = 0x1 << 5,
60 PAD_CTL_47K_PU = 0x2 << 5,
61 PAD_CTL_22K_PU = 0x3 << 5,
62 PAD_CTL_HYS_CMOS = 0x0 << 4,
63 PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
64 PAD_CTL_ODE_CMOS = 0x0 << 3,
65 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
66 PAD_CTL_DRV_NORMAL = 0x0 << 1,
67 PAD_CTL_DRV_HIGH = 0x1 << 1,
68 PAD_CTL_DRV_MAX = 0x2 << 1,
69 PAD_CTL_SRE_SLOW = 0x0 << 0,
70 PAD_CTL_SRE_FAST = 0x1 << 0
71};
72
73/*
74 * various IOMUX general purpose functions
75 */
76enum iomux_gp_func {
77 MUX_PGP_FIRI = 1 << 0,
78 MUX_DDR_MODE = 1 << 1,
79 MUX_PGP_CSPI_BB = 1 << 2,
80 MUX_PGP_ATA_1 = 1 << 3,
81 MUX_PGP_ATA_2 = 1 << 4,
82 MUX_PGP_ATA_3 = 1 << 5,
83 MUX_PGP_ATA_4 = 1 << 6,
84 MUX_PGP_ATA_5 = 1 << 7,
85 MUX_PGP_ATA_6 = 1 << 8,
86 MUX_PGP_ATA_7 = 1 << 9,
87 MUX_PGP_ATA_8 = 1 << 10,
88 MUX_PGP_UH2 = 1 << 11,
89 MUX_SDCTL_CSD0_SEL = 1 << 12,
90 MUX_SDCTL_CSD1_SEL = 1 << 13,
91 MUX_CSPI1_UART3 = 1 << 14,
92 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
93 MUX_TAMPER_DETECT_EN = 1 << 16,
94 MUX_PGP_USB_4WIRE = 1 << 17,
95 MUX_PGB_USB_COMMON = 1 << 18,
96 MUX_SDHC_MEMSTICK1 = 1 << 19,
97 MUX_SDHC_MEMSTICK2 = 1 << 20,
98 MUX_PGP_SPLL_BYP = 1 << 21,
99 MUX_PGP_UPLL_BYP = 1 << 22,
100 MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
101 MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
102 MUX_CSPI3_UART5_SEL = 1 << 25,
103 MUX_PGP_ATA_9 = 1 << 26,
104 MUX_PGP_USB_SUSPEND = 1 << 27,
105 MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
106 MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
107 MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
108 MUX_CLKO_DDR_MODE = 1 << 31,
109};
110
111/*
112 * This function enables/disables the general purpose function for a particular
113 * signal.
114 */
115void iomux_config_gpr(enum iomux_gp_func , bool);
116
117/*
118 * set the mode for a IOMUX pin.
119 */
120int mxc_iomux_mode(unsigned int);
121
122/*
123 * This function enables/disables the general purpose function for a particular
124 * signal.
125 */
126void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
127
128#define IOMUX_PADNUM_MASK 0x1ff
129#define IOMUX_GPIONUM_SHIFT 9
130#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
131#define IOMUX_MODE_SHIFT 17
132#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
133
134#define IOMUX_PIN(gpionum, padnum) \
135 (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
136 (padnum & IOMUX_PADNUM_MASK))
137
138#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
139
140#define IOMUX_TO_GPIO(iomux_pin) \
141 ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
142#define IOMUX_TO_IRQ(iomux_pin) \
143 (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
144 MXC_GPIO_INT_BASE)
145
146/*
147 * This enumeration is constructed based on the Section
148 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
149 * value is constructed based on the rules described above.
150 */
151
152enum iomux_pins {
153 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
154 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
155 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
156 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
157 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
158 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
159 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
160 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
161 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
162 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
163 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
164 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
165 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
166 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
167 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
168 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
169 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
170 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
171 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
172 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
173 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
174 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
175 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
176 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
177 MX31_PIN_READ = IOMUX_PIN(0xff, 24),
178 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
179 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
180 MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
181 MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
182 MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
183 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
184 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
185 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
186 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
187 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
188 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
189 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
190 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
191 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
192 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
193 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
194 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
195 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
196 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
197 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
198 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
199 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
200 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
201 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
202 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
203 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
204 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
205 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
206 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
207 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
208 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
209 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
210 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
211 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
212 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
213 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
214 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
215 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
216 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
217 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
218 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
219 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
220 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
221 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
222 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
223 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
224 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
225 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
226 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
227 MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
228 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
229 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
230 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
231 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
232 MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
233 MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
234 MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
235 MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
236 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
237 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
238 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
239 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
240 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
241 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
242 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
243 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
244 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
245 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
246 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
247 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
248 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
249 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
250 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
251 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
252 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
253 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
254 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
255 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
256 MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
257 MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
258 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
259 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
260 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
261 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
262 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
263 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
264 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
265 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
266 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
267 MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
268 MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
269 MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
270 MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
271 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
272 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
273 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
274 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
275 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
276 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
277 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
278 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
279 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
280 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
281 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
282 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
283 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
284 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
285 MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
286 MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
287 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
288 MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
289 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
290 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
291 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
292 MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
293 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
294 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
295 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
296 MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
297 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
298 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
299 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
300 MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
301 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
302 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
303 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
304 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
305 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
306 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
307 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
308 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
309 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
310 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
311 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
312 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
313 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
314 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
315 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
316 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
317 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
318 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
319 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
320 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
321 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
322 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
323 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
324 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
325 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
326 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
327 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
328 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
329 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
330 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
331 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
332 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
333 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
334 MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
335 MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
336 MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
337 MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
338 MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
339 MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
340 MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
341 MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
342 MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
343 MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
344 MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
345 MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
346 MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
347 MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
348 MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
349 MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
350 MX31_PIN_NFRB = IOMUX_PIN(16, 197),
351 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
352 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
353 MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
354 MX31_PIN_NFALE = IOMUX_PIN(12, 201),
355 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
356 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
357 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
358 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
359 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
360 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
361 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
362 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
363 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
364 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
365 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
366 MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
367 MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
368 MX31_PIN_RW = IOMUX_PIN(0xff, 215),
369 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
370 MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
371 MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
372 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
373 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
374 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
375 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
376 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
377 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
378 MX31_PIN_OE = IOMUX_PIN(0xff, 225),
379 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
380 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
381 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
382 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
383 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
384 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
385 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
386 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
387 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
388 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
389 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
390 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
391 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
392 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
393 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
394 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
395 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
396 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
397 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
398 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
399 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
400 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
401 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
402 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
403 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
404 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
405 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
406 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
407 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
408 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
409 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
410 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
411 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
412 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
413 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
414 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
415 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
416 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
417 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
418 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
419 MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
420 MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
421 MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
422 MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
423 MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
424 MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
425 MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
426 MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
427 MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
428 MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
429 MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
430 MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
431 MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
432 MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
433 MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
434 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
435 MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
436 MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
437 MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
438 MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
439 MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
440 MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
441 MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
442 MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
443 MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
444 MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
445 MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
446 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
447 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
448 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
449 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
450 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
451 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
452 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
453 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
454 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
455 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
456 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
457 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
458 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
459 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
460 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
461 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
462 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
463 MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
464 MX31_PIN_STX0 = IOMUX_PIN(33, 311),
465 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
466 MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
467 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
468 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
469 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
470 MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317),
471 MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318),
472 MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319),
473 MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320),
474 MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321),
475 MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322),
476 MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323),
477 MX31_PIN_PWMO = IOMUX_PIN( 9, 324),
478 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
479 MX31_PIN_COMPARE = IOMUX_PIN( 8, 326),
480 MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327),
481};
482
483/*
484 * Convenience values for use with mxc_iomux_mode()
485 *
486 * Format here is MX31_PIN_(pin name)__(function)
487 */
488#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
489#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
490#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
491#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
492#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
493#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
494
495/*
496 * This function configures the pad value for a IOMUX pin.
497 */
498void mxc_iomux_set_pad(enum iomux_pins, u32);
499
500#endif
501
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index b2c5205e1962..f416130718cf 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,17 +13,4 @@
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
17
18#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
19#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
20
21/* Number of normal interrupts */
22#define NR_IRQS (MXC_MAX_INT_LINES + \
23 MXC_MAX_GPIO_LINES + \
24 MXC_MAX_VIRTUAL_INTS)
25
26/* Number of fast interrupts */
27#define NR_FIQS MXC_MAX_INTS
28
29#endif /* __ASM_ARCH_MXC_IRQS_H__ */ 16#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/mx27.h b/include/asm-arm/arch-mxc/mx27.h
new file mode 100644
index 000000000000..212ecc246626
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx27.h
@@ -0,0 +1,302 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_MX27_H__
21#define __ASM_ARCH_MXC_MX27_H__
22
23#ifndef __ASM_ARCH_MXC_HARDWARE_H__
24#error "Do not include directly."
25#endif
26
27/* IRAM */
28#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
29
30/* Register offests */
31#define AIPI_BASE_ADDR 0x10000000
32#define AIPI_BASE_ADDR_VIRT 0xF4000000
33#define AIPI_SIZE SZ_1M
34
35#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
36#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
37#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
38#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
39#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
40#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
41#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
42#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
43#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
44#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
45#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
46#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
47#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
48#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
49#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
50#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
51#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
52#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
53#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
54#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
55#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
56#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
57
58#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
59#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
60#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
61#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
62#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000)
63#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000)
64#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
65#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
66#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
67
68#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
69#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
70#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
71#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
72/* for mx27*/
73#define OTG_BASE_ADDR USBOTG_BASE_ADDR
74#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
75#define EMMA_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
76#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
77#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
78#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
79
80#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
81#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
82#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
83#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
84#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
85
86#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
87#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
88
89/* ROMP and AVIC */
90#define ROMP_BASE_ADDR 0x10041000
91
92#define AVIC_BASE_ADDR 0x10040000
93
94#define SAHB1_BASE_ADDR 0x80000000
95#define SAHB1_BASE_ADDR_VIRT 0xF4100000
96#define SAHB1_SIZE SZ_1M
97
98#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
99#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
100
101/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
102#define X_MEMC_BASE_ADDR 0xD8000000
103#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
104#define X_MEMC_SIZE SZ_1M
105
106#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
107#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
108#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
109#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
110#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
111
112/* Memory regions and CS */
113#define SDRAM_BASE_ADDR 0xA0000000
114#define CSD1_BASE_ADDR 0xB0000000
115
116#define CS0_BASE_ADDR 0xC0000000
117#define CS1_BASE_ADDR 0xC8000000
118#define CS2_BASE_ADDR 0xD0000000
119#define CS3_BASE_ADDR 0xD2000000
120#define CS4_BASE_ADDR 0xD4000000
121#define CS5_BASE_ADDR 0xD6000000
122#define PCMCIA_MEM_BASE_ADDR 0xDC000000
123
124/*
125 * This macro defines the physical to virtual address mapping for all the
126 * peripheral modules. It is used by passing in the physical address as x
127 * and returning the virtual address. If the physical address is not mapped,
128 * it returns 0xDEADBEEF
129 */
130#define IO_ADDRESS(x) \
131 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
132 AIPI_IO_ADDRESS(x) : \
133 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
134 SAHB1_IO_ADDRESS(x) : \
135 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
136 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
137
138/* define the address mapping macros: in physical address order */
139#define AIPI_IO_ADDRESS(x) \
140 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
141
142#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
143
144#define SAHB1_IO_ADDRESS(x) \
145 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
146
147#define CS4_IO_ADDRESS(x) \
148 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
149
150#define X_MEMC_IO_ADDRESS(x) \
151 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
152
153#define PCMCIA_IO_ADDRESS(x) \
154 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
155
156/* fixed interrput numbers */
157#define MXC_INT_CCM 63
158#define MXC_INT_IIM 62
159#define MXC_INT_LCDC 61
160#define MXC_INT_SLCDC 60
161#define MXC_INT_SAHARA 59
162#define MXC_INT_SCC_SCM 58
163#define MXC_INT_SCC_SMN 57
164#define MXC_INT_USB3 56
165#define MXC_INT_USB2 55
166#define MXC_INT_USB1 54
167#define MXC_INT_VPU 53
168#define MXC_INT_EMMAPP 52
169#define MXC_INT_EMMAPRP 51
170#define MXC_INT_FEC 50
171#define MXC_INT_UART5 49
172#define MXC_INT_UART6 48
173#define MXC_INT_DMACH15 47
174#define MXC_INT_DMACH14 46
175#define MXC_INT_DMACH13 45
176#define MXC_INT_DMACH12 44
177#define MXC_INT_DMACH11 43
178#define MXC_INT_DMACH10 42
179#define MXC_INT_DMACH9 41
180#define MXC_INT_DMACH8 40
181#define MXC_INT_DMACH7 39
182#define MXC_INT_DMACH6 38
183#define MXC_INT_DMACH5 37
184#define MXC_INT_DMACH4 36
185#define MXC_INT_DMACH3 35
186#define MXC_INT_DMACH2 34
187#define MXC_INT_DMACH1 33
188#define MXC_INT_DMACH0 32
189#define MXC_INT_CSI 31
190#define MXC_INT_ATA 30
191#define MXC_INT_NANDFC 29
192#define MXC_INT_PCMCIA 28
193#define MXC_INT_WDOG 27
194#define MXC_INT_GPT1 26
195#define MXC_INT_GPT2 25
196#define MXC_INT_GPT3 24
197#define MXC_INT_GPT INT_GPT1
198#define MXC_INT_PWM 23
199#define MXC_INT_RTC 22
200#define MXC_INT_KPP 21
201#define MXC_INT_UART1 20
202#define MXC_INT_UART2 19
203#define MXC_INT_UART3 18
204#define MXC_INT_UART4 17
205#define MXC_INT_CSPI1 16
206#define MXC_INT_CSPI2 15
207#define MXC_INT_SSI1 14
208#define MXC_INT_SSI2 13
209#define MXC_INT_I2C 12
210#define MXC_INT_SDHC1 11
211#define MXC_INT_SDHC2 10
212#define MXC_INT_SDHC3 9
213#define MXC_INT_GPIO 8
214#define MXC_INT_SDHC 7
215#define MXC_INT_CSPI3 6
216#define MXC_INT_RTIC 5
217#define MXC_INT_GPT4 4
218#define MXC_INT_GPT5 3
219#define MXC_INT_GPT6 2
220#define MXC_INT_I2C2 1
221
222/* fixed DMA request numbers */
223#define DMA_REQ_NFC 37
224#define DMA_REQ_SDHC3 36
225#define DMA_REQ_UART6_RX 35
226#define DMA_REQ_UART6_TX 34
227#define DMA_REQ_UART5_RX 33
228#define DMA_REQ_UART5_TX 32
229#define DMA_REQ_CSI_RX 31
230#define DMA_REQ_CSI_STAT 30
231#define DMA_REQ_ATA_RCV 29
232#define DMA_REQ_ATA_TX 28
233#define DMA_REQ_UART1_TX 27
234#define DMA_REQ_UART1_RX 26
235#define DMA_REQ_UART2_TX 25
236#define DMA_REQ_UART2_RX 24
237#define DMA_REQ_UART3_TX 23
238#define DMA_REQ_UART3_RX 22
239#define DMA_REQ_UART4_TX 21
240#define DMA_REQ_UART4_RX 20
241#define DMA_REQ_CSPI1_TX 19
242#define DMA_REQ_CSPI1_RX 18
243#define DMA_REQ_CSPI2_TX 17
244#define DMA_REQ_CSPI2_RX 16
245#define DMA_REQ_SSI1_TX1 15
246#define DMA_REQ_SSI1_RX1 14
247#define DMA_REQ_SSI1_TX0 13
248#define DMA_REQ_SSI1_RX0 12
249#define DMA_REQ_SSI2_TX1 11
250#define DMA_REQ_SSI2_RX1 10
251#define DMA_REQ_SSI2_TX0 9
252#define DMA_REQ_SSI2_RX0 8
253#define DMA_REQ_SDHC1 7
254#define DMA_REQ_SDHC2 6
255#define DMA_REQ_MSHC 4
256#define DMA_REQ_EXT 3
257#define DMA_REQ_CSPI3_TX 2
258#define DMA_REQ_CSPI3_RX 1
259
260/* silicon revisions specific to i.MX27 */
261#define CHIP_REV_1_0 0x00
262#define CHIP_REV_2_0 0x01
263
264#ifndef __ASSEMBLY__
265extern int mx27_revision(void);
266#endif
267
268/* gpio and gpio based interrupt handling */
269#define GPIO_DR 0x1C
270#define GPIO_GDIR 0x00
271#define GPIO_PSR 0x24
272#define GPIO_ICR1 0x28
273#define GPIO_ICR2 0x2C
274#define GPIO_IMR 0x30
275#define GPIO_ISR 0x34
276#define GPIO_INT_LOW_LEV 0x3
277#define GPIO_INT_HIGH_LEV 0x2
278#define GPIO_INT_RISE_EDGE 0x0
279#define GPIO_INT_FALL_EDGE 0x1
280#define GPIO_INT_NONE 0x4
281
282/* Mandatory defines used globally */
283
284/* this is an i.MX27 CPU */
285#define cpu_is_mx27() (1)
286
287/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
288#define ARCH_NR_GPIOS (192 + 16)
289
290/* OS clock tick rate */
291#define CLOCK_TICK_RATE 13300000
292
293/* Start of RAM */
294#define PHYS_OFFSET SDRAM_BASE_ADDR
295
296/* max interrupt lines count */
297#define NR_IRQS 256
298
299/* count of internal interrupt sources */
300#define MXC_MAX_INT_LINES 64
301
302#endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 36a1af495bb3..a7373e4a56cb 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -320,6 +320,8 @@
320#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) 320#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
321#define MXC_MAX_VIRTUAL_INTS 16 321#define MXC_MAX_VIRTUAL_INTS 16
322 322
323#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
324
323/*! 325/*!
324 * Number of GPIO port as defined in the IC Spec 326 * Number of GPIO port as defined in the IC Spec
325 */ 327 */
@@ -347,6 +349,25 @@
347#define SYSTEM_REV_MIN CHIP_REV_1_0 349#define SYSTEM_REV_MIN CHIP_REV_1_0
348#define SYSTEM_REV_NUM 3 350#define SYSTEM_REV_NUM 3
349 351
352/* gpio and gpio based interrupt handling */
353#define GPIO_DR 0x00
354#define GPIO_GDIR 0x04
355#define GPIO_PSR 0x08
356#define GPIO_ICR1 0x0C
357#define GPIO_ICR2 0x10
358#define GPIO_IMR 0x14
359#define GPIO_ISR 0x18
360#define GPIO_INT_LOW_LEV 0x0
361#define GPIO_INT_HIGH_LEV 0x1
362#define GPIO_INT_RISE_EDGE 0x2
363#define GPIO_INT_FALL_EDGE 0x3
364#define GPIO_INT_NONE 0x4
365
366/* Mandatory defines used globally */
367
368/* this CPU supports up to 96 GPIOs */
369#define ARCH_NR_GPIOS 96
370
350#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 371#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
351 372
352/* this is a i.MX31 CPU */ 373/* this is a i.MX31 CPU */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 146d3f60951a..332eda4dbd3b 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -1,11 +1,20 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 4 *
5/* 5 * This program is free software; you can redistribute it and/or
6 * This program is free software; you can redistribute it and/or modify 6 * modify it under the terms of the GNU General Public License
7 * it under the terms of the GNU General Public License version 2 as 7 * as published by the Free Software Foundation; either version 2
8 * published by the Free Software Foundation. 8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
9 */ 18 */
10 19
11#ifndef __ASM_ARCH_MXC_H__ 20#ifndef __ASM_ARCH_MXC_H__
@@ -20,133 +29,8 @@
20# define cpu_is_mx31() (0) 29# define cpu_is_mx31() (0)
21#endif 30#endif
22 31
23/* 32#ifndef CONFIG_MACH_MX27
24 ***************************************** 33# define cpu_is_mx27() (0)
25 * GPT Register definitions * 34#endif
26 *****************************************
27 */
28#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
29#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
30#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
31#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
32#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
33#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
34#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
35#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
36#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
37#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
38
39/* GPT Control register bit definitions */
40#define GPTCR_FO3 (1 << 31)
41#define GPTCR_FO2 (1 << 30)
42#define GPTCR_FO1 (1 << 29)
43
44#define GPTCR_OM3_SHIFT 26
45#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
46#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
47#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
48#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
49#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
50#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
51
52#define GPTCR_OM2_SHIFT 23
53#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
54#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
55#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
56#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
57#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
58#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
59
60#define GPTCR_OM1_SHIFT 20
61#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
62#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
63#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
64#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
65#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
66#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
67
68#define GPTCR_IM2_SHIFT 18
69#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
70#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
71#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
72#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
73#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
74
75#define GPTCR_IM1_SHIFT 16
76#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
77#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
78#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
79#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
80#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
81
82#define GPTCR_SWR (1 << 15)
83#define GPTCR_FRR (1 << 9)
84
85#define GPTCR_CLKSRC_SHIFT 6
86#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
87#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
88#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
89#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
90#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
91
92#define GPTCR_STOPEN (1 << 5)
93#define GPTCR_DOZEN (1 << 4)
94#define GPTCR_WAITEN (1 << 3)
95#define GPTCR_DBGEN (1 << 2)
96
97#define GPTCR_ENMOD (1 << 1)
98#define GPTCR_ENABLE (1 << 0)
99
100#define GPTSR_OF1 (1 << 0)
101#define GPTSR_OF2 (1 << 1)
102#define GPTSR_OF3 (1 << 2)
103#define GPTSR_IF1 (1 << 3)
104#define GPTSR_IF2 (1 << 4)
105#define GPTSR_ROV (1 << 5)
106
107#define GPTIR_OF1IE GPTSR_OF1
108#define GPTIR_OF2IE GPTSR_OF2
109#define GPTIR_OF3IE GPTSR_OF3
110#define GPTIR_IF1IE GPTSR_IF1
111#define GPTIR_IF2IE GPTSR_IF2
112#define GPTIR_ROVIE GPTSR_ROV
113
114/*
115 *****************************************
116 * AVIC Registers *
117 *****************************************
118 */
119#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
120#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
121#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
122#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
123#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
124#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
125#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
126#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
127#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
128#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
129#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
130#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
131#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
132#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
133#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
134#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
135#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
136#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
137#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
138#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
139#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
140#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
141#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
142#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
143#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
144#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
145#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
146
147#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
148#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
149#define IIM_PROD_REV_SH 3
150#define IIM_PROD_REV_LEN 5
151 35
152#endif /* __ASM_ARCH_MXC_H__ */ 36#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h
new file mode 100644
index 000000000000..6cb11f4f1a06
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc_timer.h
@@ -0,0 +1,158 @@
1/*
2 * mxc_timer.h
3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 *
6 * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 * Boston, MA 02110-1301, USA.
21 */
22
23#ifndef __PLAT_MXC_TIMER_H
24#define __PLAT_MXC_TIMER_H
25
26#include <linux/clk.h>
27#include <asm/hardware.h>
28
29#ifdef CONFIG_ARCH_IMX
30#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
31#define TIMER_INTERRUPT TIM1_INT
32
33#define TCTL_VAL TCTL_CLK_PCLK1
34#define TCTL_IRQEN (1<<4)
35#define TCTL_FRR (1<<8)
36#define TCTL_CLK_PCLK1 (1<<1)
37#define TCTL_CLK_PCLK1_4 (2<<1)
38#define TCTL_CLK_TIN (3<<1)
39#define TCTL_CLK_32 (4<<1)
40
41#define MXC_TCTL 0x00
42#define MXC_TPRER 0x04
43#define MXC_TCMP 0x08
44#define MXC_TCR 0x0c
45#define MXC_TCN 0x10
46#define MXC_TSTAT 0x14
47#define TSTAT_CAPT (1<<1)
48#define TSTAT_COMP (1<<0)
49
50static inline void gpt_irq_disable(void)
51{
52 unsigned int tmp;
53
54 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
55 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
56}
57
58static inline void gpt_irq_enable(void)
59{
60 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
61 TIMER_BASE + MXC_TCTL);
62}
63
64static void gpt_irq_acknowledge(void)
65{
66 __raw_writel(0, TIMER_BASE + MXC_TSTAT);
67}
68#endif /* CONFIG_ARCH_IMX */
69
70#ifdef CONFIG_ARCH_MX2
71#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
72#define TIMER_INTERRUPT MXC_INT_GPT1
73
74#define MXC_TCTL 0x00
75#define TCTL_VAL TCTL_CLK_PCLK1
76#define TCTL_CLK_PCLK1 (1<<1)
77#define TCTL_CLK_PCLK1_4 (2<<1)
78#define TCTL_IRQEN (1<<4)
79#define TCTL_FRR (1<<8)
80#define MXC_TPRER 0x04
81#define MXC_TCMP 0x08
82#define MXC_TCR 0x0c
83#define MXC_TCN 0x10
84#define MXC_TSTAT 0x14
85#define TSTAT_CAPT (1<<1)
86#define TSTAT_COMP (1<<0)
87
88static inline void gpt_irq_disable(void)
89{
90 unsigned int tmp;
91
92 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
93 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
94}
95
96static inline void gpt_irq_enable(void)
97{
98 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
99 TIMER_BASE + MXC_TCTL);
100}
101
102static void gpt_irq_acknowledge(void)
103{
104 __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
105}
106#endif /* CONFIG_ARCH_MX2 */
107
108#ifdef CONFIG_ARCH_MX3
109#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
110#define TIMER_INTERRUPT MXC_INT_GPT
111
112#define MXC_TCTL 0x00
113#define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN)
114#define TCTL_CLK_IPG (1<<6)
115#define TCTL_FRR (1<<9)
116#define TCTL_WAITEN (1<<3)
117
118#define MXC_TPRER 0x04
119#define MXC_TSTAT 0x08
120#define TSTAT_OF1 (1<<0)
121#define TSTAT_OF2 (1<<1)
122#define TSTAT_OF3 (1<<2)
123#define TSTAT_IF1 (1<<3)
124#define TSTAT_IF2 (1<<4)
125#define TSTAT_ROV (1<<5)
126#define MXC_IR 0x0c
127#define MXC_TCMP 0x10
128#define MXC_TCMP2 0x14
129#define MXC_TCMP3 0x18
130#define MXC_TCR 0x1c
131#define MXC_TCN 0x24
132
133static inline void gpt_irq_disable(void)
134{
135 __raw_writel(0, TIMER_BASE + MXC_IR);
136}
137
138static inline void gpt_irq_enable(void)
139{
140 __raw_writel(1<<0, TIMER_BASE + MXC_IR);
141}
142
143static inline void gpt_irq_acknowledge(void)
144{
145 __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
146}
147#endif /* CONFIG_ARCH_MX3 */
148
149#define TCTL_SWR (1<<15)
150#define TCTL_CC (1<<10)
151#define TCTL_OM (1<<9)
152#define TCTL_CAP_RIS (1<<6)
153#define TCTL_CAP_FAL (2<<6)
154#define TCTL_CAP_RIS_FAL (3<<6)
155#define TCTL_CAP_ENA (1<<5)
156#define TCTL_TEN (1<<0)
157
158#endif
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h
index 0b7b34603f1c..0dca11ce21fc 100644
--- a/include/asm-arm/arch-ns9xxx/hardware.h
+++ b/include/asm-arm/arch-ns9xxx/hardware.h
@@ -66,13 +66,13 @@
66 __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) 66 __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
67 67
68# define REGGETIM_IDX(var, reg, field, idx) \ 68# define REGGETIM_IDX(var, reg, field, idx) \
69 __REGGET(var, reg ## _ ## field((idx))) / \ 69 __REGGET(var, reg ## _ ## field((idx))) / \
70 __REGSHIFT(reg ## _ ## field((idx))) 70 __REGSHIFT(reg ## _ ## field((idx)))
71 71
72#else 72#else
73 73
74# define __REG(x) io_p2v(x) 74# define __REG(x) io_p2v(x)
75# define __REG2(x, y) io_p2v((x) + (y)) 75# define __REG2(x, y) io_p2v((x) + 4 * (y))
76 76
77#endif 77#endif
78 78
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h
index e9c65ce3cb12..c7db9004ec31 100644
--- a/include/asm-arm/arch-omap/board-2430sdp.h
+++ b/include/asm-arm/arch-omap/board-2430sdp.h
@@ -36,9 +36,4 @@
36 36
37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ 37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
38 38
39/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
40#define IH_TWL4030_BASE IH_BOARD_BASE
41#define IH_TWL4030_END (IH_TWL4030_BASE+8)
42#define NR_IRQS (IH_TWL4030_END)
43
44#endif /* __ASM_ARCH_OMAP_2430SDP_H */ 39#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index 0f6404435ea8..c5d0f32a40ac 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,12 +30,6 @@
30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ 30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
31#define OMAP1710_ETHR_START 0x04000300 31#define OMAP1710_ETHR_START 0x04000300
32 32
33#define MAXIRQNUM (IH_BOARD_BASE)
34#define MAXFIQNUM MAXIRQNUM
35#define MAXSWINUM MAXIRQNUM
36
37#define NR_IRQS (MAXIRQNUM + 1)
38
39extern void h3_mmc_init(void); 33extern void h3_mmc_init(void);
40extern void h3_mmc_slot_cover_handler(void *arg, int state); 34extern void h3_mmc_slot_cover_handler(void *arg, int state);
41 35
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 56d2c98e143c..9ca03dec9d36 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -36,9 +36,6 @@
36#define OMAP1510P1_EMIFS_PRI_VALUE 0x00 36#define OMAP1510P1_EMIFS_PRI_VALUE 0x00
37#define OMAP1510P1_EMIFF_PRI_VALUE 0x00 37#define OMAP1510P1_EMIFF_PRI_VALUE 0x00
38 38
39#define NR_FPGA_IRQS 24
40#define NR_IRQS (IH_BOARD_BASE + NR_FPGA_IRQS)
41
42#ifndef __ASSEMBLY__ 39#ifndef __ASSEMBLY__
43void fpga_write(unsigned char val, int reg); 40void fpga_write(unsigned char val, int reg);
44unsigned char fpga_read(int reg); 41unsigned char fpga_read(int reg);
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
index eb74420cb439..d7429cb0f726 100644
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -36,10 +36,4 @@
36#define OMAP_SDRAM_DEVICE D256M_1X16_4B 36#define OMAP_SDRAM_DEVICE D256M_1X16_4B
37#endif 37#endif
38 38
39#define MAXIRQNUM IH_BOARD_BASE
40#define MAXFIQNUM MAXIRQNUM
41#define MAXSWINUM MAXIRQNUM
42
43#define NR_IRQS (MAXIRQNUM + 1)
44
45#endif 39#endif
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index 12a5e4de9518..4c7b3514f71a 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -33,12 +33,24 @@ struct dpll_data {
33 void __iomem *mult_div1_reg; 33 void __iomem *mult_div1_reg;
34 u32 mult_mask; 34 u32 mult_mask;
35 u32 div1_mask; 35 u32 div1_mask;
36 u16 last_rounded_m;
37 u8 last_rounded_n;
38 unsigned long last_rounded_rate;
39 unsigned int rate_tolerance;
40 u16 max_multiplier;
41 u8 max_divider;
42 u32 max_tolerance;
36# if defined(CONFIG_ARCH_OMAP3) 43# if defined(CONFIG_ARCH_OMAP3)
44 u8 modes;
37 void __iomem *control_reg; 45 void __iomem *control_reg;
38 u32 enable_mask; 46 u32 enable_mask;
39 u8 auto_recal_bit; 47 u8 auto_recal_bit;
40 u8 recal_en_bit; 48 u8 recal_en_bit;
41 u8 recal_st_bit; 49 u8 recal_st_bit;
50 void __iomem *autoidle_reg;
51 u32 autoidle_mask;
52 void __iomem *idlest_reg;
53 u8 idlest_bit;
42# endif 54# endif
43}; 55};
44 56
@@ -66,11 +78,14 @@ struct clk {
66 void __iomem *clksel_reg; 78 void __iomem *clksel_reg;
67 u32 clksel_mask; 79 u32 clksel_mask;
68 const struct clksel *clksel; 80 const struct clksel *clksel;
69 const struct dpll_data *dpll_data; 81 struct dpll_data *dpll_data;
70#else 82#else
71 __u8 rate_offset; 83 __u8 rate_offset;
72 __u8 src_offset; 84 __u8 src_offset;
73#endif 85#endif
86#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
87 struct dentry *dent; /* For visible tree hierarchy */
88#endif
74}; 89};
75 90
76struct cpufreq_frequency_table; 91struct cpufreq_frequency_table;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 36a3b62d4d8d..8ac03071f60c 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -47,8 +47,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
47} 47}
48#endif 48#endif
49 49
50/* IO bases for various OMAP processors */
51struct omap_globals {
52 void __iomem *tap; /* Control module ID code */
53 void __iomem *sdrc; /* SDRAM Controller */
54 void __iomem *sms; /* SDRAM Memory Scheduler */
55 void __iomem *ctrl; /* System Control Module */
56 void __iomem *prm; /* Power and Reset Management */
57 void __iomem *cm; /* Clock Management */
58};
59
50void omap2_set_globals_242x(void); 60void omap2_set_globals_242x(void);
51void omap2_set_globals_243x(void); 61void omap2_set_globals_243x(void);
52void omap2_set_globals_343x(void); 62void omap2_set_globals_343x(void);
53 63
64/* These get called from omap2_set_globals_xxxx(), do not call these */
65void omap2_set_globals_memory(struct omap_globals *);
66void omap2_set_globals_control(struct omap_globals *);
67void omap2_set_globals_prcm(struct omap_globals *);
68
54#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 69#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
index 59c0686f8be7..987553e3eeb9 100644
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -167,8 +167,7 @@
167 167
168#ifndef __ASSEMBLY__ 168#ifndef __ASSEMBLY__
169#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 169#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
170extern void omap_ctrl_base_set(u32 base); 170extern void __iomem *omap_ctrl_base_get(void);
171extern u32 omap_ctrl_base_get(void);
172extern u8 omap_ctrl_readb(u16 offset); 171extern u8 omap_ctrl_readb(u16 offset);
173extern u16 omap_ctrl_readw(u16 offset); 172extern u16 omap_ctrl_readw(u16 offset);
174extern u32 omap_ctrl_readl(u16 offset); 173extern u32 omap_ctrl_readl(u16 offset);
@@ -176,7 +175,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset);
176extern void omap_ctrl_writew(u16 val, u16 offset); 175extern void omap_ctrl_writew(u16 val, u16 offset);
177extern void omap_ctrl_writel(u32 val, u16 offset); 176extern void omap_ctrl_writel(u32 val, u16 offset);
178#else 177#else
179#define omap_ctrl_base_set(x) WARN_ON(1)
180#define omap_ctrl_base_get() 0 178#define omap_ctrl_base_get() 0
181#define omap_ctrl_readb(x) 0 179#define omap_ctrl_readb(x) 0
182#define omap_ctrl_readw(x) 0 180#define omap_ctrl_readw(x) 0
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index e8a4cf52778b..52db09f83281 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * OMAP cpu type detection 4 * OMAP cpu type detection
5 * 5 *
6 * Copyright (C) 2004 Nokia Corporation 6 * Copyright (C) 2004, 2008 Nokia Corporation
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
@@ -26,6 +26,12 @@
26#ifndef __ASM_ARCH_OMAP_CPU_H 26#ifndef __ASM_ARCH_OMAP_CPU_H
27#define __ASM_ARCH_OMAP_CPU_H 27#define __ASM_ARCH_OMAP_CPU_H
28 28
29struct omap_chip_id {
30 u8 oc;
31};
32
33#define OMAP_CHIP_INIT(x) { .oc = x }
34
29extern unsigned int system_rev; 35extern unsigned int system_rev;
30 36
31#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f) 37#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f)
@@ -345,6 +351,33 @@ IS_OMAP_TYPE(3430, 0x3430)
345#define OMAP2430_REV_ES1_0 0x24300000 351#define OMAP2430_REV_ES1_0 0x24300000
346#define OMAP3430_REV_ES1_0 0x34300000 352#define OMAP3430_REV_ES1_0 0x34300000
347#define OMAP3430_REV_ES2_0 0x34301000 353#define OMAP3430_REV_ES2_0 0x34301000
354#define OMAP3430_REV_ES2_1 0x34302000
355#define OMAP3430_REV_ES2_2 0x34303000
356
357/*
358 * omap_chip bits
359 *
360 * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
361 * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
362 * something that is only valid on that particular ES revision.
363 *
364 * These bits may be ORed together to indicate structures that are
365 * available on multiple chip types.
366 *
367 * To test whether a particular structure matches the current OMAP chip type,
368 * use omap_chip_is().
369 *
370 */
371#define CHIP_IS_OMAP2420 (1 << 0)
372#define CHIP_IS_OMAP2430 (1 << 1)
373#define CHIP_IS_OMAP3430 (1 << 2)
374#define CHIP_IS_OMAP3430ES1 (1 << 3)
375#define CHIP_IS_OMAP3430ES2 (1 << 4)
376
377#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
378
379int omap_chip_is(struct omap_chip_id oci);
380
348 381
349/* 382/*
350 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD 383 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
@@ -362,6 +395,8 @@ IS_OMAP_TYPE(3430, 0x3430)
362#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP) 395#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
363#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD) 396#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
364 397
365#endif 398void omap2_check_revision(void);
399
400#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
366 401
367#endif 402#endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 24acf090030d..f4dcb9587869 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,108 +22,128 @@
22#define __ASM_ARCH_DMA_H 22#define __ASM_ARCH_DMA_H
23 23
24/* Hardware registers for omap1 */ 24/* Hardware registers for omap1 */
25#define OMAP_DMA_BASE (0xfffed800) 25#define OMAP1_DMA_BASE (0xfffed800)
26#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) 26
27#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) 27#define OMAP1_DMA_GCR 0x400
28#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) 28#define OMAP1_DMA_GSCR 0x404
29#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) 29#define OMAP1_DMA_GRST 0x408
30#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) 30#define OMAP1_DMA_HW_ID 0x442
31#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) 31#define OMAP1_DMA_PCH2_ID 0x444
32#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) 32#define OMAP1_DMA_PCH0_ID 0x446
33#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) 33#define OMAP1_DMA_PCH1_ID 0x448
34#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) 34#define OMAP1_DMA_PCHG_ID 0x44a
35#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) 35#define OMAP1_DMA_PCHD_ID 0x44c
36#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) 36#define OMAP1_DMA_CAPS_0_U 0x44e
37#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) 37#define OMAP1_DMA_CAPS_0_L 0x450
38#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) 38#define OMAP1_DMA_CAPS_1_U 0x452
39#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) 39#define OMAP1_DMA_CAPS_1_L 0x454
40#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) 40#define OMAP1_DMA_CAPS_2 0x456
41#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) 41#define OMAP1_DMA_CAPS_3 0x458
42#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) 42#define OMAP1_DMA_CAPS_4 0x45a
43#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) 43#define OMAP1_DMA_PCH2_SR 0x460
44#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) 44#define OMAP1_DMA_PCH0_SR 0x480
45#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) 45#define OMAP1_DMA_PCH1_SR 0x482
46 46#define OMAP1_DMA_PCHD_SR 0x4c0
47/* Hardware registers for omap2 */ 47
48#if defined(CONFIG_ARCH_OMAP3) 48/* Hardware registers for omap2 and omap3 */
49#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000) 49#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
50#else /* CONFIG_ARCH_OMAP2 */ 50#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
51#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000) 51
52#endif 52#define OMAP_DMA4_REVISION 0x00
53 53#define OMAP_DMA4_GCR 0x78
54#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00) 54#define OMAP_DMA4_IRQSTATUS_L0 0x08
55#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78) 55#define OMAP_DMA4_IRQSTATUS_L1 0x0c
56#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08) 56#define OMAP_DMA4_IRQSTATUS_L2 0x10
57#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c) 57#define OMAP_DMA4_IRQSTATUS_L3 0x14
58#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10) 58#define OMAP_DMA4_IRQENABLE_L0 0x18
59#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14) 59#define OMAP_DMA4_IRQENABLE_L1 0x1c
60#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18) 60#define OMAP_DMA4_IRQENABLE_L2 0x20
61#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c) 61#define OMAP_DMA4_IRQENABLE_L3 0x24
62#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20) 62#define OMAP_DMA4_SYSSTATUS 0x28
63#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24) 63#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
64#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28) 64#define OMAP_DMA4_CAPS_0 0x64
65#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c) 65#define OMAP_DMA4_CAPS_2 0x6c
66#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64) 66#define OMAP_DMA4_CAPS_3 0x70
67#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c) 67#define OMAP_DMA4_CAPS_4 0x74
68#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) 68
69#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) 69#define OMAP1_LOGICAL_DMA_CH_COUNT 17
70 70#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
71#ifdef CONFIG_ARCH_OMAP1
72
73#define OMAP_LOGICAL_DMA_CH_COUNT 17
74 71
75/* Common channel specific registers for omap1 */ 72/* Common channel specific registers for omap1 */
76#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00) 73#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
77#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02) 74#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
78#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04) 75#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
79#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06) 76#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
80#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10) 77#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
81#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12) 78#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
82#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14) 79#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
83#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16) 80#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
84#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18) 81#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
85#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a) 82#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
86#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c) 83#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
87#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e) 84#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
88#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28) 85#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
89 86#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
90#else 87#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
91
92#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
93 88
94/* Common channel specific registers for omap2 */ 89/* Common channel specific registers for omap2 */
95#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) 90#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
96#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) 91#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
97#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88) 92#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
98#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c) 93#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
99#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90) 94#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
100#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94) 95#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
101#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98) 96#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
102#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4) 97#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
103#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8) 98#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
104#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac) 99#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
105#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0) 100#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
106#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4) 101#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
107#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8) 102#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
108 103#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
109#endif
110 104
111/* Channel specific registers only on omap1 */ 105/* Channel specific registers only on omap1 */
112#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08) 106#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
113#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a) 107#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
114#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c) 108#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
115#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e) 109#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
116#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20) 110#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
117#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24) 111#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
118#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22) 112#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
119#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) 113#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
114#define OMAP1_DMA_CCEN(n) 0
115#define OMAP1_DMA_CCFN(n) 0
120 116
121/* Channel specific registers only on omap2 */ 117/* Channel specific registers only on omap2 */
122#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c) 118#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
123#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0) 119#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
124#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc) 120#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
125#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0) 121#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
126#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4) 122#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
123
124/* Dummy defines to keep multi-omap compiles happy */
125#define OMAP1_DMA_REVISION 0
126#define OMAP1_DMA_IRQSTATUS_L0 0
127#define OMAP1_DMA_IRQENABLE_L0 0
128#define OMAP1_DMA_OCP_SYSCONFIG 0
129#define OMAP_DMA4_HW_ID 0
130#define OMAP_DMA4_CAPS_0_L 0
131#define OMAP_DMA4_CAPS_0_U 0
132#define OMAP_DMA4_CAPS_1_L 0
133#define OMAP_DMA4_CAPS_1_U 0
134#define OMAP_DMA4_GSCR 0
135#define OMAP_DMA4_CPC(n) 0
136
137#define OMAP_DMA4_LCH_CTRL(n) 0
138#define OMAP_DMA4_COLOR_L(n) 0
139#define OMAP_DMA4_COLOR_U(n) 0
140#define OMAP_DMA4_CCR2(n) 0
141#define OMAP1_DMA_CSSA(n) 0
142#define OMAP1_DMA_CDSA(n) 0
143#define OMAP_DMA4_CSSA_L(n) 0
144#define OMAP_DMA4_CSSA_U(n) 0
145#define OMAP_DMA4_CDSA_L(n) 0
146#define OMAP_DMA4_CDSA_U(n) 0
127 147
128/*----------------------------------------------------------------------------*/ 148/*----------------------------------------------------------------------------*/
129 149
@@ -196,63 +216,98 @@
196#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ 216#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
197#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ 217#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
198#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ 218#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
199#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */ 219#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
220#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
200#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ 221#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
201#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ 222#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
202#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ 223#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
203#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ 224#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
204#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ 225#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
205#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ 226#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
206#define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ 227#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
207#define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ 228#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
208#define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ 229#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
209#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ 230#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
210#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ 231#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
211#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ 232#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
212#define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ 233#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
213#define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ 234#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
214#define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ 235#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
215#define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ 236#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
216#define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ 237#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
217#define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ 238#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
218#define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ 239#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
240#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
241#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
242#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
243#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
244#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
245#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
246#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
247#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
248#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
249#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
250#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
251#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
252#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
253#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
254#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
255#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
219#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ 256#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
220#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ 257#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
221#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ 258#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
222#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ 259#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
223#define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */ 260#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
224#define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */ 261#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
225#define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */ 262#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
226#define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */ 263#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
227#define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */ 264#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
228#define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */ 265#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
229#define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */ 266#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
230#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */ 267#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
231#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */ 268#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
232#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */ 269#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
233#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */ 270#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
234#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */ 271#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
235#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */ 272#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
236#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */ 273#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
237#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */ 274#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
238#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */ 275#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
239 276#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
240#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */ 277#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
241#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */ 278#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
242#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */ 279#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
243#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */ 280#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
244#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */ 281#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
245#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */ 282#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
246#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */ 283#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
247#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */ 284#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
248#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */ 285#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
249#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */ 286#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
250#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */ 287#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
251#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */ 288#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
252#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ 289#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
253#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ 290#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
254#define OMAP24XX_DMA_MS 63 /* SDMA_62 */ 291#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
255#define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ 292#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
293#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
294#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
295#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
296#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
297#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
298#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
299#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
300#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
301#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
302#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
303#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
304#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
305#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
306#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
307#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
308#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
309#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
310#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
256 311
257/*----------------------------------------------------------------------------*/ 312/*----------------------------------------------------------------------------*/
258 313
@@ -358,6 +413,11 @@ enum omap_dma_burst_mode {
358 OMAP_DMA_DATA_BURST_16, 413 OMAP_DMA_DATA_BURST_16,
359}; 414};
360 415
416enum end_type {
417 OMAP_DMA_LITTLE_ENDIAN = 0,
418 OMAP_DMA_BIG_ENDIAN
419};
420
361enum omap_dma_color_mode { 421enum omap_dma_color_mode {
362 OMAP_DMA_COLOR_DIS = 0, 422 OMAP_DMA_COLOR_DIS = 0,
363 OMAP_DMA_CONSTANT_FILL, 423 OMAP_DMA_CONSTANT_FILL,
@@ -370,24 +430,34 @@ enum omap_dma_write_mode {
370 OMAP_DMA_WRITE_LAST_NON_POSTED 430 OMAP_DMA_WRITE_LAST_NON_POSTED
371}; 431};
372 432
433enum omap_dma_channel_mode {
434 OMAP_DMA_LCH_2D = 0,
435 OMAP_DMA_LCH_G,
436 OMAP_DMA_LCH_P,
437 OMAP_DMA_LCH_PD
438};
439
373struct omap_dma_channel_params { 440struct omap_dma_channel_params {
374 int data_type; /* data type 8,16,32 */ 441 int data_type; /* data type 8,16,32 */
375 int elem_count; /* number of elements in a frame */ 442 int elem_count; /* number of elements in a frame */
376 int frame_count; /* number of frames in a element */ 443 int frame_count; /* number of frames in a element */
377 444
378 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ 445 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
379 int src_amode; /* constant , post increment, indexed , double indexed */ 446 int src_amode; /* constant, post increment, indexed,
447 double indexed */
380 unsigned long src_start; /* source address : physical */ 448 unsigned long src_start; /* source address : physical */
381 int src_ei; /* source element index */ 449 int src_ei; /* source element index */
382 int src_fi; /* source frame index */ 450 int src_fi; /* source frame index */
383 451
384 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ 452 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
385 int dst_amode; /* constant , post increment, indexed , double indexed */ 453 int dst_amode; /* constant, post increment, indexed,
454 double indexed */
386 unsigned long dst_start; /* source address : physical */ 455 unsigned long dst_start; /* source address : physical */
387 int dst_ei; /* source element index */ 456 int dst_ei; /* source element index */
388 int dst_fi; /* source frame index */ 457 int dst_fi; /* source frame index */
389 458
390 int trigger; /* trigger attached if the channel is synchronized */ 459 int trigger; /* trigger attached if the channel is
460 synchronized */
391 int sync_mode; /* sycn on element, frame , block or packet */ 461 int sync_mode; /* sycn on element, frame , block or packet */
392 int src_or_dst_synch; /* source synch(1) or destination synch(0) */ 462 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
393 463
@@ -404,8 +474,8 @@ struct omap_dma_channel_params {
404 474
405extern void omap_set_dma_priority(int lch, int dst_port, int priority); 475extern void omap_set_dma_priority(int lch, int dst_port, int priority);
406extern int omap_request_dma(int dev_id, const char *dev_name, 476extern int omap_request_dma(int dev_id, const char *dev_name,
407 void (* callback)(int lch, u16 ch_status, void *data), 477 void (*callback)(int lch, u16 ch_status, void *data),
408 void *data, int *dma_ch); 478 void *data, int *dma_ch);
409extern void omap_enable_dma_irq(int ch, u16 irq_bits); 479extern void omap_enable_dma_irq(int ch, u16 irq_bits);
410extern void omap_disable_dma_irq(int ch, u16 irq_bits); 480extern void omap_disable_dma_irq(int ch, u16 irq_bits);
411extern void omap_free_dma(int ch); 481extern void omap_free_dma(int ch);
@@ -418,6 +488,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
418extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, 488extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
419 u32 color); 489 u32 color);
420extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); 490extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
491extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
421 492
422extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, 493extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
423 unsigned long src_start, 494 unsigned long src_start,
@@ -436,23 +507,26 @@ extern void omap_set_dma_dest_burst_mode(int lch,
436 enum omap_dma_burst_mode burst_mode); 507 enum omap_dma_burst_mode burst_mode);
437 508
438extern void omap_set_dma_params(int lch, 509extern void omap_set_dma_params(int lch,
439 struct omap_dma_channel_params * params); 510 struct omap_dma_channel_params *params);
440 511
441extern void omap_dma_link_lch (int lch_head, int lch_queue); 512extern void omap_dma_link_lch(int lch_head, int lch_queue);
442extern void omap_dma_unlink_lch (int lch_head, int lch_queue); 513extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
443 514
444extern int omap_set_dma_callback(int lch, 515extern int omap_set_dma_callback(int lch,
445 void (* callback)(int lch, u16 ch_status, void *data), 516 void (*callback)(int lch, u16 ch_status, void *data),
446 void *data); 517 void *data);
447extern dma_addr_t omap_get_dma_src_pos(int lch); 518extern dma_addr_t omap_get_dma_src_pos(int lch);
448extern dma_addr_t omap_get_dma_dst_pos(int lch); 519extern dma_addr_t omap_get_dma_dst_pos(int lch);
449extern int omap_get_dma_src_addr_counter(int lch);
450extern void omap_clear_dma(int lch); 520extern void omap_clear_dma(int lch);
521extern int omap_get_dma_active_status(int lch);
451extern int omap_dma_running(void); 522extern int omap_dma_running(void);
452extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, 523extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
453 int tparams); 524 int tparams);
454extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, 525extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
455 unsigned char write_prio); 526 unsigned char write_prio);
527extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
528extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
529extern int omap_get_dma_index(int lch, int *ei, int *fi);
456 530
457/* Chaining APIs */ 531/* Chaining APIs */
458#ifndef CONFIG_ARCH_OMAP1 532#ifndef CONFIG_ARCH_OMAP1
@@ -478,7 +552,7 @@ extern int omap_dma_chain_status(int chain_id);
478#endif 552#endif
479 553
480/* LCD DMA functions */ 554/* LCD DMA functions */
481extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 555extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
482 void *data); 556 void *data);
483extern void omap_free_lcd_dma(void); 557extern void omap_free_lcd_dma(void);
484extern void omap_setup_lcd_dma(void); 558extern void omap_setup_lcd_dma(void);
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
index fefb276ed402..02b29e8437ae 100644
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -66,6 +66,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer);
66 66
67void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); 67void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); 68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
69void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
69void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); 70void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
70void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); 71void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
71void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); 72void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
index 6a883e0bdbb8..f420881d2a3b 100644
--- a/include/asm-arm/arch-omap/fpga.h
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -169,30 +169,29 @@ struct h2p2_dbg_fpga {
169#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) 169#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
170 170
171/* IRQ Numbers for interrupts muxed through the FPGA */ 171/* IRQ Numbers for interrupts muxed through the FPGA */
172#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE 172#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
173#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0) 173#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
174#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1) 174#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
175#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2) 175#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
176#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3) 176#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
177#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4) 177#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
178#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5) 178#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
179#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6) 179#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
180#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7) 180#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
181#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8) 181#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
182#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9) 182#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
183#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10) 183#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
184#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11) 184#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
185#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12) 185#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
186#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13) 186#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
187#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14) 187#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
188#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15) 188#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
189#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16) 189#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
190#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17) 190#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
191#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18) 191#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
192#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19) 192#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
193#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20) 193#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
194#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21) 194#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
195#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22) 195#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
196#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23)
197 196
198#endif 197#endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 91d85b3417b7..45fdfccbd5d4 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -284,6 +284,7 @@
284#include "omap1510.h" 284#include "omap1510.h"
285#include "omap24xx.h" 285#include "omap24xx.h"
286#include "omap16xx.h" 286#include "omap16xx.h"
287#include "omap34xx.h"
287 288
288#ifndef __ASSEMBLER__ 289#ifndef __ASSEMBLER__
289 290
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 160578e1f557..0b13557fd30b 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -60,6 +60,7 @@
60#define IO_SIZE 0x40000 60#define IO_SIZE 0x40000
61#define IO_VIRT (IO_PHYS - IO_OFFSET) 61#define IO_VIRT (IO_PHYS - IO_OFFSET)
62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) 62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define io_p2v(pa) ((pa) - IO_OFFSET) 64#define io_p2v(pa) ((pa) - IO_OFFSET)
64#define io_v2p(va) ((va) + IO_OFFSET) 65#define io_v2p(va) ((va) + IO_OFFSET)
65 66
@@ -91,6 +92,7 @@
91 92
92#define IO_OFFSET 0x90000000 93#define IO_OFFSET 0x90000000
93#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 94#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
95#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
94#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 96#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
95#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ 97#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
96 98
@@ -148,6 +150,7 @@
148 150
149#define IO_OFFSET 0x90000000 151#define IO_OFFSET 0x90000000
150#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 152#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
153#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
151#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 154#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
152#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ 155#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
153 156
@@ -183,35 +186,12 @@
183#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) 186#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
184#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) 187#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
185 188
186/* 16 bit uses LDRH/STRH, base +/- offset_8 */
187typedef struct { volatile u16 offset[256]; } __regbase16;
188#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \
189 ->offset[((vaddr)&0xff)>>1]
190#define __REG16(paddr) __REGV16(io_p2v(paddr))
191
192/* 8/32 bit uses LDR/STR, base +/- offset_12 */
193typedef struct { volatile u8 offset[4096]; } __regbase8;
194#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \
195 ->offset[((vaddr)&4095)>>0]
196#define __REG8(paddr) __REGV8(io_p2v(paddr))
197
198typedef struct { volatile u32 offset[4096]; } __regbase32;
199#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \
200 ->offset[((vaddr)&4095)>>2]
201#define __REG32(paddr) __REGV32(io_p2v(paddr))
202
203extern void omap1_map_common_io(void); 189extern void omap1_map_common_io(void);
204extern void omap1_init_common_hw(void); 190extern void omap1_init_common_hw(void);
205 191
206extern void omap2_map_common_io(void); 192extern void omap2_map_common_io(void);
207extern void omap2_init_common_hw(void); 193extern void omap2_init_common_hw(void);
208 194
209#else
210
211#define __REG8(paddr) io_p2v(paddr)
212#define __REG16(paddr) io_p2v(paddr)
213#define __REG32(paddr) io_p2v(paddr)
214
215#endif 195#endif
216 196
217#endif 197#endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 87973654e625..7464c694859b 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -285,7 +285,41 @@
285#define OMAP_MAX_GPIO_LINES 192 285#define OMAP_MAX_GPIO_LINES 192
286#define IH_GPIO_BASE (128 + IH2_BASE) 286#define IH_GPIO_BASE (128 + IH2_BASE)
287#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) 287#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
288#define IH_BOARD_BASE (16 + IH_MPUIO_BASE) 288#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
289
290/* External FPGA handles interrupts on Innovator boards */
291#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
292#ifdef CONFIG_MACH_OMAP_INNOVATOR
293#define OMAP_FPGA_NR_IRQS 24
294#else
295#define OMAP_FPGA_NR_IRQS 0
296#endif
297#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
298
299/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
300#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
301#ifdef CONFIG_TWL4030_CORE
302#define TWL4030_BASE_NR_IRQS 8
303#define TWL4030_PWR_NR_IRQS 8
304#else
305#define TWL4030_BASE_NR_IRQS 0
306#define TWL4030_PWR_NR_IRQS 0
307#endif
308#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
309#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
310#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
311
312/* External TWL4030 gpio interrupts are optional */
313#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
314#ifdef CONFIG_TWL4030_GPIO
315#define TWL4030_GPIO_NR_IRQS 18
316#else
317#define TWL4030_GPIO_NR_IRQS 0
318#endif
319#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
320
321/* Total number of interrupts depends on the enabled blocks above */
322#define NR_IRQS TWL4030_GPIO_IRQ_END
289 323
290#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 324#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
291 325
@@ -293,14 +327,6 @@
293extern void omap_init_irq(void); 327extern void omap_init_irq(void);
294#endif 328#endif
295 329
296/*
297 * The definition of NR_IRQS is in board-specific header file, which is
298 * included via hardware.h
299 */
300#include <asm/hardware.h> 330#include <asm/hardware.h>
301 331
302#ifndef NR_IRQS
303#define NR_IRQS IH_BOARD_BASE
304#endif
305
306#endif 332#endif
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
index c7a0cc1c4e93..26c78f67dc8e 100644
--- a/include/asm-arm/arch-omap/mcbsp.h
+++ b/include/asm-arm/arch-omap/mcbsp.h
@@ -24,7 +24,11 @@
24#ifndef __ASM_ARCH_OMAP_MCBSP_H 24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H 25#define __ASM_ARCH_OMAP_MCBSP_H
26 26
27#include <linux/completion.h>
28#include <linux/spinlock.h>
29
27#include <asm/hardware.h> 30#include <asm/hardware.h>
31#include <asm/arch/clock.h>
28 32
29#define OMAP730_MCBSP1_BASE 0xfffb1000 33#define OMAP730_MCBSP1_BASE 0xfffb1000
30#define OMAP730_MCBSP2_BASE 0xfffb1800 34#define OMAP730_MCBSP2_BASE 0xfffb1800
@@ -40,6 +44,9 @@
40#define OMAP24XX_MCBSP1_BASE 0x48074000 44#define OMAP24XX_MCBSP1_BASE 0x48074000
41#define OMAP24XX_MCBSP2_BASE 0x48076000 45#define OMAP24XX_MCBSP2_BASE 0x48076000
42 46
47#define OMAP34XX_MCBSP1_BASE 0x48074000
48#define OMAP34XX_MCBSP2_BASE 0x49022000
49
43#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 50#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
44 51
45#define OMAP_MCBSP_REG_DRR2 0x00 52#define OMAP_MCBSP_REG_DRR2 0x00
@@ -74,7 +81,8 @@
74#define OMAP_MCBSP_REG_XCERG 0x3A 81#define OMAP_MCBSP_REG_XCERG 0x3A
75#define OMAP_MCBSP_REG_XCERH 0x3C 82#define OMAP_MCBSP_REG_XCERH 0x3C
76 83
77#define OMAP_MAX_MCBSP_COUNT 3 84#define OMAP_MAX_MCBSP_COUNT 3
85#define MAX_MCBSP_CLOCKS 3
78 86
79#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) 87#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
80#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) 88#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
@@ -117,7 +125,8 @@
117#define OMAP_MCBSP_REG_XCERG 0x74 125#define OMAP_MCBSP_REG_XCERG 0x74
118#define OMAP_MCBSP_REG_XCERH 0x78 126#define OMAP_MCBSP_REG_XCERH 0x78
119 127
120#define OMAP_MAX_MCBSP_COUNT 2 128#define OMAP_MAX_MCBSP_COUNT 2
129#define MAX_MCBSP_CLOCKS 2
121 130
122#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) 131#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
123#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) 132#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -298,6 +307,55 @@ struct omap_mcbsp_spi_cfg {
298 omap_mcbsp_word_length word_length; 307 omap_mcbsp_word_length word_length;
299}; 308};
300 309
310/* Platform specific configuration */
311struct omap_mcbsp_ops {
312 void (*request)(unsigned int);
313 void (*free)(unsigned int);
314 int (*check)(unsigned int);
315};
316
317struct omap_mcbsp_platform_data {
318 u32 virt_base;
319 u8 dma_rx_sync, dma_tx_sync;
320 u16 rx_irq, tx_irq;
321 struct omap_mcbsp_ops *ops;
322 char const *clk_name;
323};
324
325struct omap_mcbsp {
326 struct device *dev;
327 u32 io_base;
328 u8 id;
329 u8 free;
330 omap_mcbsp_word_length rx_word_length;
331 omap_mcbsp_word_length tx_word_length;
332
333 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
334 /* IRQ based TX/RX */
335 int rx_irq;
336 int tx_irq;
337
338 /* DMA stuff */
339 u8 dma_rx_sync;
340 short dma_rx_lch;
341 u8 dma_tx_sync;
342 short dma_tx_lch;
343
344 /* Completion queues */
345 struct completion tx_irq_completion;
346 struct completion rx_irq_completion;
347 struct completion tx_dma_completion;
348 struct completion rx_dma_completion;
349
350 /* Protect the field .free, while checking if the mcbsp is in use */
351 spinlock_t lock;
352 struct omap_mcbsp_platform_data *pdata;
353 struct clk *clk;
354};
355
356int omap_mcbsp_init(void);
357void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
358 int size);
301void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 359void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
302int omap_mcbsp_request(unsigned int id); 360int omap_mcbsp_request(unsigned int id);
303void omap_mcbsp_free(unsigned int id); 361void omap_mcbsp_free(unsigned int id);
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
new file mode 100644
index 000000000000..aa30c6d10abd
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap34xx.h
@@ -0,0 +1,72 @@
1/*
2 * include/asm-arm/arch-omap/omap34xx.h
3 *
4 * This file contains the processor specific definitions of the TI OMAP34XX.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 * Copyright (C) 2007 Nokia Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef __ASM_ARCH_OMAP34XX_H
25#define __ASM_ARCH_OMAP34XX_H
26
27/*
28 * Please place only base defines here and put the rest in device
29 * specific headers.
30 */
31
32#define L4_34XX_BASE 0x48000000
33#define L4_WK_34XX_BASE 0x48300000
34#define L4_WK_OMAP_BASE L4_WK_34XX_BASE
35#define L4_PER_34XX_BASE 0x49000000
36#define L4_PER_OMAP_BASE L4_PER_34XX_BASE
37#define L4_EMU_34XX_BASE 0x54000000
38#define L4_EMU_BASE L4_EMU_34XX_BASE
39#define L3_34XX_BASE 0x68000000
40#define L3_OMAP_BASE L3_34XX_BASE
41
42#define OMAP3430_32KSYNCT_BASE 0x48320000
43#define OMAP3430_CM_BASE 0x48004800
44#define OMAP3430_PRM_BASE 0x48306800
45#define OMAP343X_SMS_BASE 0x6C000000
46#define OMAP343X_SDRC_BASE 0x6D000000
47#define OMAP34XX_GPMC_BASE 0x6E000000
48#define OMAP343X_SCM_BASE 0x48002000
49#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
50
51#define OMAP34XX_IC_BASE 0x48200000
52#define OMAP34XX_IVA_INTC_BASE 0x40000000
53#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
54#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
55#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
56
57
58#if defined(CONFIG_ARCH_OMAP3430)
59
60#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE
61#define OMAP2_CM_BASE OMAP3430_CM_BASE
62#define OMAP2_PRM_BASE OMAP3430_PRM_BASE
63#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
64
65#endif
66
67#define OMAP34XX_DSP_BASE 0x58000000
68#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0)
69#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000)
70#define OMAP34XX_DSP_MMU_BASE (OMAP34XX_DSP_BASE + 0x2000000)
71#endif /* __ASM_ARCH_OMAP34XX_H */
72
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index bb9bb3fd532f..be59f4a9828b 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -11,6 +11,7 @@
11#ifndef __ARCH_ARM_OMAP_SRAM_H 11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H 12#define __ARCH_ARM_OMAP_SRAM_H
13 13
14extern int __init omap_sram_init(void);
14extern void * omap_sram_push(void * start, unsigned long size); 15extern void * omap_sram_push(void * start, unsigned long size);
15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); 16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
16 17
@@ -21,17 +22,35 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
22 23
23/* Do not use these */ 24/* Do not use these */
24extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); 25extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
25extern unsigned long sram_reprogram_clock_sz; 26extern unsigned long omap1_sram_reprogram_clock_sz;
26 27
27extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 28extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
28 u32 base_cs, u32 force_unlock); 29extern unsigned long omap24xx_sram_reprogram_clock_sz;
29extern unsigned long sram_ddr_init_sz;
30 30
31extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 31extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
32extern unsigned long sram_set_prcm_sz; 32 u32 base_cs, u32 force_unlock);
33extern unsigned long omap242x_sram_ddr_init_sz;
33 34
34extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type); 35extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
35extern unsigned long sram_reprogram_sdrc_sz; 36 int bypass);
37extern unsigned long omap242x_sram_set_prcm_sz;
38
39extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
40 u32 mem_type);
41extern unsigned long omap242x_sram_reprogram_sdrc_sz;
42
43
44extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
45 u32 base_cs, u32 force_unlock);
46extern unsigned long omap243x_sram_ddr_init_sz;
47
48extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
49 int bypass);
50extern unsigned long omap243x_sram_set_prcm_sz;
51
52extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
53 u32 mem_type);
54extern unsigned long omap243x_sram_reprogram_sdrc_sz;
36 55
37#endif 56#endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
index 8ded218cbea5..65a9c82d3bf7 100644
--- a/include/asm-arm/arch-omap/tc.h
+++ b/include/asm-arm/arch-omap/tc.h
@@ -75,16 +75,14 @@
75#ifndef __ASSEMBLER__ 75#ifndef __ASSEMBLER__
76 76
77/* EMIF Slow Interface Configuration Register */ 77/* EMIF Slow Interface Configuration Register */
78#define OMAP_EMIFS_CONFIG_REG __REG32(EMIFS_CONFIG)
79
80#define OMAP_EMIFS_CONFIG_FR (1 << 4) 78#define OMAP_EMIFS_CONFIG_FR (1 << 4)
81#define OMAP_EMIFS_CONFIG_PDE (1 << 3) 79#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
82#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) 80#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
83#define OMAP_EMIFS_CONFIG_BM (1 << 1) 81#define OMAP_EMIFS_CONFIG_BM (1 << 1)
84#define OMAP_EMIFS_CONFIG_WP (1 << 0) 82#define OMAP_EMIFS_CONFIG_WP (1 << 0)
85 83
86#define EMIFS_CCS(n) __REG32(EMIFS_CS0_CONFIG + (4 * (n))) 84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
87#define EMIFS_ACS(n) __REG32(EMIFS_ACS0 + (4 * (n))) 85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
88 86
89/* Almost all documentation for chip and board memory maps assumes 87/* Almost all documentation for chip and board memory maps assumes
90 * BM is clear. Most devel boards have a switch to control booting 88 * BM is clear. Most devel boards have a switch to control booting
@@ -93,13 +91,13 @@
93 */ 91 */
94static inline u32 omap_cs0_phys(void) 92static inline u32 omap_cs0_phys(void)
95{ 93{
96 return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) 94 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
97 ? OMAP_CS3_PHYS : 0; 95 ? OMAP_CS3_PHYS : 0;
98} 96}
99 97
100static inline u32 omap_cs3_phys(void) 98static inline u32 omap_cs3_phys(void)
101{ 99{
102 return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) 100 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
103 ? 0 : OMAP_CS3_PHYS; 101 ? 0 : OMAP_CS3_PHYS;
104} 102}
105 103
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 2147d18aaeae..ddf1861e6df9 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -34,11 +34,8 @@
34/* 34/*
35 * OTG and transceiver registers, for OMAPs starting with ARM926 35 * OTG and transceiver registers, for OMAPs starting with ARM926
36 */ 36 */
37#define OTG_REG32(offset) __REG32(OTG_BASE + (offset)) 37#define OTG_REV (OTG_BASE + 0x00)
38#define OTG_REG16(offset) __REG16(OTG_BASE + (offset)) 38#define OTG_SYSCON_1 (OTG_BASE + 0x04)
39
40#define OTG_REV_REG OTG_REG32(0x00)
41#define OTG_SYSCON_1_REG OTG_REG32(0x04)
42# define USB2_TRX_MODE(w) (((w)>>24)&0x07) 39# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
43# define USB1_TRX_MODE(w) (((w)>>20)&0x07) 40# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
44# define USB0_TRX_MODE(w) (((w)>>16)&0x07) 41# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
@@ -47,7 +44,7 @@
47# define DEV_IDLE_EN (1 << 13) 44# define DEV_IDLE_EN (1 << 13)
48# define OTG_RESET_DONE (1 << 2) 45# define OTG_RESET_DONE (1 << 2)
49# define OTG_SOFT_RESET (1 << 1) 46# define OTG_SOFT_RESET (1 << 1)
50#define OTG_SYSCON_2_REG OTG_REG32(0x08) 47#define OTG_SYSCON_2 (OTG_BASE + 0x08)
51# define OTG_EN (1 << 31) 48# define OTG_EN (1 << 31)
52# define USBX_SYNCHRO (1 << 30) 49# define USBX_SYNCHRO (1 << 30)
53# define OTG_MST16 (1 << 29) 50# define OTG_MST16 (1 << 29)
@@ -65,7 +62,7 @@
65# define HMC_TLLSPEED (1 << 7) 62# define HMC_TLLSPEED (1 << 7)
66# define HMC_TLLATTACH (1 << 6) 63# define HMC_TLLATTACH (1 << 6)
67# define OTG_HMC(w) (((w)>>0)&0x3f) 64# define OTG_HMC(w) (((w)>>0)&0x3f)
68#define OTG_CTRL_REG OTG_REG32(0x0c) 65#define OTG_CTRL (OTG_BASE + 0x0c)
69# define OTG_USB2_EN (1 << 29) 66# define OTG_USB2_EN (1 << 29)
70# define OTG_USB2_DP (1 << 28) 67# define OTG_USB2_DP (1 << 28)
71# define OTG_USB2_DM (1 << 27) 68# define OTG_USB2_DM (1 << 27)
@@ -92,7 +89,7 @@
92# define OTG_PD_VBUS (1 << 2) 89# define OTG_PD_VBUS (1 << 2)
93# define OTG_PU_VBUS (1 << 1) 90# define OTG_PU_VBUS (1 << 1)
94# define OTG_PU_ID (1 << 0) 91# define OTG_PU_ID (1 << 0)
95#define OTG_IRQ_EN_REG OTG_REG16(0x10) 92#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
96# define DRIVER_SWITCH (1 << 15) 93# define DRIVER_SWITCH (1 << 15)
97# define A_VBUS_ERR (1 << 13) 94# define A_VBUS_ERR (1 << 13)
98# define A_REQ_TMROUT (1 << 12) 95# define A_REQ_TMROUT (1 << 12)
@@ -102,9 +99,9 @@
102# define B_SRP_DONE (1 << 8) 99# define B_SRP_DONE (1 << 8)
103# define B_SRP_STARTED (1 << 7) 100# define B_SRP_STARTED (1 << 7)
104# define OPRT_CHG (1 << 0) 101# define OPRT_CHG (1 << 0)
105#define OTG_IRQ_SRC_REG OTG_REG16(0x14) 102#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
106 // same bits as in IRQ_EN 103 // same bits as in IRQ_EN
107#define OTG_OUTCTRL_REG OTG_REG16(0x18) 104#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
108# define OTGVPD (1 << 14) 105# define OTGVPD (1 << 14)
109# define OTGVPU (1 << 13) 106# define OTGVPU (1 << 13)
110# define OTGPUID (1 << 12) 107# define OTGPUID (1 << 12)
@@ -117,13 +114,13 @@
117# define USB0VDR (1 << 2) 114# define USB0VDR (1 << 2)
118# define USB0PDEN (1 << 1) 115# define USB0PDEN (1 << 1)
119# define USB0PUEN (1 << 0) 116# define USB0PUEN (1 << 0)
120#define OTG_TEST_REG OTG_REG16(0x20) 117#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
121#define OTG_VENDOR_CODE_REG OTG_REG32(0xfc) 118#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
122 119
123/*-------------------------------------------------------------------------*/ 120/*-------------------------------------------------------------------------*/
124 121
125/* OMAP1 */ 122/* OMAP1 */
126#define USB_TRANSCEIVER_CTRL_REG __REG32(0xfffe1000 + 0x0064) 123#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
127# define CONF_USB2_UNI_R (1 << 8) 124# define CONF_USB2_UNI_R (1 << 8)
128# define CONF_USB1_UNI_R (1 << 7) 125# define CONF_USB1_UNI_R (1 << 7)
129# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) 126# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
index 50f8c8802206..59f1bc96a23b 100644
--- a/include/asm-arm/arch-orion5x/io.h
+++ b/include/asm-arm/arch-orion5x/io.h
@@ -14,7 +14,6 @@
14#include "orion5x.h" 14#include "orion5x.h"
15 15
16#define IO_SPACE_LIMIT 0xffffffff 16#define IO_SPACE_LIMIT 0xffffffff
17#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE
18 17
19static inline void __iomem * 18static inline void __iomem *
20__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) 19__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
@@ -53,15 +52,12 @@ static inline void __iomem *__io(unsigned long addr)
53/***************************************************************************** 52/*****************************************************************************
54 * Helpers to access Orion registers 53 * Helpers to access Orion registers
55 ****************************************************************************/ 54 ****************************************************************************/
56#define orion5x_read(r) __raw_readl(r)
57#define orion5x_write(r, val) __raw_writel(val, r)
58
59/* 55/*
60 * These are not preempt-safe. Locks, if needed, must be taken 56 * These are not preempt-safe. Locks, if needed, must be taken
61 * care of by the caller. 57 * care of by the caller.
62 */ 58 */
63#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) 59#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r))
64#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) 60#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r))
65 61
66 62
67#endif 63#endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
index 206ddd71e193..10257f5c5e9e 100644
--- a/include/asm-arm/arch-orion5x/orion5x.h
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -2,7 +2,7 @@
2 * include/asm-arm/arch-orion5x/orion5x.h 2 * include/asm-arm/arch-orion5x/orion5x.h
3 * 3 *
4 * Generic definitions of Orion SoC flavors: 4 * Generic definitions of Orion SoC flavors:
5 * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. 5 * Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
6 * 6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 * 8 *
@@ -63,9 +63,11 @@
63/******************************************************************************* 63/*******************************************************************************
64 * Supported Devices & Revisions 64 * Supported Devices & Revisions
65 ******************************************************************************/ 65 ******************************************************************************/
66/* Orion-1 (88F5181) */ 66/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
67#define MV88F5181_DEV_ID 0x5181 67#define MV88F5181_DEV_ID 0x5181
68#define MV88F5181_REV_B1 3 68#define MV88F5181_REV_B1 3
69#define MV88F5181L_REV_A0 8
70#define MV88F5181L_REV_A1 9
69/* Orion-NAS (88F5182) */ 71/* Orion-NAS (88F5182) */
70#define MV88F5182_DEV_ID 0x5182 72#define MV88F5182_DEV_ID 0x5182
71#define MV88F5182_REV_A2 2 73#define MV88F5182_REV_A2 2
@@ -152,6 +154,7 @@
152#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) 154#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
153#define BRIDGE_INT_TIMER0 0x0002 155#define BRIDGE_INT_TIMER0 0x0002
154#define BRIDGE_INT_TIMER1 0x0004 156#define BRIDGE_INT_TIMER1 0x0004
157#define BRIDGE_INT_TIMER1_CLR (~0x0004)
155#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) 158#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
156#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) 159#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
157 160
diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
index 5c13d4fafb4e..7548cedf2d76 100644
--- a/include/asm-arm/arch-orion5x/uncompress.h
+++ b/include/asm-arm/arch-orion5x/uncompress.h
@@ -8,23 +8,38 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11#include <linux/serial_reg.h>
11#include <asm/arch/orion5x.h> 12#include <asm/arch/orion5x.h>
12 13
13#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) 14#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
14#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
15
16#define LSR_THRE 0x20
17 15
18static void putc(const char c) 16static void putc(const char c)
19{ 17{
20 int j = 0x1000; 18 unsigned char *base = SERIAL_BASE;
21 while (--j && !(*MV_UART_LSR & LSR_THRE)) 19 int i;
20
21 for (i = 0; i < 0x1000; i++) {
22 if (base[UART_LSR << 2] & UART_LSR_THRE)
23 break;
22 barrier(); 24 barrier();
23 *MV_UART_THR = c; 25 }
26
27 base[UART_TX << 2] = c;
24} 28}
25 29
26static void flush(void) 30static void flush(void)
27{ 31{
32 unsigned char *base = SERIAL_BASE;
33 unsigned char mask;
34 int i;
35
36 mask = UART_LSR_TEMT | UART_LSR_THRE;
37
38 for (i = 0; i < 0x1000; i++) {
39 if ((base[UART_LSR << 2] & mask) == mask)
40 break;
41 barrier();
42 }
28} 43}
29 44
30/* 45/*
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h
index 52bbe3bc25e1..f82f96dd1053 100644
--- a/include/asm-arm/arch-pxa/audio.h
+++ b/include/asm-arm/arch-pxa/audio.h
@@ -12,4 +12,6 @@ typedef struct {
12 void *priv; 12 void *priv;
13} pxa2xx_audio_ops_t; 13} pxa2xx_audio_ops_t;
14 14
15extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
16
15#endif 17#endif
diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h
deleted file mode 100644
index f8fac9e18009..000000000000
--- a/include/asm-arm/arch-pxa/cm-x270.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * linux/include/asm/arch-pxa/cm-x270.h
3 *
4 * Copyright Compulab Ltd., 2003, 2007
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12
13/* CM-x270 device physical addresses */
14#define CMX270_CS1_PHYS (PXA_CS1_PHYS)
15#define MARATHON_PHYS (PXA_CS2_PHYS)
16#define CMX270_IDE104_PHYS (PXA_CS3_PHYS)
17#define CMX270_IT8152_PHYS (PXA_CS4_PHYS)
18
19/* Statically mapped regions */
20#define CMX270_VIRT_BASE (0xe8000000)
21#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
22#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M)
23
24/* GPIO related definitions */
25#define GPIO_IT8152_IRQ (22)
26
27#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ)
28#define PME_IRQ IRQ_GPIO(0)
29#define CMX270_IDE_IRQ IRQ_GPIO(100)
30#define CMX270_GPIRQ1 IRQ_GPIO(101)
31#define CMX270_TOUCHIRQ IRQ_GPIO(96)
32#define CMX270_ETHIRQ IRQ_GPIO(10)
33#define CMX270_GFXIRQ IRQ_GPIO(95)
34#define CMX270_NANDIRQ IRQ_GPIO(89)
35#define CMX270_MMC_IRQ IRQ_GPIO(83)
36
37/* PCMCIA related definitions */
38#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
39#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x)))
40
41#define PCMCIA_S0_CD_VALID IRQ_GPIO(84)
42#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES
43
44#define PCMCIA_S1_CD_VALID IRQ_GPIO(83)
45#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES
46
47#define PCMCIA_S0_RDYINT IRQ_GPIO(82)
48#define PCMCIA_S1_RDYINT IRQ_GPIO(81)
49
50#define PCMCIA_RESET_GPIO 53
diff --git a/include/asm-arm/arch-pxa/eseries-gpio.h b/include/asm-arm/arch-pxa/eseries-gpio.h
new file mode 100644
index 000000000000..4c90b1310270
--- /dev/null
+++ b/include/asm-arm/arch-pxa/eseries-gpio.h
@@ -0,0 +1,50 @@
1/*
2 * eseries-gpio.h
3 *
4 * Copyright (C) Ian Molton <spyro@f2s.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/* e-series power button */
13#define GPIO_ESERIES_POWERBTN 0
14
15/* UDC GPIO definitions */
16#define GPIO_E7XX_USB_DISC 13
17#define GPIO_E7XX_USB_PULLUP 3
18
19#define GPIO_E800_USB_DISC 4
20#define GPIO_E800_USB_PULLUP 84
21
22/* e740 PCMCIA GPIO definitions */
23/* Note: PWR1 seems to be inverted */
24#define GPIO_E740_PCMCIA_CD0 8
25#define GPIO_E740_PCMCIA_CD1 44
26#define GPIO_E740_PCMCIA_RDY0 11
27#define GPIO_E740_PCMCIA_RDY1 6
28#define GPIO_E740_PCMCIA_RST0 27
29#define GPIO_E740_PCMCIA_RST1 24
30#define GPIO_E740_PCMCIA_PWR0 20
31#define GPIO_E740_PCMCIA_PWR1 23
32
33/* e750 PCMCIA GPIO definitions */
34#define GPIO_E750_PCMCIA_CD0 8
35#define GPIO_E750_PCMCIA_RDY0 12
36#define GPIO_E750_PCMCIA_RST0 27
37#define GPIO_E750_PCMCIA_PWR0 20
38
39/* e800 PCMCIA GPIO definitions */
40#define GPIO_E800_PCMCIA_RST0 69
41#define GPIO_E800_PCMCIA_RST1 72
42#define GPIO_E800_PCMCIA_PWR0 20
43#define GPIO_E800_PCMCIA_PWR1 73
44
45/* e7xx IrDA power control */
46#define GPIO_E7XX_IR_ON 38
47
48/* ASIC related GPIOs */
49#define GPIO_ESERIES_TMIO_IRQ 5
50#define GPIO_E800_ANGELX_IRQ 8
diff --git a/include/asm-arm/arch-pxa/eseries-irq.h b/include/asm-arm/arch-pxa/eseries-irq.h
new file mode 100644
index 000000000000..f2a93d5e31d3
--- /dev/null
+++ b/include/asm-arm/arch-pxa/eseries-irq.h
@@ -0,0 +1,27 @@
1/*
2 * eseries-irq.h
3 *
4 * Copyright (C) Ian Molton <spyro@f2s.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8)
13#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n))
14
15#define ANGELX_RDY0_IRQ IRQ_ANGELX(0)
16#define ANGELX_ST0_IRQ IRQ_ANGELX(1)
17#define ANGELX_CD0_IRQ IRQ_ANGELX(2)
18#define ANGELX_RDY1_IRQ IRQ_ANGELX(3)
19#define ANGELX_ST1_IRQ IRQ_ANGELX(4)
20#define ANGELX_CD1_IRQ IRQ_ANGELX(5)
21
22#define TMIO_IRQ_BASE (IRQ_BOARD_START+0)
23#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n))
24
25#define TMIO_SD_IRQ IRQ_TMIO(1)
26#define TMIO_USB_IRQ IRQ_TMIO(2)
27
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index e25558faa5a4..979a45695d7d 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -69,6 +69,12 @@
69 _id == 0x212; \ 69 _id == 0x212; \
70 }) 70 })
71 71
72#define __cpu_is_pxa255(id) \
73 ({ \
74 unsigned int _id = (id) >> 4 & 0xfff; \
75 _id == 0x2d0; \
76 })
77
72#define __cpu_is_pxa25x(id) \ 78#define __cpu_is_pxa25x(id) \
73 ({ \ 79 ({ \
74 unsigned int _id = (id) >> 4 & 0xfff; \ 80 unsigned int _id = (id) >> 4 & 0xfff; \
@@ -76,6 +82,7 @@
76 }) 82 })
77#else 83#else
78#define __cpu_is_pxa21x(id) (0) 84#define __cpu_is_pxa21x(id) (0)
85#define __cpu_is_pxa255(id) (0)
79#define __cpu_is_pxa25x(id) (0) 86#define __cpu_is_pxa25x(id) (0)
80#endif 87#endif
81 88
@@ -119,11 +126,26 @@
119#define __cpu_is_pxa320(id) (0) 126#define __cpu_is_pxa320(id) (0)
120#endif 127#endif
121 128
129#ifdef CONFIG_CPU_PXA930
130#define __cpu_is_pxa930(id) \
131 ({ \
132 unsigned int _id = (id) >> 4 & 0xfff; \
133 _id == 0x683; \
134 })
135#else
136#define __cpu_is_pxa930(id) (0)
137#endif
138
122#define cpu_is_pxa21x() \ 139#define cpu_is_pxa21x() \
123 ({ \ 140 ({ \
124 __cpu_is_pxa21x(read_cpuid_id()); \ 141 __cpu_is_pxa21x(read_cpuid_id()); \
125 }) 142 })
126 143
144#define cpu_is_pxa255() \
145 ({ \
146 __cpu_is_pxa255(read_cpuid_id()); \
147 })
148
127#define cpu_is_pxa25x() \ 149#define cpu_is_pxa25x() \
128 ({ \ 150 ({ \
129 __cpu_is_pxa25x(read_cpuid_id()); \ 151 __cpu_is_pxa25x(read_cpuid_id()); \
@@ -149,6 +171,12 @@
149 __cpu_is_pxa320(read_cpuid_id()); \ 171 __cpu_is_pxa320(read_cpuid_id()); \
150 }) 172 })
151 173
174#define cpu_is_pxa930() \
175 ({ \
176 unsigned int id = read_cpuid(CPUID_ID); \
177 __cpu_is_pxa930(id); \
178 })
179
152/* 180/*
153 * CPUID Core Generation Bit 181 * CPUID Core Generation Bit
154 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x 182 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
@@ -192,18 +220,14 @@ extern int pxa_gpio_get_value(unsigned gpio);
192extern void pxa_gpio_set_value(unsigned gpio, int value); 220extern void pxa_gpio_set_value(unsigned gpio, int value);
193 221
194/* 222/*
195 * Routine to enable or disable CKEN 223 * return current memory and LCD clock frequency in units of 10kHz
196 */ 224 */
197static inline void __deprecated pxa_set_cken(int clock, int enable) 225extern unsigned int get_memclk_frequency_10khz(void);
198{
199 extern void __pxa_set_cken(int clock, int enable);
200 __pxa_set_cken(clock, enable);
201}
202 226
203/* 227/*
204 * return current memory and LCD clock frequency in units of 10kHz 228 * register GPIO as reset generator
205 */ 229 */
206extern unsigned int get_memclk_frequency_10khz(void); 230extern int init_gpio_reset(int gpio);
207 231
208#endif 232#endif
209 233
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
index 99f4f423a8e1..0a50c3c763df 100644
--- a/include/asm-arm/arch-pxa/irda.h
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -16,4 +16,8 @@ struct pxaficp_platform_data {
16 16
17extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); 17extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
18 18
19#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
20void pxa2xx_transceiver_mode(struct device *dev, int mode);
21#endif
22
19#endif 23#endif
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index b6c8fe377683..9413121b0ed9 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -180,10 +180,13 @@
180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) 180#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
181#elif defined(CONFIG_ARCH_LUBBOCK) || \ 181#elif defined(CONFIG_ARCH_LUBBOCK) || \
182 defined(CONFIG_MACH_LOGICPD_PXA270) || \ 182 defined(CONFIG_MACH_LOGICPD_PXA270) || \
183 defined(CONFIG_MACH_TOSA) || \
183 defined(CONFIG_MACH_MAINSTONE) || \ 184 defined(CONFIG_MACH_MAINSTONE) || \
184 defined(CONFIG_MACH_PCM027) || \ 185 defined(CONFIG_MACH_PCM027) || \
185 defined(CONFIG_MACH_MAGICIAN) 186 defined(CONFIG_MACH_MAGICIAN)
186#define NR_IRQS (IRQ_BOARD_END) 187#define NR_IRQS (IRQ_BOARD_END)
188#elif defined(CONFIG_MACH_ZYLONITE)
189#define NR_IRQS (IRQ_BOARD_START + 32)
187#else 190#else
188#define NR_IRQS (IRQ_BOARD_START) 191#define NR_IRQS (IRQ_BOARD_START)
189#endif 192#endif
diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
index db8d890d237c..8de1c0dae624 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa2xx.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
@@ -128,5 +128,6 @@
128#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) 128#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0)
129 129
130extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); 130extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
131extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm);
131extern int gpio_set_wake(unsigned int gpio, unsigned int on); 132extern int gpio_set_wake(unsigned int gpio, unsigned int on);
132#endif /* __ASM_ARCH_MFP_PXA2XX_H */ 133#endif /* __ASM_ARCH_MFP_PXA2XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa930.h b/include/asm-arm/arch-pxa/mfp-pxa930.h
new file mode 100644
index 000000000000..c4e945ab1923
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa930.h
@@ -0,0 +1,491 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp-pxa930.h
3 *
4 * PXA930 specific MFP configuration definitions
5 *
6 * Copyright (C) 2007-2008 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_MFP_PXA9xx_H
14#define __ASM_ARCH_MFP_PXA9xx_H
15
16#include <asm/arch/mfp.h>
17#include <asm/arch/mfp-pxa3xx.h>
18
19/* GPIO */
20#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
21#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
22#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
23#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
24#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
25#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
26#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
27#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
28#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
29#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
30#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
31
32#define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0)
33#define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0)
34#define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0)
35#define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0)
36
37#define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0)
38#define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0)
39#define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0)
40#define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0)
41#define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0)
42#define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0)
43#define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0)
44#define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0)
45#define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0)
46#define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0)
47#define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0)
48#define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0)
49#define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0)
50#define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0)
51#define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0)
52#define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0)
53#define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0)
54#define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0)
55#define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0)
56#define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0)
57#define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0)
58#define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0)
59#define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0)
60#define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0)
61#define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0)
62
63#define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0)
64#define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0)
65#define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0)
66#define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0)
67#define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0)
68#define nLUA_GPIO_58 MFP_CFG(nLUA, AF0)
69#define nLLA_GPIO_59 MFP_CFG(nLLA, AF0)
70#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0)
71#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0)
72#define RDY_GPIO_62 MFP_CFG(RDY, AF0)
73
74/* Chip Select */
75#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
76#define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH)
77
78/* AC97 */
79#define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3)
80#define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3)
81#define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3)
82#define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3)
83#define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3)
84#define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3)
85
86/* I2C */
87#define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH)
88#define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH)
89
90#define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH)
91#define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH)
92
93#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
94#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
95
96#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
97#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
98
99#define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH)
100#define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH)
101
102#define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
103#define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
104
105#define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH)
106#define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH)
107
108/* QCI */
109#define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW)
110#define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW)
111#define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW)
112#define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW)
113#define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW)
114#define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW)
115#define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW)
116#define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW)
117#define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW)
118#define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW)
119#define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW)
120#define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW)
121#define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW)
122#define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW)
123
124/* KEYPAD */
125#define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT)
126#define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT)
127#define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT)
128#define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT)
129#define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT)
130#define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
131#define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
132#define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT)
133
134#define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT)
135#define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT)
136#define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT)
137#define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT)
138
139#define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT)
140#define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT)
141#define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT)
142#define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT)
143#define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT)
144#define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT)
145
146#define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT)
147#define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT)
148#define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT)
149#define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT)
150#define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT)
151#define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT)
152#define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT)
153#define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1)
154#define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4)
155
156#define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH)
157#define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH)
158#define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH)
159#define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
160#define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH)
161#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH)
162#define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH)
163#define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH)
164#define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH)
165
166/* LCD */
167#define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1)
168#define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1)
169#define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1)
170#define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1)
171#define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1)
172#define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2)
173#define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1)
174#define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1)
175#define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1)
176#define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1)
177#define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1)
178#define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1)
179#define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1)
180#define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1)
181#define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1)
182#define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1)
183#define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1)
184#define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1)
185#define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1)
186#define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1)
187#define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1)
188#define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1)
189#define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1)
190#define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1)
191#define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1)
192#define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3)
193#define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3)
194#define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1)
195
196/* Mini-LCD */
197#define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3)
198#define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3)
199#define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3)
200#define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3)
201#define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3)
202#define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3)
203#define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3)
204#define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3)
205#define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3)
206#define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3)
207#define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3)
208#define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3)
209#define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3)
210#define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3)
211#define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3)
212#define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3)
213#define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3)
214#define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3)
215#define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3)
216#define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3)
217#define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5)
218
219/* MMC1 */
220#define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4)
221#define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4)
222#define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4)
223#define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4)
224#define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4)
225#define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4)
226#define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3)
227#define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3)
228#define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3)
229#define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3)
230#define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3)
231#define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3)
232
233#define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2)
234#define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2)
235#define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2)
236#define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3)
237#define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2)
238
239/* MMC2 */
240#define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7)
241#define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7)
242#define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7)
243#define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7)
244#define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7)
245#define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7)
246
247#define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1)
248#define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1)
249#define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1)
250#define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1)
251#define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1)
252#define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1)
253
254#define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3)
255#define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3)
256#define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3)
257#define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3)
258#define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3)
259#define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3)
260
261/* BSSP1 */
262#define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3)
263#define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3)
264#define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3)
265#define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3)
266#define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5)
267#define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5)
268
269/* BSSP2 */
270#define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1)
271#define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1)
272#define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1)
273#define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1)
274#define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1)
275#define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4)
276
277/* BSSP3 */
278#define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1)
279#define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1)
280#define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1)
281#define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1)
282#define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1)
283
284/* BSSP4 */
285#define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4)
286#define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4)
287#define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4)
288#define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4)
289
290#define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4)
291#define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4)
292#define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4)
293#define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4)
294
295/* GSSP1 */
296#define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2)
297#define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2)
298#define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2)
299#define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2)
300#define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2)
301
302#define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4)
303#define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4)
304#define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4)
305#define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4)
306
307/* GSSP2 */
308#define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4)
309#define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4)
310#define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4)
311#define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4)
312
313#define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4)
314#define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4)
315#define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4)
316#define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4)
317
318#define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2)
319#define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2)
320#define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2)
321#define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2)
322#define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2)
323#define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5)
324
325#define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2)
326#define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2)
327#define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2)
328#define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2)
329
330/* UART1 - FFUART */
331#define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1)
332#define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1)
333#define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1)
334#define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1)
335#define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1)
336#define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1)
337#define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1)
338#define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1)
339
340#define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2)
341#define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2)
342#define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2)
343#define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2)
344#define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2)
345#define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2)
346#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2)
347#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2)
348
349/* UART2 - BTUART */
350#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1)
351#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1)
352#define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1)
353#define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1)
354
355/* UART3 - STUART */
356#define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3)
357#define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3)
358#define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3)
359#define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3)
360
361#define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5)
362#define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5)
363#define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5)
364#define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5)
365
366/* DFI */
367#define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2)
368#define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2)
369#define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2)
370#define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2)
371#define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2)
372#define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2)
373#define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2)
374#define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2)
375#define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2)
376#define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2)
377#define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2)
378#define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2)
379#define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2)
380#define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2)
381#define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2)
382#define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2)
383#define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2)
384#define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2)
385#define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2)
386#define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2)
387#define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2)
388#define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2)
389
390/* DFI - NAND */
391#define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH)
392#define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW)
393#define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW)
394#define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW)
395#define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW)
396#define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW)
397#define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW)
398#define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW)
399#define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW)
400#define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW)
401#define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW)
402#define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW)
403#define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW)
404#define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW)
405#define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW)
406#define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW)
407#define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW)
408#define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW)
409#define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH)
410#define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH)
411#define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH)
412#define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH)
413#define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH)
414#define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH)
415#define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH)
416
417/* PWM */
418#define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW)
419#define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW)
420#define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW)
421#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
422#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
423#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
424
425/* CIR */
426#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1)
427#define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3)
428
429/* USB P2 */
430#define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3)
431#define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5)
432#define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2)
433#define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7)
434#define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6)
435#define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3)
436
437#define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2)
438#define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT)
439#define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2)
440#define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2)
441#define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2)
442#define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2)
443#define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2)
444#define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2)
445
446#define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3)
447#define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3)
448#define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3)
449#define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3)
450#define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3)
451#define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3)
452#define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3)
453#define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3)
454
455/* ULPI */
456#define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4)
457#define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7)
458#define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5)
459#define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5)
460#define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5)
461#define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5)
462#define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5)
463#define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5)
464#define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4)
465#define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4)
466#define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4)
467#define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4)
468
469#define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3)
470#define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7)
471#define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5)
472#define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4)
473#define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3)
474#define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3)
475
476#define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5)
477#define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7)
478#define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5)
479#define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4)
480
481#define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3)
482#define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7)
483#define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3)
484#define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5)
485#define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4)
486#define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3)
487
488/* 1 wire */
489#define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5)
490
491#endif /* __ASM_ARCH_MFP_PXA9xx_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
index 02f6157396d3..e7d58798da67 100644
--- a/include/asm-arm/arch-pxa/mfp.h
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -210,6 +210,14 @@ enum {
210 MFP_PIN_DF_IO14, 210 MFP_PIN_DF_IO14,
211 MFP_PIN_DF_IO15, 211 MFP_PIN_DF_IO15,
212 212
213 /* additional pins on PXA930 */
214 MFP_PIN_GSIM_UIO,
215 MFP_PIN_GSIM_UCLK,
216 MFP_PIN_GSIM_UDET,
217 MFP_PIN_GSIM_nURST,
218 MFP_PIN_PMIC_INT,
219 MFP_PIN_RDY,
220
213 MFP_PIN_MAX, 221 MFP_PIN_MAX,
214}; 222};
215 223
diff --git a/include/asm-arm/arch-pxa/palmtx.h b/include/asm-arm/arch-pxa/palmtx.h
new file mode 100644
index 000000000000..1e8bccbda510
--- /dev/null
+++ b/include/asm-arm/arch-pxa/palmtx.h
@@ -0,0 +1,106 @@
1/*
2 * GPIOs and interrupts for Palm T|X Handheld Computer
3 *
4 * Based on palmld-gpio.h by Alex Osborne
5 *
6 * Authors: Marek Vasut <marek.vasut@gmail.com>
7 * Cristiano P. <cristianop@users.sourceforge.net>
8 * Jan Herman <2hp@seznam.cz>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#ifndef _INCLUDE_PALMTX_H_
17#define _INCLUDE_PALMTX_H_
18
19/** HERE ARE GPIOs **/
20
21/* GPIOs */
22#define GPIO_NR_PALMTX_GPIO_RESET 1
23
24#define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */
25#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10
26#define GPIO_NR_PALMTX_EARPHONE_DETECT 107
27
28/* SD/MMC */
29#define GPIO_NR_PALMTX_SD_DETECT_N 14
30#define GPIO_NR_PALMTX_SD_POWER 114 /* probably */
31#define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */
32
33/* TOUCHSCREEN */
34#define GPIO_NR_PALMTX_WM9712_IRQ 27
35
36/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
37#define GPIO_NR_PALMTX_IR_DISABLE 40
38
39/* USB */
40#define GPIO_NR_PALMTX_USB_DETECT_N 13
41#define GPIO_NR_PALMTX_USB_POWER 95
42#define GPIO_NR_PALMTX_USB_PULLUP 93
43
44/* LCD/BACKLIGHT */
45#define GPIO_NR_PALMTX_BL_POWER 84
46#define GPIO_NR_PALMTX_LCD_POWER 96
47
48/* LCD BORDER */
49#define GPIO_NR_PALMTX_BORDER_SWITCH 98
50#define GPIO_NR_PALMTX_BORDER_SELECT 22
51
52/* BLUETOOTH */
53#define GPIO_NR_PALMTX_BT_POWER 17
54#define GPIO_NR_PALMTX_BT_RESET 83
55
56/* PCMCIA (WiFi) */
57#define GPIO_NR_PALMTX_PCMCIA_POWER1 94
58#define GPIO_NR_PALMTX_PCMCIA_POWER2 108
59#define GPIO_NR_PALMTX_PCMCIA_RESET 79
60#define GPIO_NR_PALMTX_PCMCIA_READY 116
61
62/* NAND Flash ... this GPIO may be incorrect! */
63#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79
64
65/* INTERRUPTS */
66#define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N)
67#define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ)
68#define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT)
69#define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET)
70
71/** HERE ARE INIT VALUES **/
72
73/* Various addresses */
74#define PALMTX_PCMCIA_PHYS 0x28000000
75#define PALMTX_PCMCIA_VIRT 0xf0000000
76#define PALMTX_PCMCIA_SIZE 0x100000
77
78#define PALMTX_PHYS_RAM_START 0xa0000000
79#define PALMTX_PHYS_IO_START 0x40000000
80
81#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
82#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */
83
84/* TOUCHSCREEN */
85#define AC97_LINK_FRAME 21
86
87
88/* BATTERY */
89#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
90#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
91#define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */
92#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */
93#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */
94#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */
95#define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */
96
97#define PALMTX_BAT_MEASURE_DELAY (HZ * 1)
98
99/* BACKLIGHT */
100#define PALMTX_MAX_INTENSITY 0xFE
101#define PALMTX_DEFAULT_INTENSITY 0x7E
102#define PALMTX_LIMIT_MASK 0x7F
103#define PALMTX_PRESCALER 0x3F
104#define PALMTX_PERIOD_NS 3500
105
106#endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 4b2ea1e95c57..dce9308626b7 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -600,418 +600,6 @@
600 600
601 601
602/* 602/*
603 * USB Device Controller
604 * PXA25x and PXA27x USB device controller registers are different.
605 */
606#if defined(CONFIG_PXA25x)
607
608#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
609#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
610#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
611
612#define UDCCR __REG(0x40600000) /* UDC Control Register */
613#define UDCCR_UDE (1 << 0) /* UDC enable */
614#define UDCCR_UDA (1 << 1) /* UDC active */
615#define UDCCR_RSM (1 << 2) /* Device resume */
616#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
617#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
618#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
619#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
620#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
621
622#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
623#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
624#define UDCCS0_IPR (1 << 1) /* IN packet ready */
625#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
626#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
627#define UDCCS0_SST (1 << 4) /* Sent stall */
628#define UDCCS0_FST (1 << 5) /* Force stall */
629#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
630#define UDCCS0_SA (1 << 7) /* Setup active */
631
632/* Bulk IN - Endpoint 1,6,11 */
633#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
634#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
635#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
636
637#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
638#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
639#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
640#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
641#define UDCCS_BI_SST (1 << 4) /* Sent stall */
642#define UDCCS_BI_FST (1 << 5) /* Force stall */
643#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
644
645/* Bulk OUT - Endpoint 2,7,12 */
646#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
647#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
648#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
649
650#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
651#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
652#define UDCCS_BO_DME (1 << 3) /* DMA enable */
653#define UDCCS_BO_SST (1 << 4) /* Sent stall */
654#define UDCCS_BO_FST (1 << 5) /* Force stall */
655#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
656#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
657
658/* Isochronous IN - Endpoint 3,8,13 */
659#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
660#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
661#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
662
663#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
664#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
665#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
666#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
667#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
668
669/* Isochronous OUT - Endpoint 4,9,14 */
670#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
671#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
672#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
673
674#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
675#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
676#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
677#define UDCCS_IO_DME (1 << 3) /* DMA enable */
678#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
679#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
680
681/* Interrupt IN - Endpoint 5,10,15 */
682#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
683#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
684#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
685
686#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
687#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
688#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
689#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
690#define UDCCS_INT_SST (1 << 4) /* Sent stall */
691#define UDCCS_INT_FST (1 << 5) /* Force stall */
692#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
693
694#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
695#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
696#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
697#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
698#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
699#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
700#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
701#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
702#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
703#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
704#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
705#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
706#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
707#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
708#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
709#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
710#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
711#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
712#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
713#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
714#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
715#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
716#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
717#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
718
719#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
720
721#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
722#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
723#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
724#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
725#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
726#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
727#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
728#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
729
730#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
731
732#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
733#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
734#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
735#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
736#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
737#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
738#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
739#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
740
741#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
742
743#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
744#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
745#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
746#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
747#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
748#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
749#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
750#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
751
752#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
753
754#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
755#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
756#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
757#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
758#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
759#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
760#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
761#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
762
763#elif defined(CONFIG_PXA27x)
764
765#define UDCCR __REG(0x40600000) /* UDC Control Register */
766#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
767#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
768 Protocol Port Support */
769#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
770 Support */
771#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
772 Enable */
773#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
774#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
775#define UDCCR_ACN_S 11
776#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
777#define UDCCR_AIN_S 8
778#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
779 Setting Number */
780#define UDCCR_AAISN_S 5
781#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
782 Configuration */
783#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
784 Error */
785#define UDCCR_UDR (1 << 2) /* UDC Resume */
786#define UDCCR_UDA (1 << 1) /* UDC Active */
787#define UDCCR_UDE (1 << 0) /* UDC Enable */
788
789#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
790#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
791#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
792#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
793
794#define UDC_INT_FIFOERROR (0x2)
795#define UDC_INT_PACKETCMP (0x1)
796
797#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
798#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
799#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
800#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
801#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
802#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
803
804#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
805#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
806#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
807#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
808#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
809#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
810#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
811#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
812
813#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
814#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
815#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
816#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
817 Rising Edge Interrupt Enable */
818#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
819 Falling Edge Interrupt Enable */
820#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
821 Interrupt Enable */
822#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
823 Interrupt Enable */
824#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
825 Interrupt Enable */
826#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
827 Interrupt Enable */
828#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
829 Interrupt Enable */
830#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
831 Interrupt Enable */
832#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
833 Edge Interrupt Enable */
834#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
835 Edge Interrupt Enable */
836#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
837 Interrupt Enable */
838#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
839 Interrupt Enable */
840
841#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
842
843#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
844#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
845#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
846#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
847#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
848#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
849#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
850#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
851#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
852#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
853#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
854#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
855#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
856#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
857
858#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
859#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
860#define UDCCSR0_SA (1 << 7) /* Setup Active */
861#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
862#define UDCCSR0_FST (1 << 5) /* Force Stall */
863#define UDCCSR0_SST (1 << 4) /* Sent Stall */
864#define UDCCSR0_DME (1 << 3) /* DMA Enable */
865#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
866#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
867#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
868
869#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
870#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
871#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
872#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
873#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
874#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
875#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
876#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
877#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
878#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
879#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
880#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
881#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
882#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
883#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
884#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
885#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
886#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
887#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
888#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
889#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
890#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
891#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
892
893#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
894#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
895#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
896#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
897#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
898#define UDCCSR_FST (1 << 5) /* Force STALL */
899#define UDCCSR_SST (1 << 4) /* Sent STALL */
900#define UDCCSR_DME (1 << 3) /* DMA Enable */
901#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
902#define UDCCSR_PC (1 << 1) /* Packet Complete */
903#define UDCCSR_FS (1 << 0) /* FIFO needs service */
904
905#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
906#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
907#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
908#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
909#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
910#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
911#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
912#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
913#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
914#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
915#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
916#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
917#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
918#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
919#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
920#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
921#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
922#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
923#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
924#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
925#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
926#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
927#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
928#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
929#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
930
931#define UDCDN(x) __REG2(0x40600300, (x)<<2)
932#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
933#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
934#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
935#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
936#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
937#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
938#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
939#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
940#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
941#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
942#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
943#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
944#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
945#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
946#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
947#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
948#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
949#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
950#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
951#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
952#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
953#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
954#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
955#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
956#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
957#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
958
959#define UDCCN(x) __REG2(0x40600400, (x)<<2)
960#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
961#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
962#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
963#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
964#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
965#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
966#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
967#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
968#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
969#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
970#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
971#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
972#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
973#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
974#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
975#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
976#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
977#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
978#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
979#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
980#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
981#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
982#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
983
984#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
985#define UDCCONR_CN_S (25)
986#define UDCCONR_IN (0x07 << 22) /* Interface Number */
987#define UDCCONR_IN_S (22)
988#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
989#define UDCCONR_AISN_S (19)
990#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
991#define UDCCONR_EN_S (15)
992#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
993#define UDCCONR_ET_S (13)
994#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
995#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
996#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
997#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
998#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
999#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
1000#define UDCCONR_MPS_S (2)
1001#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
1002#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
1003
1004
1005#define UDC_INT_FIFOERROR (0x2)
1006#define UDC_INT_PACKETCMP (0x1)
1007
1008#define UDC_FNR_MASK (0x7ff)
1009
1010#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
1011#define UDC_BCR_MASK (0x3ff)
1012#endif
1013
1014/*
1015 * Fast Infrared Communication Port 603 * Fast Infrared Communication Port
1016 */ 604 */
1017 605
@@ -1237,120 +825,9 @@
1237#endif 825#endif
1238 826
1239/* 827/*
1240 * Power Manager 828 * Power Manager - see pxa2xx-regs.h
1241 */ 829 */
1242 830
1243#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
1244#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
1245#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
1246#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
1247#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
1248#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
1249#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
1250#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
1251#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
1252#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
1253#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
1254#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
1255#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
1256
1257#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
1258#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
1259#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
1260#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
1261#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
1262#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
1263#define PCMD(x) __REG2(0x40F00080, (x)<<2)
1264#define PCMD0 __REG(0x40F00080 + 0 * 4)
1265#define PCMD1 __REG(0x40F00080 + 1 * 4)
1266#define PCMD2 __REG(0x40F00080 + 2 * 4)
1267#define PCMD3 __REG(0x40F00080 + 3 * 4)
1268#define PCMD4 __REG(0x40F00080 + 4 * 4)
1269#define PCMD5 __REG(0x40F00080 + 5 * 4)
1270#define PCMD6 __REG(0x40F00080 + 6 * 4)
1271#define PCMD7 __REG(0x40F00080 + 7 * 4)
1272#define PCMD8 __REG(0x40F00080 + 8 * 4)
1273#define PCMD9 __REG(0x40F00080 + 9 * 4)
1274#define PCMD10 __REG(0x40F00080 + 10 * 4)
1275#define PCMD11 __REG(0x40F00080 + 11 * 4)
1276#define PCMD12 __REG(0x40F00080 + 12 * 4)
1277#define PCMD13 __REG(0x40F00080 + 13 * 4)
1278#define PCMD14 __REG(0x40F00080 + 14 * 4)
1279#define PCMD15 __REG(0x40F00080 + 15 * 4)
1280#define PCMD16 __REG(0x40F00080 + 16 * 4)
1281#define PCMD17 __REG(0x40F00080 + 17 * 4)
1282#define PCMD18 __REG(0x40F00080 + 18 * 4)
1283#define PCMD19 __REG(0x40F00080 + 19 * 4)
1284#define PCMD20 __REG(0x40F00080 + 20 * 4)
1285#define PCMD21 __REG(0x40F00080 + 21 * 4)
1286#define PCMD22 __REG(0x40F00080 + 22 * 4)
1287#define PCMD23 __REG(0x40F00080 + 23 * 4)
1288#define PCMD24 __REG(0x40F00080 + 24 * 4)
1289#define PCMD25 __REG(0x40F00080 + 25 * 4)
1290#define PCMD26 __REG(0x40F00080 + 26 * 4)
1291#define PCMD27 __REG(0x40F00080 + 27 * 4)
1292#define PCMD28 __REG(0x40F00080 + 28 * 4)
1293#define PCMD29 __REG(0x40F00080 + 29 * 4)
1294#define PCMD30 __REG(0x40F00080 + 30 * 4)
1295#define PCMD31 __REG(0x40F00080 + 31 * 4)
1296
1297#define PCMD_MBC (1<<12)
1298#define PCMD_DCE (1<<11)
1299#define PCMD_LC (1<<10)
1300/* FIXME: PCMD_SQC need be checked. */
1301#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
1302 bit 9 should be 0 all day. */
1303#define PVCR_VCSA (0x1<<14)
1304#define PVCR_CommandDelay (0xf80)
1305#define PCFR_PI2C_EN (0x1 << 6)
1306
1307#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1308#define PSSR_RDH (1 << 5) /* Read Disable Hold */
1309#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1310#define PSSR_STS (1 << 3) /* Standby Mode Status */
1311#define PSSR_VFS (1 << 2) /* VDD Fault Status */
1312#define PSSR_BFS (1 << 1) /* Battery Fault Status */
1313#define PSSR_SSS (1 << 0) /* Software Sleep Status */
1314
1315#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
1316
1317#define PCFR_RO (1 << 15) /* RDH Override */
1318#define PCFR_PO (1 << 14) /* PH Override */
1319#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
1320#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
1321#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
1322#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
1323#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
1324#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
1325#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1326#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1327#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
1328#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
1329
1330#define RCSR_GPR (1 << 3) /* GPIO Reset */
1331#define RCSR_SMR (1 << 2) /* Sleep Mode */
1332#define RCSR_WDR (1 << 1) /* Watchdog Reset */
1333#define RCSR_HWR (1 << 0) /* Hardware Reset */
1334
1335#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
1336#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1337#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1338#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1339#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1340#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1341#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1342#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1343#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1344#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1345#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1346#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1347#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1348#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1349#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1350#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1351#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1352#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1353
1354/* 831/*
1355 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h 832 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
1356 */ 833 */
@@ -1360,52 +837,9 @@
1360 */ 837 */
1361 838
1362/* 839/*
1363 * Core Clock 840 * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
1364 */ 841 */
1365 842
1366#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
1367#define CKEN __REG(0x41300004) /* Clock Enable Register */
1368#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
1369#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
1370
1371#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1372#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1373#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1374
1375#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
1376#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
1377#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
1378#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
1379#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
1380#define CKEN_IM (20) /* Internal Memory Clock Enable */
1381#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
1382#define CKEN_USIM (18) /* USIM Unit Clock Enable */
1383#define CKEN_MSL (17) /* MSL Unit Clock Enable */
1384#define CKEN_LCD (16) /* LCD Unit Clock Enable */
1385#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
1386#define CKEN_I2C (14) /* I2C Unit Clock Enable */
1387#define CKEN_FICP (13) /* FICP Unit Clock Enable */
1388#define CKEN_MMC (12) /* MMC Unit Clock Enable */
1389#define CKEN_USB (11) /* USB Unit Clock Enable */
1390#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
1391#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
1392#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
1393#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
1394#define CKEN_I2S (8) /* I2S Unit Clock Enable */
1395#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
1396#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
1397#define CKEN_STUART (5) /* STUART Unit Clock Enable */
1398#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
1399#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
1400#define CKEN_SSP (3) /* SSP Unit Clock Enable */
1401#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
1402#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
1403#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
1404#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
1405
1406#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1407#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1408
1409#ifdef CONFIG_PXA27x 843#ifdef CONFIG_PXA27x
1410 844
1411/* Camera Interface */ 845/* Camera Interface */
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h
new file mode 100644
index 000000000000..840305916b6d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa25x-udc.h
@@ -0,0 +1,163 @@
1#ifndef _ASM_ARCH_PXA25X_UDC_H
2#define _ASM_ARCH_PXA25X_UDC_H
3
4#ifdef _ASM_ARCH_PXA27X_UDC_H
5#error You can't include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
11
12#define UDCCR __REG(0x40600000) /* UDC Control Register */
13#define UDCCR_UDE (1 << 0) /* UDC enable */
14#define UDCCR_UDA (1 << 1) /* UDC active */
15#define UDCCR_RSM (1 << 2) /* Device resume */
16#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
17#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
18#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
19#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
20#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
21
22#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
23#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
24#define UDCCS0_IPR (1 << 1) /* IN packet ready */
25#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
26#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
27#define UDCCS0_SST (1 << 4) /* Sent stall */
28#define UDCCS0_FST (1 << 5) /* Force stall */
29#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
30#define UDCCS0_SA (1 << 7) /* Setup active */
31
32/* Bulk IN - Endpoint 1,6,11 */
33#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
36
37#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
38#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
39#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
40#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
41#define UDCCS_BI_SST (1 << 4) /* Sent stall */
42#define UDCCS_BI_FST (1 << 5) /* Force stall */
43#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
44
45/* Bulk OUT - Endpoint 2,7,12 */
46#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
48#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
49
50#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
51#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
52#define UDCCS_BO_DME (1 << 3) /* DMA enable */
53#define UDCCS_BO_SST (1 << 4) /* Sent stall */
54#define UDCCS_BO_FST (1 << 5) /* Force stall */
55#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
56#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
57
58/* Isochronous IN - Endpoint 3,8,13 */
59#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
60#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
61#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
62
63#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
64#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
65#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
66#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
67#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
68
69/* Isochronous OUT - Endpoint 4,9,14 */
70#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
71#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
72#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
73
74#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
75#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
76#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
77#define UDCCS_IO_DME (1 << 3) /* DMA enable */
78#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
79#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
80
81/* Interrupt IN - Endpoint 5,10,15 */
82#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
83#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
84#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
85
86#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
87#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
88#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
89#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
90#define UDCCS_INT_SST (1 << 4) /* Sent stall */
91#define UDCCS_INT_FST (1 << 5) /* Force stall */
92#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
93
94#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
95#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
96#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
97#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
98#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
99#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
100#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
101#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
102#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
103#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
104#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
105#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
106#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
107#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
108#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
109#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
110#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
111#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
112#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
113#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
114#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
115#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
116#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
117#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
118
119#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
120
121#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
122#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
123#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
124#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
125#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
126#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
127#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
128#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
129
130#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
131
132#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
133#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
134#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
135#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
136#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
137#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
138#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
139#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
140
141#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
142
143#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
144#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
145#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
146#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
147#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
148#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
149#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
150#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
151
152#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
153
154#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
155#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
156#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
157#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
158#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
159#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
160#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
161#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
162
163#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
new file mode 100644
index 000000000000..ab1443f8bd89
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa27x-udc.h
@@ -0,0 +1,257 @@
1#ifndef _ASM_ARCH_PXA27X_UDC_H
2#define _ASM_ARCH_PXA27X_UDC_H
3
4#ifdef _ASM_ARCH_PXA25X_UDC_H
5#error You cannot include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDCCR __REG(0x40600000) /* UDC Control Register */
9#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
10#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
11 Protocol Port Support */
12#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
13 Support */
14#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
15 Enable */
16#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
17#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
18#define UDCCR_ACN_S 11
19#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
20#define UDCCR_AIN_S 8
21#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
22 Setting Number */
23#define UDCCR_AAISN_S 5
24#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
25 Configuration */
26#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
27 Error */
28#define UDCCR_UDR (1 << 2) /* UDC Resume */
29#define UDCCR_UDA (1 << 1) /* UDC Active */
30#define UDCCR_UDE (1 << 0) /* UDC Enable */
31
32#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
33#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
34#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
35#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
36
37#define UDC_INT_FIFOERROR (0x2)
38#define UDC_INT_PACKETCMP (0x1)
39
40#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
41#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
42#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
43#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
44#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
45#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
46
47#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
48#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
49#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
50#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
51#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
52#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
53#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
54#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
55
56#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
57#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
58#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
59#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
60 Rising Edge Interrupt Enable */
61#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
62 Falling Edge Interrupt Enable */
63#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
64 Interrupt Enable */
65#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
66 Interrupt Enable */
67#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
68 Interrupt Enable */
69#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
70 Interrupt Enable */
71#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
72 Interrupt Enable */
73#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
74 Interrupt Enable */
75#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
76 Edge Interrupt Enable */
77#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
78 Edge Interrupt Enable */
79#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
80 Interrupt Enable */
81#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
82 Interrupt Enable */
83
84#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
85#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
86
87#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
88#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
89#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
90#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
91#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
92#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
93#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
94#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
95#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
96#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
97#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
98#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
99#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
100#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */
101
102#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
103#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
104#define UDCCSR0_SA (1 << 7) /* Setup Active */
105#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
106#define UDCCSR0_FST (1 << 5) /* Force Stall */
107#define UDCCSR0_SST (1 << 4) /* Sent Stall */
108#define UDCCSR0_DME (1 << 3) /* DMA Enable */
109#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
110#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
111#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
112
113#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
114#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
115#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
116#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
117#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
118#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
119#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
120#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
121#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
122#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
123#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
124#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
125#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
126#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
127#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
128#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
129#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
130#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
131#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
132#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
133#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
134#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
135#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
136
137#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
138#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
139#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
140#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
141#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
142#define UDCCSR_FST (1 << 5) /* Force STALL */
143#define UDCCSR_SST (1 << 4) /* Sent STALL */
144#define UDCCSR_DME (1 << 3) /* DMA Enable */
145#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
146#define UDCCSR_PC (1 << 1) /* Packet Complete */
147#define UDCCSR_FS (1 << 0) /* FIFO needs service */
148
149#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
150#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
151#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
152#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
153#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
154#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
155#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
156#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
157#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
158#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
159#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
160#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
161#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
162#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
163#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
164#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
165#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
166#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
167#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
168#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
169#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
170#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
171#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
172#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
173#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
174
175#define UDCDN(x) __REG2(0x40600300, (x)<<2)
176#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
177#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
178#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
179#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
180#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
181#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
182#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
183#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
184#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
185#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
186#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
187#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
188#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
189#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
190#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
191#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
192#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
193#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
194#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
195#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
196#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
197#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
198#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
199#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
200#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
201#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
202
203#define UDCCN(x) __REG2(0x40600400, (x)<<2)
204#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
205#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
206#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
207#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
208#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
209#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
210#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
211#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
212#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
213#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
214#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
215#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
216#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
217#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
218#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
219#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
220#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
221#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
222#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
223#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
224#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
225#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
226#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
227
228#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
229#define UDCCONR_CN_S (25)
230#define UDCCONR_IN (0x07 << 22) /* Interface Number */
231#define UDCCONR_IN_S (22)
232#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
233#define UDCCONR_AISN_S (19)
234#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
235#define UDCCONR_EN_S (15)
236#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
237#define UDCCONR_ET_S (13)
238#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
239#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
240#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
241#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
242#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
243#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
244#define UDCCONR_MPS_S (2)
245#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
246#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
247
248
249#define UDC_INT_FIFOERROR (0x2)
250#define UDC_INT_PACKETCMP (0x1)
251
252#define UDC_FNR_MASK (0x7ff)
253
254#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
255#define UDC_BCR_MASK (0x3ff)
256
257#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
index b81cd63cb2eb..6ef1dd09970b 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_ARCH_PXA2XX_GPIO_H 1#ifndef __ASM_ARCH_PXA2XX_GPIO_H
2#define __ASM_ARCH_PXA2XX_GPIO_H 2#define __ASM_ARCH_PXA2XX_GPIO_H
3 3
4#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
5
4/* GPIO alternate function assignments */ 6/* GPIO alternate function assignments */
5 7
6#define GPIO1_RST 1 /* reset */ 8#define GPIO1_RST 1 /* reset */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
index 9553b54fa5bc..73e0a329cf7f 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -81,4 +81,166 @@
81 81
82#endif 82#endif
83 83
84
85/*
86 * Power Manager
87 */
88
89#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
90#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
91#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
92#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
93#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
94#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
95#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
96#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
97#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
98#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
99#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
100#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
101#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
102
103#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
104#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
105#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
106#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
107#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
108#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
109#define PCMD(x) __REG2(0x40F00080, (x)<<2)
110#define PCMD0 __REG(0x40F00080 + 0 * 4)
111#define PCMD1 __REG(0x40F00080 + 1 * 4)
112#define PCMD2 __REG(0x40F00080 + 2 * 4)
113#define PCMD3 __REG(0x40F00080 + 3 * 4)
114#define PCMD4 __REG(0x40F00080 + 4 * 4)
115#define PCMD5 __REG(0x40F00080 + 5 * 4)
116#define PCMD6 __REG(0x40F00080 + 6 * 4)
117#define PCMD7 __REG(0x40F00080 + 7 * 4)
118#define PCMD8 __REG(0x40F00080 + 8 * 4)
119#define PCMD9 __REG(0x40F00080 + 9 * 4)
120#define PCMD10 __REG(0x40F00080 + 10 * 4)
121#define PCMD11 __REG(0x40F00080 + 11 * 4)
122#define PCMD12 __REG(0x40F00080 + 12 * 4)
123#define PCMD13 __REG(0x40F00080 + 13 * 4)
124#define PCMD14 __REG(0x40F00080 + 14 * 4)
125#define PCMD15 __REG(0x40F00080 + 15 * 4)
126#define PCMD16 __REG(0x40F00080 + 16 * 4)
127#define PCMD17 __REG(0x40F00080 + 17 * 4)
128#define PCMD18 __REG(0x40F00080 + 18 * 4)
129#define PCMD19 __REG(0x40F00080 + 19 * 4)
130#define PCMD20 __REG(0x40F00080 + 20 * 4)
131#define PCMD21 __REG(0x40F00080 + 21 * 4)
132#define PCMD22 __REG(0x40F00080 + 22 * 4)
133#define PCMD23 __REG(0x40F00080 + 23 * 4)
134#define PCMD24 __REG(0x40F00080 + 24 * 4)
135#define PCMD25 __REG(0x40F00080 + 25 * 4)
136#define PCMD26 __REG(0x40F00080 + 26 * 4)
137#define PCMD27 __REG(0x40F00080 + 27 * 4)
138#define PCMD28 __REG(0x40F00080 + 28 * 4)
139#define PCMD29 __REG(0x40F00080 + 29 * 4)
140#define PCMD30 __REG(0x40F00080 + 30 * 4)
141#define PCMD31 __REG(0x40F00080 + 31 * 4)
142
143#define PCMD_MBC (1<<12)
144#define PCMD_DCE (1<<11)
145#define PCMD_LC (1<<10)
146/* FIXME: PCMD_SQC need be checked. */
147#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
148 bit 9 should be 0 all day. */
149#define PVCR_VCSA (0x1<<14)
150#define PVCR_CommandDelay (0xf80)
151#define PCFR_PI2C_EN (0x1 << 6)
152
153#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
154#define PSSR_RDH (1 << 5) /* Read Disable Hold */
155#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
156#define PSSR_STS (1 << 3) /* Standby Mode Status */
157#define PSSR_VFS (1 << 2) /* VDD Fault Status */
158#define PSSR_BFS (1 << 1) /* Battery Fault Status */
159#define PSSR_SSS (1 << 0) /* Software Sleep Status */
160
161#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
162
163#define PCFR_RO (1 << 15) /* RDH Override */
164#define PCFR_PO (1 << 14) /* PH Override */
165#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
166#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
167#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
168#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
169#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
170#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
171#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
172#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
173#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
174#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
175
176#define RCSR_GPR (1 << 3) /* GPIO Reset */
177#define RCSR_SMR (1 << 2) /* Sleep Mode */
178#define RCSR_WDR (1 << 1) /* Watchdog Reset */
179#define RCSR_HWR (1 << 0) /* Hardware Reset */
180
181#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
182#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
183#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
184#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
185#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
186#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
187#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
188#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
189#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
190#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
191#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
192#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
193#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
194#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
195#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
196#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
197#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
198#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
199
200/*
201 * PXA2xx specific Core clock definitions
202 */
203#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
204#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
205#define CKEN __REG(0x41300004) /* Clock Enable Register */
206#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
207
208#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
209#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
210#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
211
212#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
213#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
214#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
215#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
216#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
217#define CKEN_IM (20) /* Internal Memory Clock Enable */
218#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
219#define CKEN_USIM (18) /* USIM Unit Clock Enable */
220#define CKEN_MSL (17) /* MSL Unit Clock Enable */
221#define CKEN_LCD (16) /* LCD Unit Clock Enable */
222#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
223#define CKEN_I2C (14) /* I2C Unit Clock Enable */
224#define CKEN_FICP (13) /* FICP Unit Clock Enable */
225#define CKEN_MMC (12) /* MMC Unit Clock Enable */
226#define CKEN_USB (11) /* USB Unit Clock Enable */
227#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
228#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
229#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
230#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
231#define CKEN_I2S (8) /* I2S Unit Clock Enable */
232#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
233#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
234#define CKEN_STUART (5) /* STUART Unit Clock Enable */
235#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
236#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
237#define CKEN_SSP (3) /* SSP Unit Clock Enable */
238#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
239#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
240#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
241#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
242
243#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
244#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
245
84#endif 246#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
index 3459fb26ce97..2206cb61a9f9 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h
@@ -41,4 +41,6 @@ struct pxa2xx_spi_chip {
41 void (*cs_control)(u32 command); 41 void (*cs_control)(u32 command);
42}; 42};
43 43
44extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
45
44#endif /*PXA2XX_SPI_H_*/ 46#endif /*PXA2XX_SPI_H_*/
diff --git a/include/asm-arm/arch-pxa/pxa3xx_nand.h b/include/asm-arm/arch-pxa/pxa3xx_nand.h
index 81a8937486cb..eb4b190b6657 100644
--- a/include/asm-arm/arch-pxa/pxa3xx_nand.h
+++ b/include/asm-arm/arch-pxa/pxa3xx_nand.h
@@ -15,4 +15,6 @@ struct pxa3xx_nand_platform_data {
15 struct mtd_partition *parts; 15 struct mtd_partition *parts;
16 unsigned int nr_parts; 16 unsigned int nr_parts;
17}; 17};
18
19extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
18#endif /* __ASM_ARCH_PXA3XX_NAND_H */ 20#endif /* __ASM_ARCH_PXA3XX_NAND_H */
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
index bbd22396841a..daf018d0c604 100644
--- a/include/asm-arm/arch-pxa/pxafb.h
+++ b/include/asm-arm/arch-pxa/pxafb.h
@@ -71,7 +71,8 @@ struct pxafb_mode_info {
71 71
72 u_char bpp; 72 u_char bpp;
73 u_int cmap_greyscale:1, 73 u_int cmap_greyscale:1,
74 unused:31; 74 depth:8,
75 unused:23;
75 76
76 /* Parallel Mode Timing */ 77 /* Parallel Mode Timing */
77 u_char hsync_len; 78 u_char hsync_len;
diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h
index 3ba464c913a5..820a189684a9 100644
--- a/include/asm-arm/arch-pxa/regs-lcd.h
+++ b/include/asm-arm/arch-pxa/regs-lcd.h
@@ -27,6 +27,12 @@
27#define LCCR3_4BPP (2 << 24) 27#define LCCR3_4BPP (2 << 24)
28#define LCCR3_8BPP (3 << 24) 28#define LCCR3_8BPP (3 << 24)
29#define LCCR3_16BPP (4 << 24) 29#define LCCR3_16BPP (4 << 24)
30#define LCCR3_18BPP (5 << 24)
31#define LCCR3_18BPP_P (6 << 24)
32#define LCCR3_19BPP (7 << 24)
33#define LCCR3_19BPP_P (1 << 29)
34#define LCCR3_24BPP ((1 << 29) | (1 << 24))
35#define LCCR3_25BPP ((1 << 29) | (2 << 24))
30 36
31#define LCCR3_PDFOR_0 (0 << 30) 37#define LCCR3_PDFOR_0 (0 << 30)
32#define LCCR3_PDFOR_1 (1 << 30) 38#define LCCR3_PDFOR_1 (1 << 30)
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
index 0255328c3c18..3c04cde2cf1f 100644
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -20,6 +20,10 @@
20#define SSTSS (0x38) /* SSP Timeslot Status */ 20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */ 21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22 22
23#if defined(CONFIG_PXA3xx)
24#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
25#endif
26
23/* Common PXA2xx bits first */ 27/* Common PXA2xx bits first */
24#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ 28#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
25#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ 29#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
@@ -29,10 +33,12 @@
29#define SSCR0_National (0x2 << 4) /* National Microwire */ 33#define SSCR0_National (0x2 << 4) /* National Microwire */
30#define SSCR0_ECS (1 << 6) /* External clock select */ 34#define SSCR0_ECS (1 << 6) /* External clock select */
31#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ 35#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
36
32#if defined(CONFIG_PXA25x) 37#if defined(CONFIG_PXA25x)
33#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ 38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
34#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ 39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
35#elif defined(CONFIG_PXA27x) 40
41#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
36#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ 42#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
37#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ 43#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
38#define SSCR0_EDSS (1 << 20) /* Extended data size select */ 44#define SSCR0_EDSS (1 << 20) /* Extended data size select */
@@ -45,6 +51,10 @@
45#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ 51#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
46#endif 52#endif
47 53
54#if defined(CONFIG_PXA3xx)
55#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
56#endif
57
48#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ 58#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
49#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ 59#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
50#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ 60#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
@@ -109,5 +119,9 @@
109#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ 119#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
110#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ 120#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
111#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ 121#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
122#if defined(CONFIG_PXA3xx)
123#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
124#endif
125
112 126
113#endif /* __ASM_ARCH_REGS_SSP_H */ 127#endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index 9aa6c2e939e8..6956fc5235f8 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -12,6 +12,7 @@
12 12
13#include <asm/proc-fns.h> 13#include <asm/proc-fns.h>
14#include "hardware.h" 14#include "hardware.h"
15#include "pxa2xx-regs.h"
15#include "pxa-regs.h" 16#include "pxa-regs.h"
16 17
17static inline void arch_idle(void) 18static inline void arch_idle(void)
@@ -20,19 +21,4 @@ static inline void arch_idle(void)
20} 21}
21 22
22 23
23static inline void arch_reset(char mode) 24void arch_reset(char mode);
24{
25 if (cpu_is_pxa2xx())
26 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
27
28 if (mode == 's') {
29 /* Jump into ROM at address 0 */
30 cpu_reset(0);
31 } else {
32 /* Initialize the watchdog and let it fire */
33 OWER = OWER_WME;
34 OSSR = OSSR_M3;
35 OSMR3 = OSCR + 368640; /* ... in 100 ms */
36 }
37}
38
diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h
index c5b6fde6907c..a72803f0461b 100644
--- a/include/asm-arm/arch-pxa/tosa.h
+++ b/include/asm-arm/arch-pxa/tosa.h
@@ -25,21 +25,18 @@
25 */ 25 */
26#define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO 26#define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO
27#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 27#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11
28#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12 28#define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1)
29#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) 29#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2)
30#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3) 30#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3)
31#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4) 31#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4)
32#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 32#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16
33#define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17 33#define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6)
34#define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18 34#define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7)
35#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 35#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19
36 36
37/* GPIO Direction 1 : output mode / 0:input mode */ 37/* GPIO Direction 1 : output mode / 0:input mode */
38#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \ 38#define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \
39 TOSA_SCOOP_AUD_PWR_ON |\ 39 TOSA_SCOOP_AUD_PWR_ON)
40 TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
41/* GPIO out put level when init 1: Hi */
42#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN )
43 40
44/* 41/*
45 * SCOOP2 jacket GPIOs 42 * SCOOP2 jacket GPIOs
@@ -49,16 +46,34 @@
49#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) 46#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1)
50#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) 47#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2)
51#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3) 48#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3)
52#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15 49#define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4)
53#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16 50#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5)
54#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 51#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17
55#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7) 52#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7)
56#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 53#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19
57 54
58/* GPIO Direction 1 : output mode / 0:input mode */ 55/* GPIO Direction 1 : output mode / 0:input mode */
59#define TOSA_SCOOP_JC_IO_DIR ( \ 56#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL)
60 TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \ 57
61 TOSA_SCOOP_JC_CARD_LIMIT_SEL ) 58/*
59 * TC6393XB GPIOs
60 */
61#define TOSA_TC6393XB_GPIO_BASE (NR_BUILTIN_GPIO + 2 * 12)
62#define TOSA_TC6393XB_GPIO(i) (TOSA_TC6393XB_GPIO_BASE + (i))
63#define TOSA_TC6393XB_GPIO_BIT(gpio) (1 << (gpio - TOSA_TC6393XB_GPIO_BASE))
64
65#define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0)
66#define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1)
67#define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3)
68#define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4)
69#define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6)
70#define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7)
71#define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9)
72#define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10)
73#define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11)
74#define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12)
75#define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14)
76#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15)
62 77
63/* 78/*
64 * Timing Generator 79 * Timing Generator
@@ -84,13 +99,13 @@
84#define TOSA_GPIO_JACKET_DETECT (7) 99#define TOSA_GPIO_JACKET_DETECT (7)
85#define TOSA_GPIO_nSD_DETECT (9) 100#define TOSA_GPIO_nSD_DETECT (9)
86#define TOSA_GPIO_nSD_INT (10) 101#define TOSA_GPIO_nSD_INT (10)
87#define TOSA_GPIO_TC6393_CLK (11) 102#define TOSA_GPIO_TC6393XB_CLK (11)
88#define TOSA_GPIO_BAT1_CRG (12) 103#define TOSA_GPIO_BAT1_CRG (12)
89#define TOSA_GPIO_CF_CD (13) 104#define TOSA_GPIO_CF_CD (13)
90#define TOSA_GPIO_BAT0_CRG (14) 105#define TOSA_GPIO_BAT0_CRG (14)
91#define TOSA_GPIO_TC6393_INT (15) 106#define TOSA_GPIO_TC6393XB_INT (15)
92#define TOSA_GPIO_BAT0_LOW (17) 107#define TOSA_GPIO_BAT0_LOW (17)
93#define TOSA_GPIO_TC6393_RDY (18) 108#define TOSA_GPIO_TC6393XB_RDY (18)
94#define TOSA_GPIO_ON_RESET (19) 109#define TOSA_GPIO_ON_RESET (19)
95#define TOSA_GPIO_EAR_IN (20) 110#define TOSA_GPIO_EAR_IN (20)
96#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ 111#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */
@@ -99,6 +114,7 @@
99#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */ 114#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */
100#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */ 115#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */
101#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */ 116#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */
117#define TOSA_GPIO_IRDA_TX (47)
102#define TOSA_GPIO_TG_SPI_SCLK (81) 118#define TOSA_GPIO_TG_SPI_SCLK (81)
103#define TOSA_GPIO_TG_SPI_CS (82) 119#define TOSA_GPIO_TG_SPI_CS (82)
104#define TOSA_GPIO_TG_SPI_MOSI (83) 120#define TOSA_GPIO_TG_SPI_MOSI (83)
@@ -137,7 +153,7 @@
137#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) 153#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
138#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) 154#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD)
139#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) 155#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
140#define TOSA_IRQ_GPIO_TC6393_INT IRQ_GPIO(TOSA_GPIO_TC6393_INT) 156#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT)
141#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) 157#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
142#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) 158#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN)
143#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) 159#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ)
diff --git a/include/asm-arm/arch-pxa/tosa_bt.h b/include/asm-arm/arch-pxa/tosa_bt.h
new file mode 100644
index 000000000000..efc3c3d3b75d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/tosa_bt.h
@@ -0,0 +1,22 @@
1/*
2 * Tosa bluetooth built-in chip control.
3 *
4 * Later it may be shared with some other platforms.
5 *
6 * Copyright (c) 2008 Dmitry Baryshkov
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#ifndef TOSA_BT_H
14#define TOSA_BT_H
15
16struct tosa_bt_data {
17 int gpio_pwr;
18 int gpio_reset;
19};
20
21#endif
22
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index dadf4c20b622..f4551269aaf2 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -11,11 +11,11 @@
11 11
12#include <linux/serial_reg.h> 12#include <linux/serial_reg.h>
13#include <asm/arch/pxa-regs.h> 13#include <asm/arch/pxa-regs.h>
14#include <asm/mach-types.h>
14 15
15#define __REG(x) ((volatile unsigned long *)x) 16#define __REG(x) ((volatile unsigned long *)x)
16
17#define UART FFUART
18 17
18static volatile unsigned long *UART = FFUART;
19 19
20static inline void putc(char c) 20static inline void putc(char c)
21{ 21{
@@ -33,8 +33,13 @@ static inline void flush(void)
33{ 33{
34} 34}
35 35
36static inline void arch_decomp_setup(void)
37{
38 if (machine_is_littleton())
39 UART = STUART;
40}
41
36/* 42/*
37 * nothing to do 43 * nothing to do
38 */ 44 */
39#define arch_decomp_setup()
40#define arch_decomp_wdog() 45#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index 4881b80f0f90..0d35ca04731e 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -15,8 +15,9 @@ struct platform_mmc_slot {
15 15
16extern struct platform_mmc_slot zylonite_mmc_slot[]; 16extern struct platform_mmc_slot zylonite_mmc_slot[];
17 17
18extern int gpio_backlight;
19extern int gpio_eth_irq; 18extern int gpio_eth_irq;
19extern int gpio_debug_led1;
20extern int gpio_debug_led2;
20 21
21extern int wm9713_irq; 22extern int wm9713_irq;
22 23
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index b4da08d7a336..6bd2295c0e01 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -126,7 +126,7 @@ static inline unsigned sz __in##fnsuffix (unsigned int port) \
126 return (unsigned sz)value; \ 126 return (unsigned sz)value; \
127} 127}
128 128
129static inline void __iomem *__ioaddr(unsigned int port) 129static inline void __iomem *__deprecated __ioaddr(unsigned int port)
130{ 130{
131 void __iomem *ret; 131 void __iomem *ret;
132 if (__PORT_PCIO(port)) 132 if (__PORT_PCIO(port))
@@ -232,8 +232,7 @@ DECLARE_IO(int,l,"")
232 result; \ 232 result; \
233}) 233})
234 234
235#define __ioaddrc(port) \ 235#define __ioaddrc(port) __ioaddr(port)
236 ((__PORT_PCIO(port) ? PCIO_BASE : IO_BASE) + ((port) << 2))
237 236
238#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) 237#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
239#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) 238#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h
index 7583895fd336..18e10d2c35ea 100644
--- a/include/asm-arm/arch-s3c2410/gpio.h
+++ b/include/asm-arm/arch-s3c2410/gpio.h
@@ -1,68 +1,18 @@
1/* 1/* linux/include/asm-arm/arch-s3c2410/gpio.h
2 * linux/include/asm-arm/arch-s3c2410/gpio.h
3 * 2 *
4 * S3C2410 GPIO wrappers for arch-neutral GPIO calls 3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
5 * 6 *
6 * Written by Philipp Zabel <philipp.zabel@gmail.com> 7 * S3C2410 - GPIO lib support
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License version 2 as
10 * the Free Software Foundation; either version 2 of the License, or 11 * published by the Free Software Foundation.
11 * (at your option) any later version. 12*/
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __ASM_ARCH_S3C2410_GPIO_H
25#define __ASM_ARCH_S3C2410_GPIO_H
26
27#include <asm/irq.h>
28#include <asm/hardware.h>
29#include <asm/arch/regs-gpio.h>
30
31static inline int gpio_request(unsigned gpio, const char *label)
32{
33 return 0;
34}
35
36static inline void gpio_free(unsigned gpio)
37{
38 return;
39}
40
41static inline int gpio_direction_input(unsigned gpio)
42{
43 s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_INPUT);
44 return 0;
45}
46
47static inline int gpio_direction_output(unsigned gpio, int value)
48{
49 s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_OUTPUT);
50 /* REVISIT can we write the value first, to avoid glitching? */
51 s3c2410_gpio_setpin(gpio, value);
52 return 0;
53}
54
55#define gpio_get_value(gpio) s3c2410_gpio_getpin(gpio)
56#define gpio_set_value(gpio,value) s3c2410_gpio_setpin(gpio, value)
57
58#include <asm-generic/gpio.h> /* cansleep wrappers */
59
60#ifdef CONFIG_CPU_S3C2400
61#define gpio_to_irq(gpio) s3c2400_gpio_getirq(gpio)
62#else
63#define gpio_to_irq(gpio) s3c2410_gpio_getirq(gpio)
64#endif
65 13
66/* FIXME implement irq_to_gpio() */ 14#define gpio_get_value __gpio_get_value
15#define gpio_set_value __gpio_set_value
16#define gpio_cansleep __gpio_cansleep
67 17
68#endif 18#include <asm-generic/gpio.h>
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index ecae9e7f5e45..37661358b42b 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -189,6 +189,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
189#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) 189#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
190#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) 190#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
191#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) 191#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
192#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
193#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
192 194
193#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ 195#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
194 196
diff --git a/include/asm-arm/arch-s3c2410/regs-sdi.h b/include/asm-arm/arch-s3c2410/regs-sdi.h
index bb9d30b72952..bfb222fa4abb 100644
--- a/include/asm-arm/arch-s3c2410/regs-sdi.h
+++ b/include/asm-arm/arch-s3c2410/regs-sdi.h
@@ -28,9 +28,15 @@
28#define S3C2410_SDIDCNT (0x30) 28#define S3C2410_SDIDCNT (0x30)
29#define S3C2410_SDIDSTA (0x34) 29#define S3C2410_SDIDSTA (0x34)
30#define S3C2410_SDIFSTA (0x38) 30#define S3C2410_SDIFSTA (0x38)
31
31#define S3C2410_SDIDATA (0x3C) 32#define S3C2410_SDIDATA (0x3C)
32#define S3C2410_SDIIMSK (0x40) 33#define S3C2410_SDIIMSK (0x40)
33 34
35#define S3C2440_SDIDATA (0x40)
36#define S3C2440_SDIIMSK (0x3C)
37
38#define S3C2440_SDICON_SDRESET (1<<8)
39#define S3C2440_SDICON_MMCCLOCK (1<<5)
34#define S3C2410_SDICON_BYTEORDER (1<<4) 40#define S3C2410_SDICON_BYTEORDER (1<<4)
35#define S3C2410_SDICON_SDIOIRQ (1<<3) 41#define S3C2410_SDICON_SDIOIRQ (1<<3)
36#define S3C2410_SDICON_RWAITEN (1<<2) 42#define S3C2410_SDICON_RWAITEN (1<<2)
@@ -42,7 +48,8 @@
42#define S3C2410_SDICMDCON_LONGRSP (1<<10) 48#define S3C2410_SDICMDCON_LONGRSP (1<<10)
43#define S3C2410_SDICMDCON_WAITRSP (1<<9) 49#define S3C2410_SDICMDCON_WAITRSP (1<<9)
44#define S3C2410_SDICMDCON_CMDSTART (1<<8) 50#define S3C2410_SDICMDCON_CMDSTART (1<<8)
45#define S3C2410_SDICMDCON_INDEX (0xff) 51#define S3C2410_SDICMDCON_SENDERHOST (1<<6)
52#define S3C2410_SDICMDCON_INDEX (0x3f)
46 53
47#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) 54#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12)
48#define S3C2410_SDICMDSTAT_CMDSENT (1<<11) 55#define S3C2410_SDICMDSTAT_CMDSENT (1<<11)
@@ -51,6 +58,9 @@
51#define S3C2410_SDICMDSTAT_XFERING (1<<8) 58#define S3C2410_SDICMDSTAT_XFERING (1<<8)
52#define S3C2410_SDICMDSTAT_INDEX (0xff) 59#define S3C2410_SDICMDSTAT_INDEX (0xff)
53 60
61#define S3C2440_SDIDCON_DS_BYTE (0<<22)
62#define S3C2440_SDIDCON_DS_HALFWORD (1<<22)
63#define S3C2440_SDIDCON_DS_WORD (2<<22)
54#define S3C2410_SDIDCON_IRQPERIOD (1<<21) 64#define S3C2410_SDIDCON_IRQPERIOD (1<<21)
55#define S3C2410_SDIDCON_TXAFTERRESP (1<<20) 65#define S3C2410_SDIDCON_TXAFTERRESP (1<<20)
56#define S3C2410_SDIDCON_RXAFTERCMD (1<<19) 66#define S3C2410_SDIDCON_RXAFTERCMD (1<<19)
@@ -59,6 +69,7 @@
59#define S3C2410_SDIDCON_WIDEBUS (1<<16) 69#define S3C2410_SDIDCON_WIDEBUS (1<<16)
60#define S3C2410_SDIDCON_DMAEN (1<<15) 70#define S3C2410_SDIDCON_DMAEN (1<<15)
61#define S3C2410_SDIDCON_STOP (1<<14) 71#define S3C2410_SDIDCON_STOP (1<<14)
72#define S3C2440_SDIDCON_DATSTART (1<<14)
62#define S3C2410_SDIDCON_DATMODE (3<<12) 73#define S3C2410_SDIDCON_DATMODE (3<<12)
63#define S3C2410_SDIDCON_BLKNUM (0x7ff) 74#define S3C2410_SDIDCON_BLKNUM (0x7ff)
64 75
@@ -68,6 +79,7 @@
68#define S3C2410_SDIDCON_XFER_RXSTART (2<<12) 79#define S3C2410_SDIDCON_XFER_RXSTART (2<<12)
69#define S3C2410_SDIDCON_XFER_TXSTART (3<<12) 80#define S3C2410_SDIDCON_XFER_TXSTART (3<<12)
70 81
82#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
71#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) 83#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12)
72 84
73#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) 85#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10)
@@ -82,10 +94,12 @@
82#define S3C2410_SDIDSTA_TXDATAON (1<<1) 94#define S3C2410_SDIDSTA_TXDATAON (1<<1)
83#define S3C2410_SDIDSTA_RXDATAON (1<<0) 95#define S3C2410_SDIDSTA_RXDATAON (1<<0)
84 96
97#define S3C2440_SDIFSTA_FIFORESET (1<<16)
98#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */
85#define S3C2410_SDIFSTA_TFDET (1<<13) 99#define S3C2410_SDIFSTA_TFDET (1<<13)
86#define S3C2410_SDIFSTA_RFDET (1<<12) 100#define S3C2410_SDIFSTA_RFDET (1<<12)
87#define S3C2410_SDIFSTA_TXHALF (1<<11) 101#define S3C2410_SDIFSTA_TFHALF (1<<11)
88#define S3C2410_SDIFSTA_TXEMPTY (1<<10) 102#define S3C2410_SDIFSTA_TFEMPTY (1<<10)
89#define S3C2410_SDIFSTA_RFLAST (1<<9) 103#define S3C2410_SDIFSTA_RFLAST (1<<9)
90#define S3C2410_SDIFSTA_RFFULL (1<<8) 104#define S3C2410_SDIFSTA_RFFULL (1<<8)
91#define S3C2410_SDIFSTA_RFHALF (1<<7) 105#define S3C2410_SDIFSTA_RFHALF (1<<7)
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index fce832820825..911393b2c6f0 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -56,6 +56,21 @@
56#endif 56#endif
57 57
58/* 58/*
59 * This can be used to enable code to cacheline align the destination
60 * pointer when bulk writing to memory. Experiments on StrongARM and
61 * XScale didn't show this a worthwhile thing to do when the cache is not
62 * set to write-allocate (this would need further testing on XScale when WA
63 * is used).
64 *
65 * On Feroceon there is much to gain however, regardless of cache mode.
66 */
67#ifdef CONFIG_CPU_FEROCEON
68#define CALGN(code...) code
69#else
70#define CALGN(code...)
71#endif
72
73/*
59 * Enable and disable interrupts 74 * Enable and disable interrupts
60 */ 75 */
61#if __LINUX_ARM_ARCH__ >= 6 76#if __LINUX_ARM_ARCH__ >= 6
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 759a97b56eed..70b0fe724b62 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -95,11 +95,7 @@
95#endif 95#endif
96 96
97#if defined(CONFIG_CPU_FEROCEON) 97#if defined(CONFIG_CPU_FEROCEON)
98# ifdef _CACHE 98# define MULTI_CACHE 1
99# define MULTI_CACHE 1
100# else
101# define _CACHE feroceon
102# endif
103#endif 99#endif
104 100
105#if defined(CONFIG_CPU_V6) 101#if defined(CONFIG_CPU_V6)
@@ -410,6 +406,13 @@ extern void flush_dcache_page(struct page *);
410 406
411extern void __flush_dcache_page(struct address_space *mapping, struct page *page); 407extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
412 408
409static inline void __flush_icache_all(void)
410{
411 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
412 :
413 : "r" (0));
414}
415
413#define ARCH_HAS_FLUSH_ANON_PAGE 416#define ARCH_HAS_FLUSH_ANON_PAGE
414static inline void flush_anon_page(struct vm_area_struct *vma, 417static inline void flush_anon_page(struct vm_area_struct *vma,
415 struct page *page, unsigned long vmaddr) 418 struct page *page, unsigned long vmaddr)
diff --git a/include/asm-arm/dyntick.h b/include/asm-arm/dyntick.h
deleted file mode 100644
index 19fab2d2b760..000000000000
--- a/include/asm-arm/dyntick.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASMARM_DYNTICK_H
2#define _ASMARM_DYNTICK_H
3
4#include <asm/mach/time.h>
5
6#endif /* _ASMARM_DYNTICK_H */
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
index 684fe0645239..5e22881a630d 100644
--- a/include/asm-arm/ecard.h
+++ b/include/asm-arm/ecard.h
@@ -85,19 +85,6 @@
85 85
86#define MAX_ECARDS 9 86#define MAX_ECARDS 9
87 87
88typedef enum { /* Cards address space */
89 ECARD_IOC,
90 ECARD_MEMC,
91 ECARD_EASI
92} card_type_t;
93
94typedef enum { /* Speed for ECARD_IOC space */
95 ECARD_SLOW = 0,
96 ECARD_MEDIUM = 1,
97 ECARD_FAST = 2,
98 ECARD_SYNC = 3
99} card_speed_t;
100
101struct ecard_id { /* Card ID structure */ 88struct ecard_id { /* Card ID structure */
102 unsigned short manufacturer; 89 unsigned short manufacturer;
103 unsigned short product; 90 unsigned short product;
@@ -190,16 +177,6 @@ struct in_chunk_dir {
190}; 177};
191 178
192/* 179/*
193 * ecard_claim: claim an expansion card entry
194 */
195#define ecard_claim(ec) ((ec)->claimed = 1)
196
197/*
198 * ecard_release: release an expansion card entry
199 */
200#define ecard_release(ec) ((ec)->claimed = 0)
201
202/*
203 * Read a chunk from an expansion card 180 * Read a chunk from an expansion card
204 * cd : where to put read data 181 * cd : where to put read data
205 * ec : expansion card info struct 182 * ec : expansion card info struct
@@ -209,18 +186,6 @@ struct in_chunk_dir {
209extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num); 186extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num);
210 187
211/* 188/*
212 * Obtain the address of a card. This returns the "old style" address
213 * and should no longer be used.
214 */
215static inline unsigned int __deprecated
216ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed)
217{
218 extern unsigned int __ecard_address(struct expansion_card *,
219 card_type_t, card_speed_t);
220 return __ecard_address(ec, type, speed);
221}
222
223/*
224 * Request and release ecard resources 189 * Request and release ecard resources
225 */ 190 */
226extern int ecard_request_resources(struct expansion_card *ec); 191extern int ecard_request_resources(struct expansion_card *ec);
diff --git a/include/asm-arm/ftrace.h b/include/asm-arm/ftrace.h
new file mode 100644
index 000000000000..584ef9a8e5a5
--- /dev/null
+++ b/include/asm-arm/ftrace.h
@@ -0,0 +1,14 @@
1#ifndef _ASM_ARM_FTRACE
2#define _ASM_ARM_FTRACE
3
4#ifdef CONFIG_FTRACE
5#define MCOUNT_ADDR ((long)(mcount))
6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
7
8#ifndef __ASSEMBLY__
9extern void mcount(void);
10#endif
11
12#endif
13
14#endif /* _ASM_ARM_FTRACE */
diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h
index a32b86ac62aa..af64676650a2 100644
--- a/include/asm-arm/hardware/iop3xx-adma.h
+++ b/include/asm-arm/hardware/iop3xx-adma.h
@@ -260,7 +260,7 @@ static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op)
260static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, 260static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
261 int *slots_per_op) 261 int *slots_per_op)
262{ 262{
263 static const int slot_count_table[] = { 0, 263 static const char slot_count_table[] = {
264 1, 1, 1, 1, /* 01 - 04 */ 264 1, 1, 1, 1, /* 01 - 04 */
265 2, 2, 2, 2, /* 05 - 08 */ 265 2, 2, 2, 2, /* 05 - 08 */
266 4, 4, 4, 4, /* 09 - 12 */ 266 4, 4, 4, 4, /* 09 - 12 */
@@ -270,7 +270,7 @@ static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
270 8, 8, 8, 8, /* 25 - 28 */ 270 8, 8, 8, 8, /* 25 - 28 */
271 8, 8, 8, 8, /* 29 - 32 */ 271 8, 8, 8, 8, /* 29 - 32 */
272 }; 272 };
273 *slots_per_op = slot_count_table[src_cnt]; 273 *slots_per_op = slot_count_table[src_cnt - 1];
274 return *slots_per_op; 274 return *slots_per_op;
275} 275}
276 276
diff --git a/include/asm-arm/hardware/iop3xx-gpio.h b/include/asm-arm/hardware/iop3xx-gpio.h
new file mode 100644
index 000000000000..0c9331f9ac24
--- /dev/null
+++ b/include/asm-arm/hardware/iop3xx-gpio.h
@@ -0,0 +1,73 @@
1/*
2 * linux/include/asm-arm/hardware/iop3xx-gpio.h
3 *
4 * IOP3xx GPIO wrappers
5 *
6 * Copyright (c) 2008 Arnaud Patard <arnaud.patard@rtp-net.org>
7 * Based on IXP4XX gpio.h file
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
26#define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
27
28#include <asm/hardware.h>
29#include <asm-generic/gpio.h>
30
31#define IOP3XX_N_GPIOS 8
32
33static inline int gpio_get_value(unsigned gpio)
34{
35 if (gpio > IOP3XX_N_GPIOS)
36 return __gpio_get_value(gpio);
37
38 return gpio_line_get(gpio);
39}
40
41static inline void gpio_set_value(unsigned gpio, int value)
42{
43 if (gpio > IOP3XX_N_GPIOS) {
44 __gpio_set_value(gpio, value);
45 return;
46 }
47 gpio_line_set(gpio, value);
48}
49
50static inline int gpio_cansleep(unsigned gpio)
51{
52 if (gpio < IOP3XX_N_GPIOS)
53 return 0;
54 else
55 return __gpio_cansleep(gpio);
56}
57
58/*
59 * The GPIOs are not generating any interrupt
60 * Note : manuals are not clear about this
61 */
62static inline int gpio_to_irq(int gpio)
63{
64 return -EINVAL;
65}
66
67static inline int irq_to_gpio(int gpio)
68{
69 return -EINVAL;
70}
71
72#endif
73
diff --git a/include/asm-arm/hw_irq.h b/include/asm-arm/hw_irq.h
index 98d594a973d6..f1a08a500604 100644
--- a/include/asm-arm/hw_irq.h
+++ b/include/asm-arm/hw_irq.h
@@ -6,15 +6,4 @@
6 6
7#include <asm/mach/irq.h> 7#include <asm/mach/irq.h>
8 8
9#if defined(CONFIG_NO_IDLE_HZ)
10# include <asm/dyntick.h>
11# define handle_dynamic_tick(action) \
12 if (!(action->flags & IRQF_TIMER) && system_timer->dyn_tick) { \
13 write_seqlock(&xtime_lock); \
14 if (system_timer->dyn_tick->state & DYN_TICK_ENABLED) \
15 system_timer->dyn_tick->handler(irq, NULL); \
16 write_sequnlock(&xtime_lock); \
17 }
18#endif
19
20#endif 9#endif
diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h
index 47fe34d692da..c8986bb99ed5 100644
--- a/include/asm-arm/kexec.h
+++ b/include/asm-arm/kexec.h
@@ -14,8 +14,6 @@
14 14
15#define KEXEC_ARCH KEXEC_ARCH_ARM 15#define KEXEC_ARCH KEXEC_ARCH_ARM
16 16
17#define KEXEC_BOOT_PARAMS_SIZE 1536
18
19#define KEXEC_ARM_ATAGS_OFFSET 0x1000 17#define KEXEC_ARM_ATAGS_OFFSET 0x1000
20#define KEXEC_ARM_ZIMAGE_OFFSET 0x8000 18#define KEXEC_ARM_ZIMAGE_OFFSET 0x8000
21 19
diff --git a/include/asm-arm/kgdb.h b/include/asm-arm/kgdb.h
new file mode 100644
index 000000000000..67af4b841984
--- /dev/null
+++ b/include/asm-arm/kgdb.h
@@ -0,0 +1,104 @@
1/*
2 * ARM KGDB support
3 *
4 * Author: Deepak Saxena <dsaxena@mvista.com>
5 *
6 * Copyright (C) 2002 MontaVista Software Inc.
7 *
8 */
9
10#ifndef __ARM_KGDB_H__
11#define __ARM_KGDB_H__
12
13#include <linux/ptrace.h>
14
15/*
16 * GDB assumes that we're a user process being debugged, so
17 * it will send us an SWI command to write into memory as the
18 * debug trap. When an SWI occurs, the next instruction addr is
19 * placed into R14_svc before jumping to the vector trap.
20 * This doesn't work for kernel debugging as we are already in SVC
21 * we would loose the kernel's LR, which is a bad thing. This
22 * is bad thing.
23 *
24 * By doing this as an undefined instruction trap, we force a mode
25 * switch from SVC to UND mode, allowing us to save full kernel state.
26 *
27 * We also define a KGDB_COMPILED_BREAK which can be used to compile
28 * in breakpoints. This is important for things like sysrq-G and for
29 * the initial breakpoint from trap_init().
30 *
31 * Note to ARM HW designers: Add real trap support like SH && PPC to
32 * make our lives much much simpler. :)
33 */
34#define BREAK_INSTR_SIZE 4
35#define GDB_BREAKINST 0xef9f0001
36#define KGDB_BREAKINST 0xe7ffdefe
37#define KGDB_COMPILED_BREAK 0xe7ffdeff
38#define CACHE_FLUSH_IS_SAFE 1
39
40#ifndef __ASSEMBLY__
41
42static inline void arch_kgdb_breakpoint(void)
43{
44 asm(".word 0xe7ffdeff");
45}
46
47extern void kgdb_handle_bus_error(void);
48extern int kgdb_fault_expected;
49
50#endif /* !__ASSEMBLY__ */
51
52/*
53 * From Kevin Hilman:
54 *
55 * gdb is expecting the following registers layout.
56 *
57 * r0-r15: 1 long word each
58 * f0-f7: unused, 3 long words each !!
59 * fps: unused, 1 long word
60 * cpsr: 1 long word
61 *
62 * Even though f0-f7 and fps are not used, they need to be
63 * present in the registers sent for correct processing in
64 * the host-side gdb.
65 *
66 * In particular, it is crucial that CPSR is in the right place,
67 * otherwise gdb will not be able to correctly interpret stepping over
68 * conditional branches.
69 */
70#define _GP_REGS 16
71#define _FP_REGS 8
72#define _EXTRA_REGS 2
73#define GDB_MAX_REGS (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
74
75#define KGDB_MAX_NO_CPUS 1
76#define BUFMAX 400
77#define NUMREGBYTES (GDB_MAX_REGS << 2)
78#define NUMCRITREGBYTES (32 << 2)
79
80#define _R0 0
81#define _R1 1
82#define _R2 2
83#define _R3 3
84#define _R4 4
85#define _R5 5
86#define _R6 6
87#define _R7 7
88#define _R8 8
89#define _R9 9
90#define _R10 10
91#define _FP 11
92#define _IP 12
93#define _SPT 13
94#define _LR 14
95#define _PC 15
96#define _CPSR (GDB_MAX_REGS - 1)
97
98/*
99 * So that we can denote the end of a frame for tracing,
100 * in the simple case:
101 */
102#define CFI_END_FRAME(func) __CFI_END_FRAME(_PC, _SPT, func)
103
104#endif /* __ASM_KGDB_H__ */
diff --git a/include/asm-arm/kprobes.h b/include/asm-arm/kprobes.h
index c042194d3ab5..b1a37876942d 100644
--- a/include/asm-arm/kprobes.h
+++ b/include/asm-arm/kprobes.h
@@ -59,6 +59,7 @@ struct kprobe_ctlblk {
59}; 59};
60 60
61void arch_remove_kprobe(struct kprobe *); 61void arch_remove_kprobe(struct kprobe *);
62void kretprobe_trampoline(void);
62 63
63int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr); 64int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr);
64int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr); 65int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr);
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 5dc357013b79..2fd36ea0130d 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -41,30 +41,8 @@ struct sys_timer {
41#ifndef CONFIG_GENERIC_TIME 41#ifndef CONFIG_GENERIC_TIME
42 unsigned long (*offset)(void); 42 unsigned long (*offset)(void);
43#endif 43#endif
44
45#ifdef CONFIG_NO_IDLE_HZ
46 struct dyn_tick_timer *dyn_tick;
47#endif
48};
49
50#ifdef CONFIG_NO_IDLE_HZ
51
52#define DYN_TICK_ENABLED (1 << 1)
53
54struct dyn_tick_timer {
55 spinlock_t lock;
56 unsigned int state; /* Current state */
57 int (*enable)(void); /* Enables dynamic tick */
58 int (*disable)(void); /* Disables dynamic tick */
59 void (*reprogram)(unsigned long); /* Reprograms the timer */
60 int (*handler)(int, void *);
61}; 44};
62 45
63void timer_dyn_reprogram(void);
64#else
65#define timer_dyn_reprogram() do { } while (0)
66#endif
67
68extern struct sys_timer *system_timer; 46extern struct sys_timer *system_timer;
69extern void timer_tick(void); 47extern void timer_tick(void);
70 48
diff --git a/include/asm-arm/mach/udc_pxa2xx.h b/include/asm-arm/mach/udc_pxa2xx.h
index f9f3606986c2..9e5ed7c0f27f 100644
--- a/include/asm-arm/mach/udc_pxa2xx.h
+++ b/include/asm-arm/mach/udc_pxa2xx.h
@@ -23,6 +23,7 @@ struct pxa2xx_udc_mach_info {
23 */ 23 */
24 bool gpio_vbus_inverted; 24 bool gpio_vbus_inverted;
25 u16 gpio_vbus; /* high == vbus present */ 25 u16 gpio_vbus; /* high == vbus present */
26 bool gpio_pullup_inverted;
26 u16 gpio_pullup; /* high == pullup activated */ 27 u16 gpio_pullup; /* high == pullup activated */
27}; 28};
28 29
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 6913d02ca5d6..91b9dfdfed52 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -97,6 +97,11 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
97#ifdef CONFIG_MMU 97#ifdef CONFIG_MMU
98 unsigned int cpu = smp_processor_id(); 98 unsigned int cpu = smp_processor_id();
99 99
100#ifdef CONFIG_SMP
101 /* check for possible thread migration */
102 if (!cpus_empty(next->cpu_vm_mask) && !cpu_isset(cpu, next->cpu_vm_mask))
103 __flush_icache_all();
104#endif
100 if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) { 105 if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) {
101 check_context(next); 106 check_context(next);
102 cpu_switch_mm(next->pgd, next); 107 cpu_switch_mm(next->pgd, next);
diff --git a/include/asm-arm/plat-orion/cache-feroceon-l2.h b/include/asm-arm/plat-orion/cache-feroceon-l2.h
new file mode 100644
index 000000000000..ba4e016d3ec0
--- /dev/null
+++ b/include/asm-arm/plat-orion/cache-feroceon-l2.h
@@ -0,0 +1,11 @@
1/*
2 * include/asm-arm/plat-orion/cache-feroceon-l2.h
3 *
4 * Copyright (C) 2008 Marvell Semiconductor
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11extern void __init feroceon_l2_init(int l2_wt_override);
diff --git a/include/asm-arm/plat-orion/mv_xor.h b/include/asm-arm/plat-orion/mv_xor.h
new file mode 100644
index 000000000000..c349e8ff5cc0
--- /dev/null
+++ b/include/asm-arm/plat-orion/mv_xor.h
@@ -0,0 +1,28 @@
1/*
2 * Marvell XOR platform device data definition file.
3 */
4
5#ifndef __ASM_PLAT_ORION_MV_XOR_H
6#define __ASM_PLAT_ORION_MV_XOR_H
7
8#include <linux/dmaengine.h>
9#include <linux/mbus.h>
10
11#define MV_XOR_SHARED_NAME "mv_xor_shared"
12#define MV_XOR_NAME "mv_xor"
13
14struct mbus_dram_target_info;
15
16struct mv_xor_platform_shared_data {
17 struct mbus_dram_target_info *dram;
18};
19
20struct mv_xor_platform_data {
21 struct platform_device *shared;
22 int hw_id;
23 dma_cap_mask_t cap_mask;
24 size_t pool_size;
25};
26
27
28#endif
diff --git a/include/asm-arm/plat-orion/orion_nand.h b/include/asm-arm/plat-orion/orion_nand.h
index ffd3852a0dd7..ad4ce94c1998 100644
--- a/include/asm-arm/plat-orion/orion_nand.h
+++ b/include/asm-arm/plat-orion/orion_nand.h
@@ -18,6 +18,7 @@ struct orion_nand_data {
18 u8 ale; /* address line number connected to ALE */ 18 u8 ale; /* address line number connected to ALE */
19 u8 cle; /* address line number connected to CLE */ 19 u8 cle; /* address line number connected to CLE */
20 u8 width; /* buswidth */ 20 u8 width; /* buswidth */
21 u8 chip_delay;
21}; 22};
22 23
23 24
diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h
index 6434ac685d21..e61b7bd97af5 100644
--- a/include/asm-arm/plat-orion/pcie.h
+++ b/include/asm-arm/plat-orion/pcie.h
@@ -14,6 +14,7 @@
14u32 orion_pcie_dev_id(void __iomem *base); 14u32 orion_pcie_dev_id(void __iomem *base);
15u32 orion_pcie_rev(void __iomem *base); 15u32 orion_pcie_rev(void __iomem *base);
16int orion_pcie_link_up(void __iomem *base); 16int orion_pcie_link_up(void __iomem *base);
17int orion_pcie_x4_mode(void __iomem *base);
17int orion_pcie_get_local_bus_nr(void __iomem *base); 18int orion_pcie_get_local_bus_nr(void __iomem *base);
18void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); 19void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
19void orion_pcie_setup(void __iomem *base, 20void orion_pcie_setup(void __iomem *base,
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index 8b0d594397b1..b5bc692f3489 100644
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -65,6 +65,15 @@
65#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) 65#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
66#define S3C2410_TCFG1_MUX0_MASK (15<<0) 66#define S3C2410_TCFG1_MUX0_MASK (15<<0)
67 67
68#define S3C2410_TCFG1_MUX_DIV2 (0<<0)
69#define S3C2410_TCFG1_MUX_DIV4 (1<<0)
70#define S3C2410_TCFG1_MUX_DIV8 (2<<0)
71#define S3C2410_TCFG1_MUX_DIV16 (3<<0)
72#define S3C2410_TCFG1_MUX_TCLK (4<<0)
73#define S3C2410_TCFG1_MUX_MASK (15<<0)
74
75#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
76
68/* for each timer, we have an count buffer, an compare buffer and 77/* for each timer, we have an count buffer, an compare buffer and
69 * an observation buffer 78 * an observation buffer
70*/ 79*/
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
index f9d6f0317bc1..badaac9d64a8 100644
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ b/include/asm-arm/plat-s3c24xx/devs.h
@@ -21,6 +21,8 @@ extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
21extern struct platform_device *s3c24xx_uart_devs[]; 21extern struct platform_device *s3c24xx_uart_devs[];
22extern struct platform_device *s3c24xx_uart_src[]; 22extern struct platform_device *s3c24xx_uart_src[];
23 23
24extern struct platform_device s3c_device_timer[];
25
24extern struct platform_device s3c_device_usb; 26extern struct platform_device s3c_device_usb;
25extern struct platform_device s3c_device_lcd; 27extern struct platform_device s3c_device_lcd;
26extern struct platform_device s3c_device_wdt; 28extern struct platform_device s3c_device_wdt;
@@ -36,11 +38,6 @@ extern struct platform_device s3c_device_spi1;
36 38
37extern struct platform_device s3c_device_nand; 39extern struct platform_device s3c_device_nand;
38 40
39extern struct platform_device s3c_device_timer0;
40extern struct platform_device s3c_device_timer1;
41extern struct platform_device s3c_device_timer2;
42extern struct platform_device s3c_device_timer3;
43
44extern struct platform_device s3c_device_usbgadget; 41extern struct platform_device s3c_device_usbgadget;
45 42
46/* s3c2440 specific devices */ 43/* s3c2440 specific devices */
diff --git a/include/asm-arm/plat-s3c24xx/mci.h b/include/asm-arm/plat-s3c24xx/mci.h
new file mode 100644
index 000000000000..2d0852ac3b27
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/mci.h
@@ -0,0 +1,15 @@
1#ifndef _ARCH_MCI_H
2#define _ARCH_MCI_H
3
4struct s3c24xx_mci_pdata {
5 unsigned int wprotect_invert : 1;
6 unsigned int detect_invert : 1; /* set => detect active high. */
7
8 unsigned int gpio_detect;
9 unsigned int gpio_wprotect;
10 unsigned long ocr_avail;
11 void (*set_power)(unsigned char power_mode,
12 unsigned short vdd);
13};
14
15#endif /* _ARCH_NCI_H */
diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h
deleted file mode 100644
index 1a5c9232a91e..000000000000
--- a/include/asm-arm/rtc.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * linux/include/asm-arm/rtc.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef ASMARM_RTC_H
11#define ASMARM_RTC_H
12
13struct module;
14
15struct rtc_ops {
16 struct module *owner;
17 int (*open)(void);
18 void (*release)(void);
19 int (*ioctl)(unsigned int, unsigned long);
20
21 int (*read_time)(struct rtc_time *);
22 int (*set_time)(struct rtc_time *);
23 int (*read_alarm)(struct rtc_wkalrm *);
24 int (*set_alarm)(struct rtc_wkalrm *);
25 int (*proc)(char *buf);
26};
27
28void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *);
29void rtc_update(unsigned long, unsigned long);
30int register_rtc(struct rtc_ops *);
31void unregister_rtc(struct rtc_ops *);
32
33static inline int rtc_periodic_alarm(struct rtc_time *tm)
34{
35 return (tm->tm_year == -1) ||
36 ((unsigned)tm->tm_mon >= 12) ||
37 ((unsigned)(tm->tm_mday - 1) >= 31) ||
38 ((unsigned)tm->tm_hour > 23) ||
39 ((unsigned)tm->tm_min > 59) ||
40 ((unsigned)tm->tm_sec > 59);
41}
42
43#endif
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index af99636db400..7fffa2404b8e 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -101,6 +101,9 @@ extern void platform_cpu_die(unsigned int cpu);
101extern int platform_cpu_kill(unsigned int cpu); 101extern int platform_cpu_kill(unsigned int cpu);
102extern void platform_cpu_enable(unsigned int cpu); 102extern void platform_cpu_enable(unsigned int cpu);
103 103
104extern void arch_send_call_function_single_ipi(int cpu);
105extern void arch_send_call_function_ipi(cpumask_t mask);
106
104/* 107/*
105 * Local timer interrupt handling function (can be IPI'ed). 108 * Local timer interrupt handling function (can be IPI'ed).
106 */ 109 */
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8c6bc1bb9d1a..909656c747ef 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -39,6 +39,7 @@
39#define TLB_V6_D_ASID (1 << 17) 39#define TLB_V6_D_ASID (1 << 17)
40#define TLB_V6_I_ASID (1 << 18) 40#define TLB_V6_I_ASID (1 << 18)
41 41
42#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
42#define TLB_DCLEAN (1 << 30) 43#define TLB_DCLEAN (1 << 30)
43#define TLB_WB (1 << 31) 44#define TLB_WB (1 << 31)
44 45
@@ -51,6 +52,7 @@
51 * v4 - ARMv4 without write buffer 52 * v4 - ARMv4 without write buffer
52 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction 53 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
53 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction 54 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
55 * fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
54 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction 56 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
55 */ 57 */
56#undef _TLB 58#undef _TLB
@@ -103,6 +105,23 @@
103# define v4wbi_always_flags (-1UL) 105# define v4wbi_always_flags (-1UL)
104#endif 106#endif
105 107
108#define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
109 TLB_V4_I_FULL | TLB_V4_D_FULL | \
110 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
111
112#ifdef CONFIG_CPU_TLB_FEROCEON
113# define fr_possible_flags fr_tlb_flags
114# define fr_always_flags fr_tlb_flags
115# ifdef _TLB
116# define MULTI_TLB 1
117# else
118# define _TLB v4wbi
119# endif
120#else
121# define fr_possible_flags 0
122# define fr_always_flags (-1UL)
123#endif
124
106#define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \ 125#define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \
107 TLB_V4_I_FULL | TLB_V4_D_FULL | \ 126 TLB_V4_I_FULL | TLB_V4_D_FULL | \
108 TLB_V4_D_PAGE) 127 TLB_V4_D_PAGE)
@@ -245,12 +264,14 @@ extern struct cpu_tlb_fns cpu_tlb;
245#define possible_tlb_flags (v3_possible_flags | \ 264#define possible_tlb_flags (v3_possible_flags | \
246 v4_possible_flags | \ 265 v4_possible_flags | \
247 v4wbi_possible_flags | \ 266 v4wbi_possible_flags | \
267 fr_possible_flags | \
248 v4wb_possible_flags | \ 268 v4wb_possible_flags | \
249 v6wbi_possible_flags) 269 v6wbi_possible_flags)
250 270
251#define always_tlb_flags (v3_always_flags & \ 271#define always_tlb_flags (v3_always_flags & \
252 v4_always_flags & \ 272 v4_always_flags & \
253 v4wbi_always_flags & \ 273 v4wbi_always_flags & \
274 fr_always_flags & \
254 v4wb_always_flags & \ 275 v4wb_always_flags & \
255 v6wbi_always_flags) 276 v6wbi_always_flags)
256 277
@@ -417,6 +438,11 @@ static inline void flush_pmd_entry(pmd_t *pmd)
417 if (tlb_flag(TLB_DCLEAN)) 438 if (tlb_flag(TLB_DCLEAN))
418 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" 439 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
419 : : "r" (pmd) : "cc"); 440 : : "r" (pmd) : "cc");
441
442 if (tlb_flag(TLB_L2CLEAN_FR))
443 asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
444 : : "r" (pmd) : "cc");
445
420 if (tlb_flag(TLB_WB)) 446 if (tlb_flag(TLB_WB))
421 dsb(); 447 dsb();
422} 448}
@@ -428,6 +454,10 @@ static inline void clean_pmd_entry(pmd_t *pmd)
428 if (tlb_flag(TLB_DCLEAN)) 454 if (tlb_flag(TLB_DCLEAN))
429 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" 455 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
430 : : "r" (pmd) : "cc"); 456 : : "r" (pmd) : "cc");
457
458 if (tlb_flag(TLB_L2CLEAN_FR))
459 asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
460 : : "r" (pmd) : "cc");
431} 461}
432 462
433#undef tlb_flag 463#undef tlb_flag
diff --git a/include/asm-arm/traps.h b/include/asm-arm/traps.h
index f1541afcf85c..aa399aec568e 100644
--- a/include/asm-arm/traps.h
+++ b/include/asm-arm/traps.h
@@ -24,4 +24,6 @@ static inline int in_exception_text(unsigned long ptr)
24 ptr < (unsigned long)&__exception_text_end; 24 ptr < (unsigned long)&__exception_text_end;
25} 25}
26 26
27extern void __init early_trap_init(void);
28
27#endif 29#endif