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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-07-27 05:10:58 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-07-27 05:10:58 -0400
commitdaf93dd55c48b65ab2f1907e0fc5ef994896c787 (patch)
tree38465ea53d1861c7583193b7bb031b20bf05c453 /include/asm-arm
parent6cab48602996cdbcb277375a8107d53e21e8c9b9 (diff)
[ARM] fix VIPT/VIVT macro optimisations, add comments
cacheflush.h was doing: ... VIVT only stuff ... VIPT only stuff ... VIVT or VIPT stuff which is clearly bogus - we would only ever use the "VIVT or VIPT" case when both VIVT and VIPT are not selected. Fix this. Add comments to each case, including noting the impossibility of correctly detecting the cache type of ARM926 and ARMv6 cores from the cache type register in the "VIVT or VIPT" case. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/cacheflush.h17
1 files changed, 13 insertions, 4 deletions
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 03cf1ee977b7..e68a1cbcc852 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -459,15 +459,19 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
459#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0) 459#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
460 460
461#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT) 461#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
462 462/*
463 * VIVT caches only
464 */
463#define cache_is_vivt() 1 465#define cache_is_vivt() 1
464#define cache_is_vipt() 0 466#define cache_is_vipt() 0
465#define cache_is_vipt_nonaliasing() 0 467#define cache_is_vipt_nonaliasing() 0
466#define cache_is_vipt_aliasing() 0 468#define cache_is_vipt_aliasing() 0
467#define icache_is_vivt_asid_tagged() 0 469#define icache_is_vivt_asid_tagged() 0
468 470
469#elif defined(CONFIG_CPU_CACHE_VIPT) 471#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
470 472/*
473 * VIPT caches only
474 */
471#define cache_is_vivt() 0 475#define cache_is_vivt() 0
472#define cache_is_vipt() 1 476#define cache_is_vipt() 1
473#define cache_is_vipt_nonaliasing() \ 477#define cache_is_vipt_nonaliasing() \
@@ -489,7 +493,12 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
489 }) 493 })
490 494
491#else 495#else
492 496/*
497 * VIVT or VIPT caches. Note that this is unreliable since ARM926
498 * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
499 * There's no way to tell from the CacheType register what type (!)
500 * the cache is.
501 */
493#define cache_is_vivt() \ 502#define cache_is_vivt() \
494 ({ \ 503 ({ \
495 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ 504 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \