diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2008-07-05 04:02:50 -0400 |
---|---|---|
committer | Robert Schwebel <r.schwebel@pengutronix.de> | 2008-07-05 04:02:50 -0400 |
commit | 90292ea60f1c730efb9fea02b2e12676da89ebef (patch) | |
tree | 514a820eca32b08b79864aeb5382d620d37b5d99 /include/asm-arm | |
parent | 07bd1a6cc7cbb3f373fbe49b204c6cde5e9155fc (diff) |
MXC: add io multiplexing functions for mx3
This patch adds functions to use the io multiplexer on mx3 platforms.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'include/asm-arm')
-rw-r--r-- | include/asm-arm/arch-mxc/iomux-mx3.h | 501 |
1 files changed, 501 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mxc/iomux-mx3.h b/include/asm-arm/arch-mxc/iomux-mx3.h new file mode 100644 index 000000000000..7509e7692f08 --- /dev/null +++ b/include/asm-arm/arch-mxc/iomux-mx3.h | |||
@@ -0,0 +1,501 @@ | |||
1 | /* | ||
2 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation; either version 2 | ||
8 | * of the License, or (at your option) any later version. | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
17 | * MA 02110-1301, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef __MACH_MX31_IOMUX_H__ | ||
21 | #define __MACH_MX31_IOMUX_H__ | ||
22 | |||
23 | #include <linux/types.h> | ||
24 | |||
25 | /* | ||
26 | * various IOMUX output functions | ||
27 | */ | ||
28 | |||
29 | #define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ | ||
30 | #define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ | ||
31 | #define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ | ||
32 | #define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ | ||
33 | #define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ | ||
34 | #define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ | ||
35 | #define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ | ||
36 | #define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ | ||
37 | #define IOMUX_ICONFIG_NONE 0 /* not configured for input */ | ||
38 | #define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ | ||
39 | #define IOMUX_ICONFIG_FUNC 2 /* used as function */ | ||
40 | #define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ | ||
41 | #define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ | ||
42 | |||
43 | #define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) | ||
44 | #define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) | ||
45 | #define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) | ||
46 | #define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) | ||
47 | |||
48 | /* | ||
49 | * various IOMUX pad functions | ||
50 | */ | ||
51 | enum iomux_pad_config { | ||
52 | PAD_CTL_NOLOOPBACK = 0x0 << 9, | ||
53 | PAD_CTL_LOOPBACK = 0x1 << 9, | ||
54 | PAD_CTL_PKE_NONE = 0x0 << 8, | ||
55 | PAD_CTL_PKE_ENABLE = 0x1 << 8, | ||
56 | PAD_CTL_PUE_KEEPER = 0x0 << 7, | ||
57 | PAD_CTL_PUE_PUD = 0x1 << 7, | ||
58 | PAD_CTL_100K_PD = 0x0 << 5, | ||
59 | PAD_CTL_100K_PU = 0x1 << 5, | ||
60 | PAD_CTL_47K_PU = 0x2 << 5, | ||
61 | PAD_CTL_22K_PU = 0x3 << 5, | ||
62 | PAD_CTL_HYS_CMOS = 0x0 << 4, | ||
63 | PAD_CTL_HYS_SCHMITZ = 0x1 << 4, | ||
64 | PAD_CTL_ODE_CMOS = 0x0 << 3, | ||
65 | PAD_CTL_ODE_OpenDrain = 0x1 << 3, | ||
66 | PAD_CTL_DRV_NORMAL = 0x0 << 1, | ||
67 | PAD_CTL_DRV_HIGH = 0x1 << 1, | ||
68 | PAD_CTL_DRV_MAX = 0x2 << 1, | ||
69 | PAD_CTL_SRE_SLOW = 0x0 << 0, | ||
70 | PAD_CTL_SRE_FAST = 0x1 << 0 | ||
71 | }; | ||
72 | |||
73 | /* | ||
74 | * various IOMUX general purpose functions | ||
75 | */ | ||
76 | enum iomux_gp_func { | ||
77 | MUX_PGP_FIRI = 1 << 0, | ||
78 | MUX_DDR_MODE = 1 << 1, | ||
79 | MUX_PGP_CSPI_BB = 1 << 2, | ||
80 | MUX_PGP_ATA_1 = 1 << 3, | ||
81 | MUX_PGP_ATA_2 = 1 << 4, | ||
82 | MUX_PGP_ATA_3 = 1 << 5, | ||
83 | MUX_PGP_ATA_4 = 1 << 6, | ||
84 | MUX_PGP_ATA_5 = 1 << 7, | ||
85 | MUX_PGP_ATA_6 = 1 << 8, | ||
86 | MUX_PGP_ATA_7 = 1 << 9, | ||
87 | MUX_PGP_ATA_8 = 1 << 10, | ||
88 | MUX_PGP_UH2 = 1 << 11, | ||
89 | MUX_SDCTL_CSD0_SEL = 1 << 12, | ||
90 | MUX_SDCTL_CSD1_SEL = 1 << 13, | ||
91 | MUX_CSPI1_UART3 = 1 << 14, | ||
92 | MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, | ||
93 | MUX_TAMPER_DETECT_EN = 1 << 16, | ||
94 | MUX_PGP_USB_4WIRE = 1 << 17, | ||
95 | MUX_PGB_USB_COMMON = 1 << 18, | ||
96 | MUX_SDHC_MEMSTICK1 = 1 << 19, | ||
97 | MUX_SDHC_MEMSTICK2 = 1 << 20, | ||
98 | MUX_PGP_SPLL_BYP = 1 << 21, | ||
99 | MUX_PGP_UPLL_BYP = 1 << 22, | ||
100 | MUX_PGP_MSHC1_CLK_SEL = 1 << 23, | ||
101 | MUX_PGP_MSHC2_CLK_SEL = 1 << 24, | ||
102 | MUX_CSPI3_UART5_SEL = 1 << 25, | ||
103 | MUX_PGP_ATA_9 = 1 << 26, | ||
104 | MUX_PGP_USB_SUSPEND = 1 << 27, | ||
105 | MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, | ||
106 | MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, | ||
107 | MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, | ||
108 | MUX_CLKO_DDR_MODE = 1 << 31, | ||
109 | }; | ||
110 | |||
111 | /* | ||
112 | * This function enables/disables the general purpose function for a particular | ||
113 | * signal. | ||
114 | */ | ||
115 | void iomux_config_gpr(enum iomux_gp_func , bool); | ||
116 | |||
117 | /* | ||
118 | * set the mode for a IOMUX pin. | ||
119 | */ | ||
120 | int mxc_iomux_mode(unsigned int); | ||
121 | |||
122 | /* | ||
123 | * This function enables/disables the general purpose function for a particular | ||
124 | * signal. | ||
125 | */ | ||
126 | void mxc_iomux_set_gpr(enum iomux_gp_func, bool); | ||
127 | |||
128 | #define IOMUX_PADNUM_MASK 0x1ff | ||
129 | #define IOMUX_GPIONUM_SHIFT 9 | ||
130 | #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) | ||
131 | #define IOMUX_MODE_SHIFT 17 | ||
132 | #define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT) | ||
133 | |||
134 | #define IOMUX_PIN(gpionum, padnum) \ | ||
135 | (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \ | ||
136 | (padnum & IOMUX_PADNUM_MASK)) | ||
137 | |||
138 | #define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT) | ||
139 | |||
140 | #define IOMUX_TO_GPIO(iomux_pin) \ | ||
141 | ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) | ||
142 | #define IOMUX_TO_IRQ(iomux_pin) \ | ||
143 | (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ | ||
144 | MXC_GPIO_INT_BASE) | ||
145 | |||
146 | /* | ||
147 | * This enumeration is constructed based on the Section | ||
148 | * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated | ||
149 | * value is constructed based on the rules described above. | ||
150 | */ | ||
151 | |||
152 | enum iomux_pins { | ||
153 | MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), | ||
154 | MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), | ||
155 | MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), | ||
156 | MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), | ||
157 | MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), | ||
158 | MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), | ||
159 | MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), | ||
160 | MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), | ||
161 | MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), | ||
162 | MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), | ||
163 | MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), | ||
164 | MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), | ||
165 | MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), | ||
166 | MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), | ||
167 | MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), | ||
168 | MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), | ||
169 | MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), | ||
170 | MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), | ||
171 | MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), | ||
172 | MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), | ||
173 | MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), | ||
174 | MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), | ||
175 | MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), | ||
176 | MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), | ||
177 | MX31_PIN_READ = IOMUX_PIN(0xff, 24), | ||
178 | MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), | ||
179 | MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), | ||
180 | MX31_PIN_SER_RS = IOMUX_PIN(89, 27), | ||
181 | MX31_PIN_LCS1 = IOMUX_PIN(88, 28), | ||
182 | MX31_PIN_LCS0 = IOMUX_PIN(87, 29), | ||
183 | MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), | ||
184 | MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), | ||
185 | MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), | ||
186 | MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), | ||
187 | MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), | ||
188 | MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), | ||
189 | MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), | ||
190 | MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), | ||
191 | MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), | ||
192 | MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), | ||
193 | MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), | ||
194 | MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), | ||
195 | MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), | ||
196 | MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), | ||
197 | MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), | ||
198 | MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), | ||
199 | MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), | ||
200 | MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), | ||
201 | MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), | ||
202 | MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), | ||
203 | MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), | ||
204 | MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), | ||
205 | MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), | ||
206 | MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), | ||
207 | MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), | ||
208 | MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), | ||
209 | MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), | ||
210 | MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), | ||
211 | MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), | ||
212 | MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), | ||
213 | MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), | ||
214 | MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), | ||
215 | MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), | ||
216 | MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), | ||
217 | MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), | ||
218 | MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), | ||
219 | MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), | ||
220 | MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), | ||
221 | MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), | ||
222 | MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), | ||
223 | MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), | ||
224 | MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), | ||
225 | MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), | ||
226 | MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), | ||
227 | MX31_PIN_USB_OC = IOMUX_PIN(30, 74), | ||
228 | MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), | ||
229 | MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), | ||
230 | MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), | ||
231 | MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), | ||
232 | MX31_PIN_TDO = IOMUX_PIN(0xff, 79), | ||
233 | MX31_PIN_TDI = IOMUX_PIN(0xff, 80), | ||
234 | MX31_PIN_TMS = IOMUX_PIN(0xff, 81), | ||
235 | MX31_PIN_TCK = IOMUX_PIN(0xff, 82), | ||
236 | MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), | ||
237 | MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), | ||
238 | MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), | ||
239 | MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), | ||
240 | MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), | ||
241 | MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), | ||
242 | MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), | ||
243 | MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), | ||
244 | MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), | ||
245 | MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), | ||
246 | MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), | ||
247 | MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), | ||
248 | MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), | ||
249 | MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), | ||
250 | MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), | ||
251 | MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), | ||
252 | MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), | ||
253 | MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), | ||
254 | MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), | ||
255 | MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), | ||
256 | MX31_PIN_TXD2 = IOMUX_PIN(28, 103), | ||
257 | MX31_PIN_RXD2 = IOMUX_PIN(27, 104), | ||
258 | MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), | ||
259 | MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), | ||
260 | MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), | ||
261 | MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), | ||
262 | MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), | ||
263 | MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), | ||
264 | MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), | ||
265 | MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), | ||
266 | MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), | ||
267 | MX31_PIN_CTS1 = IOMUX_PIN(39, 114), | ||
268 | MX31_PIN_RTS1 = IOMUX_PIN(38, 115), | ||
269 | MX31_PIN_TXD1 = IOMUX_PIN(37, 116), | ||
270 | MX31_PIN_RXD1 = IOMUX_PIN(36, 117), | ||
271 | MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), | ||
272 | MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), | ||
273 | MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), | ||
274 | MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), | ||
275 | MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), | ||
276 | MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), | ||
277 | MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), | ||
278 | MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), | ||
279 | MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), | ||
280 | MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), | ||
281 | MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), | ||
282 | MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), | ||
283 | MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), | ||
284 | MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), | ||
285 | MX31_PIN_SFS6 = IOMUX_PIN(26, 132), | ||
286 | MX31_PIN_SCK6 = IOMUX_PIN(25, 133), | ||
287 | MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), | ||
288 | MX31_PIN_STXD6 = IOMUX_PIN(23, 135), | ||
289 | MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), | ||
290 | MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), | ||
291 | MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), | ||
292 | MX31_PIN_STXD5 = IOMUX_PIN(21, 139), | ||
293 | MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), | ||
294 | MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), | ||
295 | MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), | ||
296 | MX31_PIN_STXD4 = IOMUX_PIN(19, 143), | ||
297 | MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), | ||
298 | MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), | ||
299 | MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), | ||
300 | MX31_PIN_STXD3 = IOMUX_PIN(17, 147), | ||
301 | MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), | ||
302 | MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), | ||
303 | MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), | ||
304 | MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), | ||
305 | MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), | ||
306 | MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), | ||
307 | MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), | ||
308 | MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), | ||
309 | MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), | ||
310 | MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), | ||
311 | MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), | ||
312 | MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), | ||
313 | MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), | ||
314 | MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), | ||
315 | MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), | ||
316 | MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), | ||
317 | MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), | ||
318 | MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), | ||
319 | MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), | ||
320 | MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), | ||
321 | MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), | ||
322 | MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), | ||
323 | MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), | ||
324 | MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), | ||
325 | MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), | ||
326 | MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), | ||
327 | MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), | ||
328 | MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), | ||
329 | MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), | ||
330 | MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), | ||
331 | MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), | ||
332 | MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), | ||
333 | MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), | ||
334 | MX31_PIN_D0 = IOMUX_PIN(0xff, 181), | ||
335 | MX31_PIN_D1 = IOMUX_PIN(0xff, 182), | ||
336 | MX31_PIN_D2 = IOMUX_PIN(0xff, 183), | ||
337 | MX31_PIN_D3 = IOMUX_PIN(0xff, 184), | ||
338 | MX31_PIN_D4 = IOMUX_PIN(0xff, 185), | ||
339 | MX31_PIN_D5 = IOMUX_PIN(0xff, 186), | ||
340 | MX31_PIN_D6 = IOMUX_PIN(0xff, 187), | ||
341 | MX31_PIN_D7 = IOMUX_PIN(0xff, 188), | ||
342 | MX31_PIN_D8 = IOMUX_PIN(0xff, 189), | ||
343 | MX31_PIN_D9 = IOMUX_PIN(0xff, 190), | ||
344 | MX31_PIN_D10 = IOMUX_PIN(0xff, 191), | ||
345 | MX31_PIN_D11 = IOMUX_PIN(0xff, 192), | ||
346 | MX31_PIN_D12 = IOMUX_PIN(0xff, 193), | ||
347 | MX31_PIN_D13 = IOMUX_PIN(0xff, 194), | ||
348 | MX31_PIN_D14 = IOMUX_PIN(0xff, 195), | ||
349 | MX31_PIN_D15 = IOMUX_PIN(0xff, 196), | ||
350 | MX31_PIN_NFRB = IOMUX_PIN(16, 197), | ||
351 | MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), | ||
352 | MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), | ||
353 | MX31_PIN_NFCLE = IOMUX_PIN(13, 200), | ||
354 | MX31_PIN_NFALE = IOMUX_PIN(12, 201), | ||
355 | MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), | ||
356 | MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), | ||
357 | MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), | ||
358 | MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), | ||
359 | MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), | ||
360 | MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), | ||
361 | MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), | ||
362 | MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), | ||
363 | MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), | ||
364 | MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), | ||
365 | MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), | ||
366 | MX31_PIN_CAS = IOMUX_PIN(0xff, 213), | ||
367 | MX31_PIN_RAS = IOMUX_PIN(0xff, 214), | ||
368 | MX31_PIN_RW = IOMUX_PIN(0xff, 215), | ||
369 | MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), | ||
370 | MX31_PIN_LBA = IOMUX_PIN(0xff, 217), | ||
371 | MX31_PIN_ECB = IOMUX_PIN(0xff, 218), | ||
372 | MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), | ||
373 | MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), | ||
374 | MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), | ||
375 | MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), | ||
376 | MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), | ||
377 | MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), | ||
378 | MX31_PIN_OE = IOMUX_PIN(0xff, 225), | ||
379 | MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), | ||
380 | MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), | ||
381 | MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), | ||
382 | MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), | ||
383 | MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), | ||
384 | MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), | ||
385 | MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), | ||
386 | MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), | ||
387 | MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), | ||
388 | MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), | ||
389 | MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), | ||
390 | MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), | ||
391 | MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), | ||
392 | MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), | ||
393 | MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), | ||
394 | MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), | ||
395 | MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), | ||
396 | MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), | ||
397 | MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), | ||
398 | MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), | ||
399 | MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), | ||
400 | MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), | ||
401 | MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), | ||
402 | MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), | ||
403 | MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), | ||
404 | MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), | ||
405 | MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), | ||
406 | MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), | ||
407 | MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), | ||
408 | MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), | ||
409 | MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), | ||
410 | MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), | ||
411 | MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), | ||
412 | MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), | ||
413 | MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), | ||
414 | MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), | ||
415 | MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), | ||
416 | MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), | ||
417 | MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), | ||
418 | MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), | ||
419 | MX31_PIN_A25 = IOMUX_PIN(0xff, 266), | ||
420 | MX31_PIN_A24 = IOMUX_PIN(0xff, 267), | ||
421 | MX31_PIN_A23 = IOMUX_PIN(0xff, 268), | ||
422 | MX31_PIN_A22 = IOMUX_PIN(0xff, 269), | ||
423 | MX31_PIN_A21 = IOMUX_PIN(0xff, 270), | ||
424 | MX31_PIN_A20 = IOMUX_PIN(0xff, 271), | ||
425 | MX31_PIN_A19 = IOMUX_PIN(0xff, 272), | ||
426 | MX31_PIN_A18 = IOMUX_PIN(0xff, 273), | ||
427 | MX31_PIN_A17 = IOMUX_PIN(0xff, 274), | ||
428 | MX31_PIN_A16 = IOMUX_PIN(0xff, 275), | ||
429 | MX31_PIN_A14 = IOMUX_PIN(0xff, 276), | ||
430 | MX31_PIN_A15 = IOMUX_PIN(0xff, 277), | ||
431 | MX31_PIN_A13 = IOMUX_PIN(0xff, 278), | ||
432 | MX31_PIN_A12 = IOMUX_PIN(0xff, 279), | ||
433 | MX31_PIN_A11 = IOMUX_PIN(0xff, 280), | ||
434 | MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), | ||
435 | MX31_PIN_A10 = IOMUX_PIN(0xff, 282), | ||
436 | MX31_PIN_A9 = IOMUX_PIN(0xff, 283), | ||
437 | MX31_PIN_A8 = IOMUX_PIN(0xff, 284), | ||
438 | MX31_PIN_A7 = IOMUX_PIN(0xff, 285), | ||
439 | MX31_PIN_A6 = IOMUX_PIN(0xff, 286), | ||
440 | MX31_PIN_A5 = IOMUX_PIN(0xff, 287), | ||
441 | MX31_PIN_A4 = IOMUX_PIN(0xff, 288), | ||
442 | MX31_PIN_A3 = IOMUX_PIN(0xff, 289), | ||
443 | MX31_PIN_A2 = IOMUX_PIN(0xff, 290), | ||
444 | MX31_PIN_A1 = IOMUX_PIN(0xff, 291), | ||
445 | MX31_PIN_A0 = IOMUX_PIN(0xff, 292), | ||
446 | MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), | ||
447 | MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), | ||
448 | MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), | ||
449 | MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), | ||
450 | MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), | ||
451 | MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), | ||
452 | MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), | ||
453 | MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), | ||
454 | MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), | ||
455 | MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), | ||
456 | MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), | ||
457 | MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), | ||
458 | MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), | ||
459 | MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), | ||
460 | MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), | ||
461 | MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), | ||
462 | MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), | ||
463 | MX31_PIN_SRX0 = IOMUX_PIN(34, 310), | ||
464 | MX31_PIN_STX0 = IOMUX_PIN(33, 311), | ||
465 | MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), | ||
466 | MX31_PIN_SRST0 = IOMUX_PIN(67, 313), | ||
467 | MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), | ||
468 | MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), | ||
469 | MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), | ||
470 | MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317), | ||
471 | MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318), | ||
472 | MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319), | ||
473 | MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320), | ||
474 | MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321), | ||
475 | MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322), | ||
476 | MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323), | ||
477 | MX31_PIN_PWMO = IOMUX_PIN( 9, 324), | ||
478 | MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), | ||
479 | MX31_PIN_COMPARE = IOMUX_PIN( 8, 326), | ||
480 | MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), | ||
481 | }; | ||
482 | |||
483 | /* | ||
484 | * Convenience values for use with mxc_iomux_mode() | ||
485 | * | ||
486 | * Format here is MX31_PIN_(pin name)__(function) | ||
487 | */ | ||
488 | #define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) | ||
489 | #define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) | ||
490 | #define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) | ||
491 | #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) | ||
492 | #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) | ||
493 | #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) | ||
494 | |||
495 | /* | ||
496 | * This function configures the pad value for a IOMUX pin. | ||
497 | */ | ||
498 | void mxc_iomux_set_pad(enum iomux_pins, u32); | ||
499 | |||
500 | #endif | ||
501 | |||